misc: Remove support for checking out as a mercurial repo.

This will still be technically possible with the right converters, but
this removes the tags, ignore file, and style checking hooks related to
mercurial. We no longer maintain a mercurial mirror of the main git
repository, and this support adds clutter and could diverge from the git
style hooks, etc, over time.

Change-Id: Icf4833c4f0fda51ea98989d1d741432ae3ddc6dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31174
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Fix VOP2 dissasembly prints

VOP2 prints VSRC1 register index as hex instead of decimal if the
instruction contains a literal operand.  This patch resets the
format specifiers in the stream to print the register correctly.

Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-gcn3, gpu-compute: Implement out-of-range accesses

Certain buffer out-of-range memory accesses should be special
cased and not generate memory accesses. This patch implements
those special cases and supresses lanes from accessing memory
when the calculated address falls in an ISA-specified out-of-range
condition.

Change-Id: I8298f861c6b59587789853a01e503ba7d98cb13d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29935
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-gcn3: Fix writelane src0,src1 usage

Src1 should only be used for lane select.  The data should come
from src0.

Change-Id: Ibe960df2e56d351a3819b40194104d2972a5cd4c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29933
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Dropping fetchs when no entry is reserved in the buffer

This changeset drops fetches if there is no entry reserved in the
fetch buffer for that instruction. This can happen due to a fetch
attempted to be issued in the same cycle where a branch instruction
flushed the fetch buffer, while an ITLB or I-cache request is still
pending.

Change-Id: I3b80dbd71af27ccf790b543bd5c034bb9b02624a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29932
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-gcn3: fix bits that SDWA selects

This commit fixes a bug in 200f2408 where the SDWA support was selecting bits
backwards.  As part of this commit, to help resolve this problem in the
future, I have added asserts in the helper functions in bitfield.hh to ensure
that the number of bits aren't negative.

Change-Id: I4b0ecb0e7c110600c0b5063101b75f9adcc512ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29931
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-arm: Fix coding style in self_debug.[cc, hh]

Change-Id: I67be98af412b745ea9e16d4e8c6d422c9fbb29fc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove getters/setters from SelfDebug class

Change-Id: I63e5ed25e453cb8fcb2c39ba0728cc81c499c166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31081
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix pmc == on SelfDebug

The Assignment operator was used instead of the Equal-To

Change-Id: Ibf5a0006bce79b67d662fd1f8942699582956d58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31080
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Move breakpoint/watchpoint check out of the TLB

The breakpoint, watchpoint, vector catch and software step checks
have been moved from the TLB to the SelfDebug class.

This is cleaningup the TLB model which is simply asking the SelfDebug
class if there is a pending debug fault

Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31079
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Style fixes for src/dev/arm/gic_v2.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I80dce7b72775beabafa3b54e915a369571f2e4c9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31057
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Implement Level Sensitive PPIs in GICv2

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I9ae411110f08f4a1de95469ff5ed6788354abafc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31056
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Use getIntConfig when reading/writing GICD_ICFGR

This patch is changing the getIntConfig helper (which has been
used so far by isLevelSensitive only) to make it usable by the
read/writes of the GICD_ICFGR register.

While the helper was previously returning the irq config bits
provided a single irq as an input, this new version is returning
the entire GICD_ICFGR word (read/writable)

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31055
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Move GICv2 intConfig for consistency

Every other helper is placed below the respective array storage

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31054
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Consolidate most of the StackTrace classes into a base class.

These classes are all basically empty now that Alpha has been deleted,
except in cases where the arch versions had copied versions of the Alpha
code.

This change pulls all the generic logic out of the arch versions, making
the arch versions much simpler and making it clearer what the core
functionality of the class is, and what parts are architecture specific
details.

In the future, the way the StackTrace class is instantiated should be
delegated to the Workload class so that ISA agnostic code doesn't need
to know about a particular ISA's StackTrace class, and so that
StackTrace logic can, at least theoretically, be specialized for a
particular workload. The way a stack trace is collected could vary from
OS to OS, for example.

Change-Id: Id8108f94e9fe8baf9b4056f2b6404571e9fa52f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30961
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Slightly modernize and simplify code in cpu/profile.(hh|cc).

Change-Id: Ideb104d20b333305ead2356cbfff2aac2e0173b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30960
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Initialized some variables

Some of the variables in pauth_helpers.cc
are uninitialized in certain control paths
which causes a compiler warning. We initialize
these to false since they should be updated
to the correct value in all valid code paths.

Change-Id: If34d7daaf2404c2cf014c7b4c0c2f979580f36b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31094
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add basic support for KVM_CAP_ARM_USER_IRQ

KVM_CAP_ARM_USER_IRQ is a KVM extension introduced in newer versions of
Linux (>= 4.12). It supports delivering interrupt from the kernel-space
timer to the user-space GIC, which means that it will be unnecessary to
use the memory-mapped timer and emulate it in gem5 anymore.

Using the option provided by this change, Linux is able to boot with 1
CPU successfully, and the speed is slightly faster then the memory-
mapped timer option. However, multicore seems to hang during boot and
still needs more investigation to be enabled.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: I146bbcce3cf66f8f5ebee04ea5f1b9f54868721a
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30921
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-kvm,arch-arm: Improve KvmCPU tick event scheduling

The memory-mapped timer emulated by gem5 is driven by the underlying
gem5 tick, which means that we must align the tick with the host time
to make the timer interrupt fire at a nearly native rate.

In each KVM execution round, the number of ticks incremented is
directly calculated from the number of instructions executed. However,
when a guest CPU switches to idle state, KVM seems to stay in kernel-
space until the POSIX timer set up in user-space raises an expiration
signal, instead of trapping to user-space immediately; and somehow the
instruction count is just too low to match the elapsed host time. This
makes the gem5 tick increment very slowly when the guest is idle and
drastically slow down workloads being sensitive to the guest time which
is driven by timer interrupt.

Before switching to KVM to execute the guest code, gem5 programs the
POSIX timer to expire according to the remaining ticks before the next
event in the event queue. Based on this, we can come up with the
following solution: If KVM returns to user-space due to POSIX timer
expiration, it must be time to process the next gem5 event, so we just
fast-forward the tick (by scheduling the next CPU tick event) to that
event directly without calculating from the instruction count.

There is one more related issue needed to be solved. The KVM exit
reason, KVM_EXIT_INTR, was treated as the case where the KVM execution
was disturbed by POSIX timer expiration. However, there exists a case
where the exit reason is KVM_EXIT_INTR but the POSIX timer has not
expired. Its cause is still unknown, but it can be observed via the
"old_value" argument returned by timer_settime() when disarming the
POSIX timer. In addition, it seems to happen often when a guest CPU is
not in idle state. When this happens, the above tick event scheduling
incorrectly treats KVM_EXIT_INTR as POSIX timer expiration and fast-
forwards the tick to process the next event too early. This makes the
guest feel external events come too fast, and will sometimes cause
trouble. One example is the VSYNC interrupt from HDLCD. The guest seems
to get stuck in VSYNC handling if the KVM CPU is not given enough time
between each VSYNC interrupt to complete a service. (Honestly I did not
dig in to see how the guest handled the VSYNC interrupt and how the
above situation became trouble. I just observed from the debug trace of
GIC & HDLCD & timer, and made this conclusion.) This change also uses
a workaround to detect POSIX timer expiration correctly to make the
guest work with HDLCD.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: I6159238a36fc18c0c881d177a742d8a7745a23ca
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix handling of writing timer control registers

We should also deal with change of the imask bit, or we will lose timer
interrupt if the timer expires before the guest kernel unmasks the bit.
More precisely, consider the following common pattern in timer interrupt
handling:

    1. Set the interrupt mask bit (CNTV_CTL.IMASK)
    2. Reprogram the downcounter (CNTV_TVAL) for the next interrupt
    3. Clear the interrupt mask bit (CNTV_CTL.IMASK)

The timer can expires between step 2 & 3 if the value programmed in step
2 is small enough, and this seems very likely to happen in KVM mode. If
we don't check for timer expiration right after unmasking, we will miss
the only chance to inject the interrupt.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: I75e8253bb78d15ae72cb985ed132f896d8e92ca6
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30918
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-kvm: Initialize _hasKernelIRQChip in the constructor

This class member was only correctly set to true when using an in-kernel
interrupt controller, but was un-initialized when trying to use a user-
space one and would cause trouble.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: I71b052c6da7e8790b05a15c07e7933bc4f912785
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30917
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make generic timer work with level-sensitive support

Support for level-sensitive PPIs and SPIs has been added to GICv2 now.
It is therefore the timer's responsibility to notify GICv2 to clear its
interrupt pending state. Without doing this, the guest will get stuck
in just a single round of the interrupt handler because GICv2 does not
clear the pending state, and eventually make the guest treat this
interrupt as problematic and then just disable it.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: Ia8fd96bf00b28e91aa440274e6f8bb000446fbe3
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30916
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add earlycon to default kernel_cmd.

The earlyprintk kernel command line argument does not take a value on Arm.
Rather pass early console name using the earlycon command line argument.

Change-Id: Ie14fc425e87c50a0b59fa4270a3743ed4fe97589
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31074
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Optionally share the backing store

This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).

Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30994
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Don't use pseudo instructions to implement regular instructions.

Some ARM instructions were using quiesce and quiesceSkip pseudo
instruction bodies instead of implementing the one line of each of those
functions themselves. This creates two problems. First, it adds an
artificial depedence on the pseudo instruction implementations. Second,
it would confusing cause pseudo instruction DPRINTFs to fire when normal
instructions were executing.

This change simply replaces the calls with their targets one line
implementation, with some very minor duplication from multiple call
sights factored out into a local variable.

Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27790
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Verify number of CPUs when restoring Generic Timer Cpts.

When restoring a checkpoint containing a generic timer, the checkpoint
expects to connect the timer to the same number of CPUs that were
present when the checkpoint was taken. If the number of CPUs in the
new simulation is different, deserialization will fail. In the case
that the number of CPUs expected by the checkpoint is greater than the
number of CPUs present, this will cause a segmentation fault caused by
reading off the end of the list of Thread Contexts.

This commit fixes the problem by checking the number of CPUs present
in the simulation matches the number of CPUs expected by the generic
timer checkpoint. If there is a mismatch, a fatal error is triggered
with an informative message to the user.

Change-Id: Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30576
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented

The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28

Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30934
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface

The O3 model uses ReExec faults to flush the pipeline and restart
after a memory ordering violation, e.g. due to an incoming snoop.

These, just like branch mispredict flushes, are not architectural
faults but micro-architectural events, and should therefore not
show up on the instruction tracing interface.

This adds a check on faulting instructions in commit, to verify
if the instruction faulted due to ReExec, to avoid tracing it.

Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30554
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-arm: Fix routeToHyp conditions for Excp Type

Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30620
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix the indentation in arch/x86/stacktrace.hh.

The namespace shouldn't be indented.

Change-Id: I2bd5fa5adbbad62a35cfb54a9509c48d45076539
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30959
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Delete the unused ProcessInfo class.

Change-Id: Ie67f696005fa60e117e1e4e4e985aee5e767ccec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30958
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Delete util/batch, util/pbs, and util qdo.

The util/pbs directory has a set of python scripts which were written to
submit jobs to the PBS pool at the University of Michigan. They aren't
incredibly specialized for that environment, but they do have a little
bit of hard coding which, for instance, uses paths which are only
meaningful there.

The util/batch directory was added alongside a seemingly unrelated
change (perhaps by accident?) and is a slightly updated copy of util/pbs
which also (or instead?) supports OAR.

The qdo script seems to be a script for managing job queues on PBS
and/or OAR, and is also tuned to the UofM environment, for instance
insisting that a path starts with /n/poolfs so that files are available
on an NFS volume shared with the pool.

All three of these scripts could potentially be useful with modification
in a similar environment, but also all three are unmaintained. The
environment in UofM may no longer actually match the expectations of
these scripts, and even if it does/did, gem5 may no longer be 100%
compatible with them.

If these scripts sit in util not being used by anyone, they add clutter
and complexity without adding any value. If someone really needs to know
what was once in them, they can be recovered from revision control.

Change-Id: I0192bd119893f7a41fcb820f4cf408609b03cd27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30957
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add M5_VAR_USED to var used in dprint

Change-Id: I8f8654b8546ee8df3d4acd1ccbc5080ad38764c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30896
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove some unused vars from self_debug.hh

Change-Id: I68b4ddfe66a34a29c0abfd52a8448e0b8a5bbe94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30895
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add missing override to ARM faults

Change-Id: I7d64bdb4dfb0ba204e734f727b016bea168180ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30894
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add Check for AddressSize Fault

This patch add a check for AddressSize Fault during translation when
MMU is disabled.

Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30619
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Implementation of Vector Catch debug exception

This commit implements Vector Catch exception as they are described
in Armv8 reference manual chapter G2. This exception is just for AArch32.

+ tlb.cc: Implements the entry point for vector catch in addres mode
+ faults.hh/cc: Implements the entry point for vector catch in exception trap mode.
+ miscregs.cc: enables the use of vector catch releated registers
+ miscregs_types.hh: New bitwise type for vector catch control registers.
+ types.hh: declaration of EC for vector catch exception
+ self_debug.hh/cc: Main implementation of the vector catch functions to
                    match address and exceptions type.

Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30618
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Retrofit the VPtr type.

Rename it to be ProxyPtr and ConstProxyPtr, merge it with the
functionality of BufferArg and TypedBufferArg, etc., as described in
this design doc.

https://docs.google.com/document/d/1BYHBJcf7dB2Z25zAZ9snbeRKfstK9uERYH_3h66w_tc/

Change-Id: I2fddde20cc0ece257685bc50bd3419a4e9a00145
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29400
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Reverting version numbers

Change-Id: Ib423bf30e3a45c6e0c869499cd490851feeac5d1

misc: Merged m5ops_base hotfix into develop

This hotfix was a cherry-pick of
https://gem5-review.googlesource.com/c/public/gem5/+/30914.

Change-Id: Icb57bca196d8112d8b4457264b8e695cef0b1068

misc: Updated release notes and version number

Updated the release notes and version number for the v20.0.0.3
hot-fix.

Change-Id: I3fe8eda1e6859f76a91fbcee595426bd25bfe432
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30956
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove m5ops_base declaration from ArmSystem

This declaration should have been removed but was accidentally re-added.
It keeps m5ops_base from being passed correctly from Python to C++ when
using ARM ISA, and hence triggers gem5 crash when the guest tries to
call m5ops. This change removes it again to fix the crash.

JIRA: https://gem5.atlassian.net/browse/GEM5-658

Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30914
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(cherry picked from commit e3793fd8a9b7096a67a0f4260a36cd4dd5afe72f)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30955
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

cpu: Some cleanups in the O3 rename map.

Fix some style problems, mostly having to do with return type, but also
one with indentation.

Also simplify the very nested set of std::min-s into one.

Change-Id: I6dbb22128755d5b0c6bb71bd6f1b01e6234e2377
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30454
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Get rid of auto return types in the PhysRegFile.

This is a C++14 feature, where we only support up to C++11 currently. It
also unnecessarily obfuscates what these functions are doing, since the
return type is a simple and fixed.

Change-Id: I7459ed885c3f006edbcecd4c6be9835d77dbbbae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30434
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add .mailmap file

This file helps map committers' ids to a canonical name and email. This
is useful for tracking the same committer over time.

I've done my best to map the ids manually. I've tried to choose current
institutions/emails for the people that I personally know, but I am sure
to have missed many. Feel free to correct your own!

Change-Id: I17d57368a2ecb056025a6dabef37485ec5ce6aa9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29672
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove m5ops_base declaration from ArmSystem

This declaration should have been removed but was accidentally re-added.
It keeps m5ops_base from being passed correctly from Python to C++ when
using ARM ISA, and hence triggers gem5 crash when the guest tries to
call m5ops. This change removes it again to fix the crash.

JIRA: https://gem5.atlassian.net/browse/GEM5-658

Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30914
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Updated DTB warnings in fs.py for Arm platforms.

fs.py warns when an Arm platform is being created without a DTB file,
if the platform does not support the automatic creation of a DTB.

Updated the list of supported platforms with recent additions in order
to remove incorrect and potentially confusing warnings.

Change-Id: I549124a1afbc36e313f614dccab17973582bc3f7
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30575
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Implementation of SelfHosted Debug Software step

This commit implements SelfHosted Debug Software step as is defined in
Armv8 Reference manual chapter D2.

+ decoder.hh/cc/isa: Checks the software step bit in order to skip the instruction
              before its decode.
+ faults.hh/cc: implemented SoftwareStep exception and proper modification
                of spsr during the invoke of other exceptions
+ isa.cc: Set debug mask if needed during cpsr modification
+ tlb.cc: Checks if software step is in ACTIVE state to avoid trigger
          breakpoint or watchpoint exception
+ self_debug.hh/cc: Implementation of State change and ss bit based during eret.
+ types.hh: Define sofware step flags like step, load or stepped to check the different flags
        that triggering software step should use for the ISS code.
+ pseudo.hh/isa: Triggers the sofware step esception after decode.
+ static_inst.cc: Call debugExceptionReturnsSS durint eret routine.

Change-Id: I3a64507c64842c34c76ad7f6daa5f4306bd55d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30617
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Support device memories

Adds support for device memories in the system and RubySystem classes.
Devices may register memory ranges with the system class and packets
which originate from the device MasterID will update the device memory
in Ruby. In RubySystem functional access is updated to keep the packets
within the Ruby network they originated from.

Change-Id: I47850df1dc1994485d471ccd9da89e8d88eb0d20
JIRA: https://gem5.atlassian.net/browse/GEM5-470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29653
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

stats: add --stats-root option to dump only under some SimObjects

This commit makes it possible to make invocations such as:

gem5.opt se.py --stats-root 'system.cpu[:].dtb' --stats-root 'system.membus'

When --stats-root is given, only stats that are under any of the root
SimObjects get dumped. E.g. the above invocation would dump stats such as:

system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.membus.pwrStateResidencyTicks::UNDEFINED
system.membus.trans_dist::ReadReq

but not for example `system.clk_domain.clock`.

If the --stats-root is given, only new stats as defined at:
Idc8ff448b9f70a796427b4a5231e7371485130b4 get dumped, and old ones are
ignored. The commits following that one have done some initial conversion
work, but many stats are still in the old format.

Change-Id: Iadaef26edf9a678b39f774515600884fbaeec497
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Fix python3 incompatibility issue in slicc's HTML builder

In python3, an iterator does not have the next() method.
next(iterator) works in both python2.7+ and python3.

Change-Id: Ic1ceb993018a0f37e8d30086a054ffc2e311bb46
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30874
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Improve error message occurs when base couldn't open a file

Change-Id: Icaa571216f0eed4527a6aaddcf0c6814ad282c56
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30794
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implementation of ARMv8 SelfDebug Watchpoints

This change includes ArmV8 SelfDebug Watchpoint implementation
as is described in Armv8 Reference manual D2/G2
The changes specific descriptions are as follow:
+ ArmISA.py: Enable up to 16 DBGWn registers
+ isa.cc: Include in setMiscReg specific cases for DBGWCn registers enable bit
+ miscregs_types.hh: Define DBGWC bitwise types
+ miscregs.hh/cc: Definition of watchpoint registers and its initialization
+ tlb.cc: Call for watchpoint entry point on tlb translation for dtlb.
+ fault.cc/hh: Definition/implementation of Watchpoint exception and
               modification on DataAbort Exception accordingly to handle
               AArch32 Watchpoint exceptions.
+ types.hh: Exception Code for watchpoint.
+ self_debug.cc/hh: Watchpoint check and comparison. Definition and
                    implementation of all the watchpoint auxiliar functions.

Change-Id: If275e4df0d28918dd887ab78166e653da875310a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

util: Add missing iostream header to util/m5/src/commands.cc

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I93f99284ecda22c73572cc0ffa8c3be0160ce560
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30734
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Add a missing "break" in an ARM miscreg decode function.

This change accidentally left out a "break" which gcc found and
complained about.

arch-arm: Implementation of Hardware Breakpoint exception

This change adds in the break based on the assumption that the function
should not fall through that case to the next.

Change-Id: Id728a0c9a504d1b6d231d3fe1e7c5ece05d3ac4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30654
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Remove dead code from results.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ib145f8916fdde9f1571eb71ca2fef3501b48804b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30244
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

ext: Remove dead code from main.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I5f0fbe6c4f5620503c03dfb1b3c8eb1fac31409e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30243
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

ext: Remove dead code from configuration.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ibaf812ace94c2ae0e2115552a87fb506a427bb89
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30242
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

stats: add option to disable alignment spaces in stats.txt file

The alignment spaces in stats.txt takes up a lot of space and increases
simulation time, this commit adds the option to disable them with:

--stats-file stats.txt?spaces=False

Sample old lines with ?desc=False:

system.cpu.op_class::FloatMultAcc                   0      0.00%     65.92%
system.cpu.op_class::FloatDiv                       0      0.00%     65.92%

Sample new lines with ?desc=False;spaces=False:

system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%

On a 1000 dumpstats m5op loop spaces=False reduces:

* size: from 38MB to 20MB
* time: from 4.5s to 3.5s

Change-Id: Ib738b996b5646c329094cf61aaa1d977e844e759
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28627
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix minor bug PAUTH comparision with 0

Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30615
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Fix SCR.NS compare to 0

Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30614
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

util: Move the call type implementations into their own subdir.

Change-Id: Ie94c2ef4783b6b5700beb0f0bbeb765ce9b03934
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27551
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

util: c++-ify command line arguments in the m5 utility.

Change-Id: Icfdd95c61ac9937823027563d086e5a690870fb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27550
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

util: c++-ify the call type in the m5 utility.

Use a class to track call type information, and mostly avoid having to
use ifdefs to include or not include support for individual call types.

Change-Id: I731c99e67ea1c511d53431df3f77b4a959919a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27549
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

util: Convert the m5 utility to C++.

This will make it possible to use the googletest unit testing framework,
and will let us use c++ mechanisms to simplify and streamline the code.

Change-Id: I8ab358de47ce6b5c2d601cc0b9f2a694b2037a9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27548
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

util: Pull most code out of m5.c.

By pulling the code out, this code can be tested by unit tests.

Change-Id: I2d0510995d3e97d721f1de3024120f0c90b7a5ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27547
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

python,util: Fixed string decoding in include verifier

The Python2 <-> Python3 port included a decode on a string as part of
the include statement git-hook verifier. This results in a failure. To
fix this issue, the file to be checked is opened in binary mode.

This issue was highlighted by Gabe Black here:
https://gem5-review.googlesource.com/c/public/gem5/+/28588

Change-Id: I9a30ecc24d4741853ed1c2d0c03addf57c3e5b6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30336
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix -Werror=maybe-uninitialized in system.cc

The patch is simply initializing when to 0 before unserializing
the real value

Change-Id: I4e19eeafa9334116b440948af1943f3835803671
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30594
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-arm: Fix arm switcheroo regressions

These were failing with the combination of:

https://gem5-review.googlesource.com/c/public/gem5/+/29233

with

https://gem5-review.googlesource.com/c/public/gem5/+/27967

Change-Id: I8d3c3701faf4828e76aaa2cb895b9589f057d370
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30616
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Ignore chmod syscall

chmod caused crashes in certain MIOpen apps with the newer
version of MIOpen used in the Dockerfile. Ignoring it allows
those apps to finish.

Change-Id: If8d144d64f76ae04f384ebf983024c571b26875e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30534
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update MIOpen version used in Docker

The updated MIOpen version uses rocBLAS instead of MIOpenGEMM for
both convolution and rnn GEMM kernels, which provides a speedup in
simulation.

Change-Id: I4b81f18e95d39fd79b22d0bf92563ede61e44e32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30494
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing.

Change-Id: Ifca504bc298c09cbc16ef7cded21da455fb1e118
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25146
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move guts of quiesce and quiesceTick from ThreadContext to System.

The functions in ThreadContext are now just convenience wrappers.

Change-Id: Ib56c4bdd27e611fb667a8056dfae37065f4034eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25145
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implementation of Hardware Breakpoint exception

This code implementes hardware breakpoint exception as part of
software debug explained in ARMv8 reference manual ChapterD2.

+ ArmISA.py: Modify register to allow up to 15 Breakpoint registers
+ Sconscript: Add new file self_debug
+ faults.cc/hh: Defintion and implementation of HardwareBreakpoint
                exception inheriting ArmFault.
+ isa.cc/hh: ArmISA contains now an attribute pointing to the SelfDebug
             object that will be used to be access SelfDebug infrastructure
             Added special cases for setMiscReg to cache debug enable bits.
+ miscregs.hh/cc: Definition and initialization of DBGDCn and DBGDVn
                  registers.
+ tlb.cc/hh: We include the access to check for breakpoint instruction as
             part of the tlb translation process, checking if it comes from a
             fetch in the itlb
+ types.hh: Definition of new bitwise register types.
+ utility.cc/hh: Definition and implementation of auxiliar functions for
                the selfDebug.
+ self_debug.hh/cc: Main files that include the implemenattion of
            breakpoint checks, selfdebug enable and auxiliar functions.

Change-Id: I0e2a4be7f778de560c512253a9148da61e3e7e7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27967
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Make headTailMap a std::unordered_map

There is no reason that the headTailMap needs to be
sorted, so let's use a std::unordered_map.

Change-Id: I18641b893352c18ec86e3775c8947a05a6c6547d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29930
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Remove unused function hostWakeUp from shader

Change-Id: Ib4415a7c5918da03bbd16fe9adb4dd593dcaa95c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29929
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Fix V_MAD_I32_I24 sign extension

We are not properly sign extending the bits we hack off for
V_MAD_I32_I24.

This fixes rnn_fwdBwd 64 1 1 lstm pte assertion failure.

Change-Id: I2516e5715227cbd822e6a62630674f64f7a109e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29928
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3, gpu-compute: Fix issue when reading const operands

Currently, when an instruction has an operand that reads a const
value, it goes thru the same readMiscReg() api call as other
misc registers (real HW registers, not constant values). There
is an issue, however, when casting from the const values (which are
32b) to higher precision values, like 64b.

This change creates a separate, templated function call to the GPU's
ISA state that will return the correct type.

Change-Id: I41965ebeeed20bb70e919fce5ad94d957b3af802
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29927
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Updating implementation of atomics

This changeset is moving the access of the data operand
from initiateAcc to the execute method of atomic instructions.

Change-Id: I1debae302f0b13f79ed2b7a9ed2f6b07fcec5128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29926
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: add support for HSA's barrier bit kernel synchronization

This commit adds support for the HSA's barrier bit version of
synchronization.  This method of synchronization is used for all
HIP benchmarks, and thus is necessary to ensure that multiple
kernels from the same queue are synchronizing properly.

Change-Id: I64f2d311a3970b71194e0555e2b932800df65e98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29925
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix build errors with gcc 10.x

This fixes conditions that perform a redundant check to
see if an unsigned value is greater than or equal to
zero. With gcc 10.x, this generates the following error
because of implicit usage of the "-Werror=type-limits"
flag.

"comparison of unsigned expression in '>= 0' is always true"

Change-Id: Ib1a88035ef5fba410d18de0adf614db4bc634faf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30474
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Use new InstRecord faulting flag in cpu models

This patch sets the faulting flag in atomic, timing, minor and o3 CPU
models.

It also fixes the minor/timing CPU models which were not respecting the
ExecFaulting flag. This is now checked before calling dump() on the
tracing object, to bring it in line with the other CPU models.

Change-Id: I9c7b64cc5605596eb7fcf25fdecaeac5c4b5e3d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30135
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add faulting flag to instruction tracing interface

This patch adds a faulting flag to InstRecord.
This allows tracers to identify that the traced instruction has
faulted, when ExecFaulting is enabled. It can be set with
InstRecord::setFaulting() and read with Instrecord::getFaulting().

Change-Id: I390392d59de930533eab101e96dc4d3c76500748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object

We already provide to the user the CCFLAGS_EXTRA, LDFLAGS_EXTRA
variables to pass flags to scons when compiling/linking gem5.
Those variables are not passed to the marshal object.
We add an extra pair:

MARSHAL_CCFLAGS_EXTRA, MARSHAL_LDFLAGS_EXTRA

to add flag injection capabilities to the marshal object.

The patch is also renaming base_py_env to marshal_env.
This happens for 2 reasons:

1) At the moment the marshal compilation is the only task
making use of the base python environment.

2) Consistency with the EXTRA variable names added with this patch.
I could have named them as BASE_XXFLAGS_EXTRA, but it seems too much
generic and users might be confused by that, as they might think
the BASE_XXFLAGS_EXTRA is a subset of the XXFLAGS_EXTRA so that
setting it will affect gem5 compilation as well.

Change-Id: I3e420caa897059455ff8f35462db2b38da050e93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30016
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Teach gem5 to recognize the gem5 semihosting immediate values.

These give access to the gem5 extension calls, currently only the pseudo
ops.

Change-Id: I60ece82f1f084791971a2de0b54be2f0d9da243e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27246
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

util: Add a semihosting implementation to the aarch64 m5 utility.

This will allow it to work on CPUs that only support semihosting like
ARM's fastmodels.

Change-Id: I74e536d79d0f77b864e1e4b9d73e265b6d0b1fcb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27245
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Allow overriding the magic address in the m5 utility.

This is useful in situations where the address is hard to know ahead of
time, for instance on ARM systems where the address map is hard to
predict.

The default address is now M5OP_ADDR, or 0 if that's not defined.

Change-Id: I3140e05b04365c1a76e52f8c3dc85f472c230ae4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27244
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-ruby: add cache hit/miss statistics for TCP and TCC

Change-Id: Ifa6fdbb9dd062a3684b9620eac6683c57e651a72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

arch-gcn3: Implement instruction v_div_fixup_f32

Instruction v_div_fixup_f32 was unimplemented. The
implementation was added by mimicking v_div_fixup_f64.

Change-Id: I9306b198f327e9fde3414aa1bb2bec20503b1efd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29924
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Implement instruction v_div_fmas_f32

Instruction v_div_fmas_f32 was unimplemented. The
implementation was added by mimicking v_div_fmas_f64.

Change-Id: I262820a7a66877d140eb99b538715c3cae4d1860
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29923
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: fix bug with SDWA support

Instructions that use the SDWA field need to use the extra SRC0
register associated with the SDWA instruction instead of the
"default" SRC0 register, since the default SRC0 register contains
the SDWA information when SDWA is being used.  This commit fixes
15de044c to take this into account.  Additionally, this commit
removes reads of the registers from the SDWA helper functions,
since they overwrite any changes made to the destination register.
Finally, this change modifies the instructions that use SDWA to
simplify the flow through the execute() functions.

Change-Id: I3bad83133808dfffc6a4c40bbd49c3d76599e669
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29922
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: remove deprecated hsail gpu_hello

Change-Id: I7e15075e7805af732e89c3269fdff9d65a144219
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29921
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: add support for unaligned accesses

Previously, with HSAIL, we were guaranteed by the HSA specification
that the GPU will never issue unaligned accesses.  However, now
that we are directly running GCN this is no longer true.
Accordingly, this commit adds support for unaligned accesses.
Moreover, to reduce the replication of nearly identical
code for the different request types, I also added new helper
functions that are called by all the different memory request
producing instruction types in op_encodings.hh.

Adding support for unaligned instructions requires changing
the statusBitVector used to track the status of the memory
requests for each lane from a bit per lane to an int per lane.
This is necessary because an unaligned access may span multiple
cache lines.  In the worst case, each lane may span multiple
cache lines.  There are corresponding changes in the files that
use the statusBitVector.

Change-Id: I319bf2f0f644083e98ca546d2bfe68cf87a5f967
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29920
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Implement instruction v_div_scale_f32

Instruction v_div_scale_f32 was unimplemented, the
implementation was added by mimicking v_div_scale_f64.

Change-Id: I89cdfd02ab01b5936de0e9f6c41e7f3fc4f10ae1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29919
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

config: fix settings of kernel boundary sync flags

Change-Id: I58a8edc5d324bdcaa84e3d715e2712a43e8ede0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29918
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: enable flexible control of kernel boundary syncs

Kernel end release was turned on for VIPER protocol, which
is in fact write-through based and thus no need to have
release operation. This changeset splits the option
'impl_kern_boundary_sync' into 'impl_kern_launch_acq'
and 'impl_kern_end_rel', and turns off release on VIPER.

Change-Id: I5490019b6765a25bd801cc78fb7445b90eb02a3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29917
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: remove recvToken from GM pipe exec

Tokens were previously acquired in GM pipe exec but has been moved to
acqCoalescerToken. This removes the extraneous code which was acquiring
tokens twice, causing them to be depleted and triggering an assertion.

Change-Id: Ic92de8f06cc85828b29c69790bdadde057ef1777
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29916
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm

This change adds DMA support to the MOESI_AMD_Base-dir.sm,
which is needed to support ROCm apps/GCN3 ISA in the VIPER
ptl. The DMA controller is copied from the MOESI_hammer-dma.sm
with few modifications.

Change-Id: I56141436eee1c8f62c2a0915fa3b63b83bbcbc9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29914
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: GCN3 and VIPER integration

This patch modifies the Coalescer and VIPER protocol to support memory
synchronization requests and write-completion responses that are
required by upcoming GCN3 implementation.

VIPER protocol is simplified to be a solely write-through protocol.

Change-Id: Iccfa3d749a0301172a1cc567c59609bb548dace6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29913
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Initialize stackSize and stackMin in MemState

Initialize _stackSize and _stackMin to the maximum stack size values.
The are setup in each arch's Process::initState and may be uninitialized
until then. If a stack fixup occurs before these are setup, addresses
which are not in the stack might be allocated on the stack. This
prevents that until they are initialized in Process::initState. If an
access occurs before that with these initial values, the stack fixup
will simply allocate a page of memory in the stack space. However, it
will not print the typical info messages about growing the stack during
this time.

Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
JIRA: https://gem5.atlassian.net/browse/GEM5-629
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30394
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>