Ali Saidi [Thu, 1 Dec 2011 08:15:22 +0000 (00:15 -0800)]
O3: Add stat that counts how many cycles the O3 cpu was quiesced.
--HG--
extra : rebase_source :
043b9307eef3c5b87f8e6370765641e016ed1fa7
Gabe Black [Thu, 1 Dec 2011 05:17:14 +0000 (00:17 -0500)]
X86: Fix a bad segmentation check for the stack segment.
--HG--
extra : rebase_source :
755f4f6eae52f88ed516a1f1ac9e2565725d89c1
Ali Saidi [Wed, 30 Nov 2011 23:57:11 +0000 (18:57 -0500)]
SPARC: update SE stats for FP fix
--HG--
extra : rebase_source :
954a009a9f8eef6cae6050ee99f264e0fb456f85
Gabe Black [Mon, 28 Nov 2011 09:35:55 +0000 (04:35 -0500)]
SPARC: Minor style fix.
I forgot to fix this as well per Ali's feedback.
--HG--
extra : rebase_source :
e70d031cb5f91e2212a1a73ea1769bf0549b826c
Andreas Hansson [Mon, 28 Nov 2011 09:34:18 +0000 (04:34 -0500)]
SPARC: Fixing a minor copy-paste bug using the wrong variable
There was a bug in the mm_disk implementation where a copy paste error
resulted in the d32 variable not being initialised (as it incorrectly
was used instead of d16), and gcc 4.5 complaining.
--HG--
extra : rebase_source :
9515e87b188b9eac189da8034cb13c3bf7d9e20b
Gabe Black [Mon, 28 Nov 2011 09:19:57 +0000 (04:19 -0500)]
SPARC: Update the FS stats for the recent FP fix.
--HG--
extra : rebase_source :
643e3541507576e30d9cd4dec045e5b94532c342
Gabe Black [Mon, 28 Nov 2011 03:00:58 +0000 (22:00 -0500)]
SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.
--HG--
extra : rebase_source :
ee79ab89c5a707c1294f38abb84c60f8ef64196c
Gabe Black [Mon, 28 Nov 2011 03:00:57 +0000 (22:00 -0500)]
Compiler: Add an M5_NO_INLINE define.
--HG--
extra : rebase_source :
1f5e8b7bb6b0a8bb4f951b6d7189964d96ed5df1
Tushar Krishna [Wed, 23 Nov 2011 21:34:13 +0000 (16:34 -0500)]
Topology: bug fix in external link initialization
--HG--
extra : rebase_source :
c226cd1e5e5ed4d4c64fa9427de4905bd8335e34
Tushar Krishna [Wed, 23 Nov 2011 01:11:18 +0000 (20:11 -0500)]
Remove standard_1level_CMP-protocol.sm include statement from Network
--HG--
extra : rebase_source :
51a2dd4bb643e3dc5b0218a6190cf5c1989f9691
Gabe Black [Sun, 20 Nov 2011 13:10:05 +0000 (05:10 -0800)]
X86: Fix the constant detecting three byte opcodes in the predecoder.
--HG--
extra : rebase_source :
b64c3d2348cb73177024695fb6e205d51bf1cda9
Nilay Vaish [Fri, 18 Nov 2011 04:53:56 +0000 (22:53 -0600)]
Regression: Update statistics for x86 long regression tests
This patch updates reference statistics for the regression tests. This
update was necessitated by a recent change in behavior of some instructions
in the x86 architecture.
Nilay Vaish [Mon, 14 Nov 2011 23:44:35 +0000 (17:44 -0600)]
Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
Gabe Black [Thu, 10 Nov 2011 05:48:28 +0000 (21:48 -0800)]
GCC: Guard some gcc flags so they're used when available and needed.
Nilay Vaish [Sat, 5 Nov 2011 20:32:23 +0000 (15:32 -0500)]
Tests: Update stats due to addition of fence microop
Tushar Krishna [Fri, 4 Nov 2011 22:40:22 +0000 (18:40 -0400)]
GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
Nilay Vaish [Fri, 4 Nov 2011 16:26:12 +0000 (11:26 -0500)]
MESI Protocol: Add functions for profiling misses
Nilay Vaish [Fri, 4 Nov 2011 03:52:21 +0000 (22:52 -0500)]
x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
Nilay Vaish [Fri, 4 Nov 2011 03:52:02 +0000 (22:52 -0500)]
Protocol: Remove standard one and two level files
Nilay Vaish [Fri, 4 Nov 2011 03:46:45 +0000 (22:46 -0500)]
Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
Gabe Black [Mon, 31 Oct 2011 08:09:44 +0000 (01:09 -0700)]
GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
Nilay Vaish [Sun, 30 Oct 2011 20:57:39 +0000 (15:57 -0500)]
Commit due to merge.
Nilay Vaish [Sun, 30 Oct 2011 20:55:32 +0000 (15:55 -0500)]
Python: Remove import for random
Nilay Vaish [Sat, 29 Oct 2011 21:54:57 +0000 (16:54 -0500)]
Ruby FS: Add the options for kernel and simulation script
These options were missing from the script ruby_fs.py. This patch adds these
options to the script.
Nilay Vaish [Fri, 28 Oct 2011 18:04:33 +0000 (13:04 -0500)]
Merged with recent changes.
Nilay Vaish [Fri, 28 Oct 2011 18:00:35 +0000 (13:00 -0500)]
Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.
Steve Reinhardt [Sun, 23 Oct 2011 05:30:08 +0000 (22:30 -0700)]
SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.
The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
Steve Reinhardt [Sun, 23 Oct 2011 05:30:07 +0000 (22:30 -0700)]
syscall_emul: implement MAP_FIXED option to mmap()
Steve Reinhardt [Sat, 22 Oct 2011 23:52:07 +0000 (16:52 -0700)]
tests: fix spurious scons "Error 1" messages
Turns out these are due to diff reporting that files
acutally differed via a non-zero exit code.
Steve Reinhardt [Thu, 20 Oct 2011 20:11:56 +0000 (13:11 -0700)]
dev: clean up PioDevice and DmaDevive getPort() methods.
Make DmaDevice::getPort() call PioDevice::getPort() instead
of just copying and pasting the code.
Also move definitions from .hh to .cc file.
Steve Reinhardt [Thu, 20 Oct 2011 20:09:10 +0000 (13:09 -0700)]
SimObject: add export_method* hooks to export C++ methods to Python
Replace the (broken as of previous changeset) swig_objdecl() method
that allowed/forced you to substitute a whole new C++ struct
definition for SWIG to wrap with a set of export_method* hooks
that let you just declare a set of C++ methods (or other declarations)
that get inserted in the auto-generated struct.
Restore the System get/setMemoryMode methods, and use this mechanism
to specialize SimObject as well, eliminating teh need for sim_object.i.
Needed bits of sim_object.i are moved to the new pyobject.i.
Also sucked a little SimObject specialization into cxx_param_decl()
allowing us to get rid of src/sim/sim_object_params.hh. Now the
generation and wrapping of the base SimObject param struct is more
in line with how derived objects are handled.
--HG--
rename : src/python/swig/sim_object.i => src/python/swig/pyobject.i
Steve Reinhardt [Thu, 20 Oct 2011 20:08:49 +0000 (13:08 -0700)]
scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript
file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
the process a little clearer.
- Did a little generated file/module renaming:
- vptype_Foo now Foo_vector
- init_Foo is now Foo_init
This makes it easier to see all the Foo-related files in a
sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
objects get/setMemoryMode method exports. Will be fixing this in
a future changeset.
Ali Saidi [Wed, 19 Oct 2011 23:08:31 +0000 (18:08 -0500)]
ARM: Fix small bug in config script that prevents android from booting
Nathan Binkert [Tue, 18 Oct 2011 00:06:40 +0000 (17:06 -0700)]
scons: fix building of shared objects
Nilay Vaish [Mon, 10 Oct 2011 22:01:33 +0000 (17:01 -0500)]
mc146818: Correctly serialize tickEvent
'tickEvent' was not being serialized as in its place 'event' was being used.
This patch rectifies this error.
Gabe Black [Tue, 27 Sep 2011 07:25:26 +0000 (00:25 -0700)]
O3: Tidy up some DPRINTFs in the LSQ.
Gabe Black [Tue, 27 Sep 2011 07:24:43 +0000 (00:24 -0700)]
Faults: Replace calls to genMachineCheckFault with M5PanicFault.
Gabe Black [Tue, 27 Sep 2011 07:17:09 +0000 (00:17 -0700)]
Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
Gabe Black [Tue, 27 Sep 2011 07:16:33 +0000 (00:16 -0700)]
Faults: Make the generic faults more consistent between SE and FS.
All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
Gabe Black [Tue, 27 Sep 2011 06:48:54 +0000 (23:48 -0700)]
ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.
Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
Nilay Vaish [Mon, 26 Sep 2011 17:18:32 +0000 (12:18 -0500)]
LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
Gabe Black [Mon, 26 Sep 2011 09:09:04 +0000 (02:09 -0700)]
SE/FS: Define a const bool FullSystem which will equal FULL_SYSTEM.
This constant will have the same value as FULL_SYSTEM but will not be usable
by the preprocessor. It can be substituted into places where FULL_SYSTEM is
used in a C++ context and will make it easier to find which parts of the
simulator still use FULL_SYSTEM with the preprocessor using grep.
Gabe Black [Sun, 25 Sep 2011 00:03:18 +0000 (17:03 -0700)]
SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
Gabe Black [Sat, 24 Sep 2011 23:59:11 +0000 (16:59 -0700)]
SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
Steve Reinhardt [Sat, 24 Sep 2011 15:12:26 +0000 (08:12 -0700)]
style.py: don't die on empty files
Gabe Black [Fri, 23 Sep 2011 09:42:22 +0000 (02:42 -0700)]
X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
Steve Reinhardt [Fri, 23 Sep 2011 01:59:55 +0000 (18:59 -0700)]
event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.
Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
Steve Reinhardt [Fri, 23 Sep 2011 01:59:54 +0000 (18:59 -0700)]
pseudo_inst: clean up workbegin/workend functions
Use exitSimLoop() function instead of explicitly scheduling
on mainEventQueue (which won't work once we go to multiple
event queues). Also introduced a local params variable to
shorten a lot of expressions.
Steve Reinhardt [Fri, 23 Sep 2011 01:58:14 +0000 (18:58 -0700)]
params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability.
Properly compare IpAddress objects (by value and not object identity).
Also fix up derived param classes (IpNetmask and IpWithPort)
similarly.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS, faults: Update how the PC is set.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Use inheritance to consolidate class definitions.
Gabe Black [Mon, 19 Sep 2011 13:17:21 +0000 (06:17 -0700)]
MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Get rid of the unused "count" field in FaultVals.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
MIPS: Consolidate the two AddressErrorFault variants.
Gabe Black [Mon, 19 Sep 2011 13:17:20 +0000 (06:17 -0700)]
Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Add constructors to the fault classes.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
Gabe Black [Mon, 19 Sep 2011 13:17:19 +0000 (06:17 -0700)]
SPARC: Remove #if FULL_SYSTEMs from the ISA description.
Gabe Black [Mon, 19 Sep 2011 13:14:02 +0000 (06:14 -0700)]
MIPS: Get rid of #if style config checks in the ISA description.
Gabe Black [Mon, 19 Sep 2011 13:09:15 +0000 (06:09 -0700)]
MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
Gabe Black [Mon, 19 Sep 2011 12:53:54 +0000 (05:53 -0700)]
MIPS: Get rid of the unused (and partially defined) CacheError fault.
Gabe Black [Mon, 19 Sep 2011 12:19:45 +0000 (05:19 -0700)]
Endianness: Make it easier to check the compiled in guest endianness.
It was technically possible but clumsy to determine what endianness a guest
was configured with using the state in byteswap.hh. This change makes that
information available more directly.
Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
Gabe Black [Mon, 19 Sep 2011 10:40:30 +0000 (03:40 -0700)]
Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
Gabe Black [Mon, 19 Sep 2011 10:39:58 +0000 (03:39 -0700)]
PseudoInst: Make all the pseudo insts available in SE and FS.
Gabe Black [Mon, 19 Sep 2011 09:53:37 +0000 (02:53 -0700)]
X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
Gabe Black [Mon, 19 Sep 2011 09:46:48 +0000 (02:46 -0700)]
Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
Gabe Black [Mon, 19 Sep 2011 09:40:19 +0000 (02:40 -0700)]
PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
Gabe Black [Mon, 19 Sep 2011 06:26:39 +0000 (23:26 -0700)]
Pseudoinst: Add an initParam pseudo inst function.
Ali Saidi [Sat, 17 Sep 2011 16:34:03 +0000 (12:34 -0400)]
MIPS: Fix regressions tests
Ali Saidi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
IGbE: Clean up debug printing and proprly account for copied bytes.
Some DPRINTFs were printing uninitalized values because the DPRINTFs were
always being printed even when the features they were printing weren't
being used. This change moves the DPRINTFs into the appropriate if blocks
and initializes the state variables correctly.
There also is a case where the offset into the packet could be calculated
incorrectly during a DMA that is fixed.
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
ARM: update TLB to set request packet ASID field
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
Mem: Allow ASID to be set after request is created.
Chander Sudanthi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.
Daniel Johnson [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
ARM: Implement numcpus bits in L2CTLR register.
Ali Saidi [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
Prakash Ramrakhyani [Tue, 13 Sep 2011 17:06:13 +0000 (12:06 -0500)]
gem5ops: Implement Java JNI for gem5Ops
These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;
public class HelloWorld {
public static void main(String[] args) {
gem5Op gem5 = new gem5Op();
System.out.println("Rpns0:" + gem5.rpns());
System.out.println("Rpns1:" + gem5.rpns());
}
static {
System.loadLibrary("gem5OpJni");
}
}
When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java
and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
Ali Saidi [Tue, 13 Sep 2011 16:58:09 +0000 (12:58 -0400)]
O3: Update stats for new ordering fix.
Ali Saidi [Tue, 13 Sep 2011 16:58:08 +0000 (12:58 -0400)]
LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).
This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.
The performance improvement on SPEC benchmarks can be substantial (2-10%).
Deyuan Guo [Sat, 10 Sep 2011 10:45:25 +0000 (03:45 -0700)]
MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.
Testing:
Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
Gabe Black [Sat, 10 Sep 2011 09:31:15 +0000 (02:31 -0700)]
PseudoInst: Add compiler guards to pseudo_inst.hh.
Gabe Black [Fri, 9 Sep 2011 09:40:11 +0000 (02:40 -0700)]
StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
Gabe Black [Fri, 9 Sep 2011 09:30:01 +0000 (02:30 -0700)]
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
Gabe Black [Fri, 9 Sep 2011 08:35:05 +0000 (01:35 -0700)]
MIPS: Update MIPS stats for cleaned up operand checks.
Gabe Black [Fri, 9 Sep 2011 08:01:43 +0000 (01:01 -0700)]
Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
Gabe Black [Thu, 8 Sep 2011 10:21:14 +0000 (03:21 -0700)]
ISA parser: Don't look for operands in strings.
Gabe Black [Thu, 8 Sep 2011 10:20:05 +0000 (03:20 -0700)]
ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
Gabe Black [Tue, 6 Sep 2011 01:36:26 +0000 (18:36 -0700)]
X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
Gabe Black [Mon, 5 Sep 2011 09:48:57 +0000 (02:48 -0700)]
X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
Lisa Hsu [Sat, 3 Sep 2011 00:04:00 +0000 (17:04 -0700)]
TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why. Add a little warn() to explain it a bit. Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
Lisa Hsu [Thu, 1 Sep 2011 22:25:54 +0000 (15:25 -0700)]
Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
Lisa Hsu [Thu, 1 Sep 2011 18:41:44 +0000 (11:41 -0700)]
Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.
Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
Nilay Vaish [Mon, 29 Aug 2011 11:34:40 +0000 (06:34 -0500)]
SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
Nilay Vaish [Mon, 29 Aug 2011 10:10:23 +0000 (05:10 -0500)]
Ruby: Remove some unused code
Nilay Vaish [Fri, 26 Aug 2011 17:27:58 +0000 (12:27 -0500)]
Ruby: Eliminate modulo op for computing set size.
Ali Saidi [Fri, 19 Aug 2011 20:08:09 +0000 (15:08 -0500)]
ARM: Add some MP regressions and clean up the disk images and kernels a bit