Ali Saidi [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
Giacomo Gabrielli [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
O3: Create a pipeline activity viewer for the O3 CPU model.
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
Ali Saidi [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
ARM: Update stats for better miscreg support for MP configurations.
Wade Walker [Fri, 15 Jul 2011 16:53:34 +0000 (11:53 -0500)]
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
Wade Walker [Fri, 15 Jul 2011 16:53:34 +0000 (11:53 -0500)]
ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
Nilay Vaish [Tue, 12 Jul 2011 00:57:10 +0000 (19:57 -0500)]
se.py: Fixes the way ruby's options are added
Nilay Vaish [Mon, 11 Jul 2011 21:52:52 +0000 (16:52 -0500)]
X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
Gabe Black [Mon, 11 Jul 2011 11:47:06 +0000 (04:47 -0700)]
ISA: Get rid of the unused mem_acc_type template parameter.
Ali Saidi [Sun, 10 Jul 2011 17:56:09 +0000 (12:56 -0500)]
O3: Update stats for fetch and bp changes.
Mrinmoy Ghosh [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
Branch predictor: Fixes the tournament branch predictor.
Branch predictor could not predict a branch in a nested loop because:
1. The global history was not updated after a mispredict squash.
2. The global history was updated in the fetch stage. The choice predictors
that were updated used the changed global history. This is incorrect, as
it incorporates the state of global history after the branch in
encountered. Fixed update to choice predictor using the global history
state before the branch happened.
3. The global predictor table was also updated using the global history state
before the branch happened as above.
Additionally, parameters to initialize ctr and history size were reversed.
Geoffrey Blake [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
O3: Fix up pipelining icache accesses in fetch stage to function properly
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
IO: Handle case where ISA Fake device is being used as a fake memory.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
O3: Make sure fetch doesn't go off into the weeds during speculation.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
Config: Add support for a Self.all proxy object
Daniel Johnson [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
ARM: Fix mp interrupt bug in GIC.
Missing "!" made multiprocessor interrupts operate incorrectly.
Korey Sewell [Fri, 8 Jul 2011 01:32:49 +0000 (21:32 -0400)]
alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
Brad Beckmann [Thu, 7 Jul 2011 01:45:15 +0000 (18:45 -0700)]
ruby: added generic dma machine
Brad Beckmann [Thu, 7 Jul 2011 01:44:42 +0000 (18:44 -0700)]
MOESI_hammer: Fixed uniprocessor DMA bug
Nathan Binkert [Wed, 6 Jul 2011 01:30:05 +0000 (18:30 -0700)]
slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.
Nathan Binkert [Wed, 6 Jul 2011 01:30:05 +0000 (18:30 -0700)]
slicc: cleanup slicc code and make it less verbose
Nathan Binkert [Wed, 6 Jul 2011 01:30:04 +0000 (18:30 -0700)]
grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently. This makes implementing an include statement as part
of a grammar possible.
Gabe Black [Wed, 6 Jul 2011 00:46:46 +0000 (17:46 -0700)]
X86: Add a config for an FS regression on O3.
Gabe Black [Tue, 5 Jul 2011 23:52:57 +0000 (16:52 -0700)]
ISAs: Streamline some spots where Mem is used in the ISA descriptions.
Gabe Black [Tue, 5 Jul 2011 23:52:15 +0000 (16:52 -0700)]
ISA parser: Define operand types with a ctype directly.
Gabe Black [Tue, 5 Jul 2011 23:48:18 +0000 (16:48 -0700)]
ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
Nilay Vaish [Sun, 3 Jul 2011 16:38:25 +0000 (11:38 -0500)]
Merged with Gabe's recent changes.
Nilay Vaish [Sun, 3 Jul 2011 16:33:46 +0000 (11:33 -0500)]
Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
Gabe Black [Sun, 3 Jul 2011 05:52:26 +0000 (22:52 -0700)]
tracediff: Check for --debug-flags now instead of --trace-flags.
Gabe Black [Sun, 3 Jul 2011 05:35:04 +0000 (22:35 -0700)]
ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
Gabe Black [Sun, 3 Jul 2011 05:34:58 +0000 (22:34 -0700)]
ExecContext: Get rid of the now unused read/write templated functions.
Gabe Black [Sun, 3 Jul 2011 05:34:29 +0000 (22:34 -0700)]
ISA: Use readBytes/writeBytes for all instruction level memory operations.
Gabe Black [Sun, 3 Jul 2011 05:31:42 +0000 (22:31 -0700)]
Stats: Update stats for the x86 store fault fix.
Gabe Black [Sun, 3 Jul 2011 05:31:22 +0000 (22:31 -0700)]
X86: Fix store microops so they don't drop faults in timing mode.
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
Nilay Vaish [Fri, 1 Jul 2011 21:29:33 +0000 (16:29 -0500)]
Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
Brad Beckmann [Fri, 1 Jul 2011 00:57:26 +0000 (19:57 -0500)]
Regression: Updates regression outputs for Ruby memtest
This patch updates the regression outputs for Ruby memtest. This was
required because of the changes carried out by the addition of functional
access support to Ruby.
Brad Beckmann [Fri, 1 Jul 2011 00:54:02 +0000 (19:54 -0500)]
config: removed unnecessary slashes
This patch removes unnecessary slashes from a couple of python scripts.
Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
Nilay Vaish [Tue, 28 Jun 2011 23:27:38 +0000 (18:27 -0500)]
arch: print next upc correctly
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
Joel Hestness [Fri, 24 Jun 2011 20:47:35 +0000 (15:47 -0500)]
Ruby: remove unused functions in CacheMemory: get/setMemoryValue
Deyaun Guo [Thu, 23 Jun 2011 03:35:21 +0000 (23:35 -0400)]
mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
Gabe Black [Wed, 22 Jun 2011 02:28:14 +0000 (19:28 -0700)]
X86: Eliminate an unused argument for building store microops.
Korey Sewell [Tue, 21 Jun 2011 02:44:24 +0000 (22:44 -0400)]
inorder: sparc: add 02.insttest regression
Korey Sewell [Tue, 21 Jun 2011 02:44:22 +0000 (22:44 -0400)]
inorder: sparc: add hello world regression
- add InOrderCPU compile option to SPARC
- add hello regression for SPARC
Korey Sewell [Mon, 20 Jun 2011 22:58:31 +0000 (18:58 -0400)]
merge regression updates
Korey Sewell [Mon, 20 Jun 2011 22:57:14 +0000 (18:57 -0400)]
alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
Korey Sewell [Mon, 20 Jun 2011 16:21:10 +0000 (12:21 -0400)]
inorder: alpha-hello regression update
Korey Sewell [Mon, 20 Jun 2011 12:37:25 +0000 (08:37 -0400)]
inorder: merge gabes compile fix
Gabe Black [Mon, 20 Jun 2011 09:29:14 +0000 (02:29 -0700)]
InOder: Fix a compile error.
Korey Sewell [Mon, 20 Jun 2011 03:26:36 +0000 (23:26 -0400)]
inorder: gem5.opt compile
variable name typo.
Korey Sewell [Mon, 20 Jun 2011 01:54:53 +0000 (21:54 -0400)]
inorder: update eon regr w/eon info
previous commit copied over O3 stats, this one puts the inorder ones in the right place
Korey Sewell [Mon, 20 Jun 2011 01:43:43 +0000 (21:43 -0400)]
inorder: add 10.linux-boot regression
Korey Sewell [Mon, 20 Jun 2011 01:43:43 +0000 (21:43 -0400)]
inorder: add eon regression
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: update SE regressions
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: clear reg. dep entry after removing from list
this will safeguard future code from trying to remove
from the list twice. That code wouldnt break but would
waste time.
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: se: squash after syscalls
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: cleanup dprintfs in cache unit
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: SE mode TLB faults
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder:tracing: fix fault tracing bug
Korey Sewell [Mon, 20 Jun 2011 01:43:42 +0000 (21:43 -0400)]
inorder: se compile fixes
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder: add necessary debug flag header files
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
mips: mark unaligned access flag as true
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder: clear fetchbuffer on traps
implement clearfetchbufferfunction
extend predecoder to use multiple threads and clear those on trap
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder: use separate float-reg bits function in dyninst
this will make sure we get the correct view of a FP register
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder: use trapPending flag to manage traps
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
Korey Sewell [Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)]
inorder: handle serializing instructions
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
alpha: fix warn_once for prefetches
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
inorder: register ports for FS mode
handle "snoop" port registration as well as functional
port setup for FS mode
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
inorder: check for interrupts each tick
use a dummy instruction to facilitate the squash after
the interrupts trap
Korey Sewell [Mon, 20 Jun 2011 01:43:40 +0000 (21:43 -0400)]
inorder: explicit fault check
Before graduating an instruction, explicitly check fault
by making the fault check it's own separate command
that can be put on an instruction schedule.
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
inorder: squash and trap behind a tlb fault
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
inorder: stall stores on store conditionals & compare/swaps
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
alpha: make hwrei a control inst
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?
The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
inorder: make InOrder CPU FS compilable/visible
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
inorder: remove memdep tracking for default pipeline
speculative load/store pipelines can reenable this
Korey Sewell [Mon, 20 Jun 2011 01:43:39 +0000 (21:43 -0400)]
inorder: fetchBuffer tracking
calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: redefine DynInst FP result type
Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: treat SE mode syscalls as a trapping instruction
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: bug in mdu
segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: optionally track faulting instructions
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: cleanup events in resource pool
remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
----
Also, match the resPool event function names to the cpu event function names
----
Korey Sewell [Mon, 20 Jun 2011 01:43:38 +0000 (21:43 -0400)]
inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: remove decode squash
also, cleanup comments for gem5.fast compilation
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: support for compare and swap insts
dont treat read() and write() fields as mut. exclusive
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: branch predictor update
only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: priority for grad/squash events
define separate priority resource pool squash and graduate events
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: remove stalls on trap squash
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
inorder: no dep. tracking for zero reg
this causes forwarding a bad value register value
Korey Sewell [Mon, 20 Jun 2011 01:43:37 +0000 (21:43 -0400)]
imported patch recoverPCfromTrap
Korey Sewell [Mon, 20 Jun 2011 01:43:36 +0000 (21:43 -0400)]
imported patch squash_from_next_stage
Korey Sewell [Mon, 20 Jun 2011 01:43:36 +0000 (21:43 -0400)]
inorder: add flatDestReg member to dyninst
use it in reg. dep. tracking
Korey Sewell [Mon, 20 Jun 2011 01:43:36 +0000 (21:43 -0400)]
inorder: update event priorities
dont use offset to calculate this but rather an enum
that can be updated
Korey Sewell [Mon, 20 Jun 2011 01:43:36 +0000 (21:43 -0400)]
inorder: implement trap handling
Korey Sewell [Mon, 20 Jun 2011 01:43:35 +0000 (21:43 -0400)]
inorder: cleanup intercomm. structs/squash info
Korey Sewell [Mon, 20 Jun 2011 01:43:35 +0000 (21:43 -0400)]
inorder: use setupSquash for misspeculation
implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
Korey Sewell [Mon, 20 Jun 2011 01:43:35 +0000 (21:43 -0400)]
sparc: init. cache state in TLB
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
Korey Sewell [Mon, 20 Jun 2011 01:43:35 +0000 (21:43 -0400)]
inorder: DynInst handling of stores for big-endian ISAs
The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC