Kevin Lim [Fri, 3 Mar 2006 20:41:57 +0000 (15:41 -0500)]
Remove intr_post function. No longer being used.
--HG--
extra : convert_revision :
1dc1d691244fd2edbd21d5cbf0764622d8f95fbb
Kevin Lim [Fri, 3 Mar 2006 20:28:25 +0000 (15:28 -0500)]
Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
The shadow registers are folded into the normal integer registers to ease renaming indexing.
Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.
arch/alpha/ev5.cc:
Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using.
Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.
Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).
Change the dependence tags to reflect the integer registers include the 8 shadow registers.
Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
Change from MachInst to ExtMachInst to support shadow register renaming.
--HG--
extra : convert_revision :
1d23eabf735e297068e1917445a6348e9f8c88d5
Kevin Lim [Tue, 28 Feb 2006 20:16:24 +0000 (15:16 -0500)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean
arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
Hand merge.
--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision :
c941dd2198851398820b38a66471372ed8454891
Gabe Black [Tue, 28 Feb 2006 11:28:09 +0000 (06:28 -0500)]
Corrected some mistakes in the hand merge
--HG--
extra : convert_revision :
84d852e625f754c4414403e8c3e26bda80500d4f
Gabe Black [Tue, 28 Feb 2006 11:17:57 +0000 (06:17 -0500)]
Hand merged
--HG--
extra : convert_revision :
0fd5ecbba5dc6299dd046926ec27595ca4d97ee7
Gabe Black [Tue, 28 Feb 2006 11:13:35 +0000 (06:13 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
Gabe Black [Tue, 28 Feb 2006 11:03:57 +0000 (06:03 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
3a3ff8fcf472db385219a00ae434d1f3fea43b18
Gabe Black [Tue, 28 Feb 2006 11:02:18 +0000 (06:02 -0500)]
Cleaned up and slightly reorganized the Fault class heirarchy.
arch/alpha/ev5.cc:
Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
AlphaFault is now an abstract class.
arch/alpha/faults.hh:
AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.
--HG--
extra : convert_revision :
2cb906708e3eaec4a12587484c09e50ed6ef88fc
Gabe Black [Tue, 28 Feb 2006 04:26:13 +0000 (23:26 -0500)]
Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
--HG--
extra : convert_revision :
56e33536cdd9079ace03896b85ea3c84b6eb4e57
Gabe Black [Mon, 27 Feb 2006 21:46:00 +0000 (16:46 -0500)]
Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes.
--HG--
extra : convert_revision :
0378261342df008c2bf6d260295ef21b15f119a8
Gabe Black [Mon, 27 Feb 2006 21:27:01 +0000 (16:27 -0500)]
Got rid of the fault_addr function.
--HG--
extra : convert_revision :
deb54cd82db47abb6d9bac76e072f2a4b1c883b2
Kevin Lim [Mon, 27 Feb 2006 17:09:08 +0000 (12:09 -0500)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean
--HG--
extra : convert_revision :
97c345f0715a347ce34f9cabd994485f30f2e171
Kevin Lim [Mon, 27 Feb 2006 16:44:35 +0000 (11:44 -0500)]
Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).
arch/alpha/alpha_memory.cc:
Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes.
The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
Change access to the IPR to go through the XC.
arch/isa_parser.py:
Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
Change accesses to the IPRs to go through the miscRegs.
For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
Remove old misc reg accessors.
cpu/o3/cpu.cc:
Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
Change accesses to the misc regs.
cpu/o3/regfile.hh:
Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
Have accesses to the misc regs use the new access methods.
--HG--
extra : convert_revision :
e32e0a3fe99522e17294bbe106ff5591cb1a9d76
Gabe Black [Mon, 27 Feb 2006 11:05:10 +0000 (06:05 -0500)]
Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision :
9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
Gabe Black [Mon, 27 Feb 2006 10:35:43 +0000 (05:35 -0500)]
Changed targetarch to just arch.
SConscript:
Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
Added all of the remaining targetarch files to isa_switch_hdrs
--HG--
extra : convert_revision :
a37d18349e27cf92dce12814f21944daa7fe9480
Gabe Black [Mon, 27 Feb 2006 09:05:02 +0000 (04:05 -0500)]
Fixed up some include paths.
kern/kernel_stats.cc:
Replaced targetarch with arch/alpha, since osfpal.hh is not a targetarched file.
--HG--
extra : convert_revision :
24a25f27e5912cb949568cf5fd0ab856771ba0d1
Gabe Black [Mon, 27 Feb 2006 09:02:45 +0000 (04:02 -0500)]
Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class, and replaced the isA templated function with them where appropriate.
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.
--HG--
extra : convert_revision :
3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
Gabe Black [Mon, 27 Feb 2006 09:00:24 +0000 (04:00 -0500)]
Put the Alpha faults into the AlphaISA namespace
--HG--
extra : convert_revision :
d9586bb8ffaab74673aa0b3d17bb676b949ff212
Gabe Black [Mon, 27 Feb 2006 08:57:15 +0000 (03:57 -0500)]
MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.
arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
MachineCheckFaults are now generated by the ISA, rather than being created directly.
--HG--
extra : convert_revision :
34a7da41639e93be21ed70dac681b27480008d19
Gabe Black [Mon, 27 Feb 2006 06:38:47 +0000 (01:38 -0500)]
Changed targetarch to arch for isa_traits.hh include
--HG--
extra : convert_revision :
e7ae43d812140ec99b782394e54903153f8d0476
Gabe Black [Mon, 27 Feb 2006 06:32:49 +0000 (01:32 -0500)]
Where architecture independent sources included arch/alpha/xxx.hh, they were changed to include targetarch/xxx.hh
cpu/base_dyn_inst.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/comm.hh:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/kernel_stats.cc:
Changed arch/alpha to targetarch
sim/process.cc:
Changed arch/alpha to targetarch, and removed gaurding ifdef
--HG--
extra : convert_revision :
3c29e6baeb1cd900f7b5e11144a5d547a6c7c5ab
Nathan Binkert [Mon, 27 Feb 2006 04:06:21 +0000 (23:06 -0500)]
fix some minor stats stuff
util/stats/stats.py:
fix up a few of the stats.
--HG--
extra : convert_revision :
61c600cd146900c8cc0cf60a9036f2e999a5e244
Nathan Binkert [Mon, 27 Feb 2006 01:31:08 +0000 (20:31 -0500)]
add some support for random access of data in packet fifos
dev/pktfifo.cc:
add support for copying arbitrary data out of a
packet fifo
dev/pktfifo.hh:
add support for copying arbitrary data out of a
packet fifo.
Add functions to determine where in the fifo a
particular packet is
--HG--
extra : convert_revision :
f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1
Nathan Binkert [Sun, 26 Feb 2006 15:44:01 +0000 (10:44 -0500)]
Allow graph_group to not be selected so we can have a
normal ungrouped barchart
--HG--
extra : convert_revision :
7d55440c9bb060607eddbb72448a3413944bb6ba
Nathan Binkert [Sun, 26 Feb 2006 06:00:15 +0000 (01:00 -0500)]
better function categorization
util/stats/categories.py:
bit more stuff for categorizing functions
--HG--
extra : convert_revision :
03617246a9254a580684dce82836517d1efdfc5b
Nathan Binkert [Sun, 26 Feb 2006 05:57:37 +0000 (00:57 -0500)]
fix small python bug in database processing code
util/stats/db.py:
fix usage of hasattr
--HG--
extra : convert_revision :
b384e1efeda76921c565f9f391694c27273edcec
Nathan Binkert [Sun, 26 Feb 2006 05:35:10 +0000 (00:35 -0500)]
code cleanup
util/stats/barchart.py:
clean up some of lisa's messy code
remove trailing whitespace while I'm at it.
--HG--
extra : convert_revision :
f2fe6777fb4b458fa1d5b5b743f6274014c229ad
Nathan Binkert [Sun, 26 Feb 2006 05:19:02 +0000 (00:19 -0500)]
forgot to add a chart option
util/stats/chart.py:
add a bool config option for determining
if the legend is inside or outside the figure
--HG--
extra : convert_revision :
e862d1832a0cc3c1837758cc247bc77c0a02ec12
Nathan Binkert [Sun, 26 Feb 2006 05:11:54 +0000 (00:11 -0500)]
add error bars and more options for legend placement
util/stats/barchart.py:
Add support for error bars
util/stats/barchart.py:
add support to choose between a legend inside or
outside the figure.
--HG--
extra : convert_revision :
14273e385c106bf27a2013991f9f34ca6551b96c
Nathan Binkert [Sun, 26 Feb 2006 04:48:13 +0000 (23:48 -0500)]
better colors for barcharts
util/stats/barchart.py:
If there are fewer than 5 colors, pick from a subset of
5 so there is more consistency in colors between graphs
--HG--
extra : convert_revision :
6cf64c2f8ed81e714e24a3ebe5a7a60ca168b231
Steve Reinhardt [Sun, 26 Feb 2006 03:57:46 +0000 (22:57 -0500)]
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when
CPU_MODELS parameter changes.
arch/SConscript:
Fix typo in comment.
cpu/SConscript:
Convert exec signature generator to Action so we can add dependency
on CPU_MODELS environment var.
Print nicer string while we're at it.
Also add some comments.
--HG--
extra : convert_revision :
bcb38a7941943cf071dac34cdbb2ece5456b8620
Nathan Binkert [Sun, 26 Feb 2006 03:03:47 +0000 (22:03 -0500)]
only build libelf.a, forget about the other
libelf junk.
--HG--
extra : convert_revision :
964473c0ff1fc2f8fd9fbb8a1533eb3730b61fac
Nathan Binkert [Sun, 26 Feb 2006 03:01:05 +0000 (22:01 -0500)]
Since the delayed write stuff is gone, get rid of regWrite
and merge it with writeBar0
--HG--
extra : convert_revision :
354642e0d528b6a5a7f2cdf0264d93e738b2d4eb
Gabe Black [Fri, 24 Feb 2006 23:45:46 +0000 (18:45 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
d3e160f6e938af5d2118883f8d7c91fa29a0ccaa
Gabe Black [Fri, 24 Feb 2006 23:45:28 +0000 (18:45 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
Hand merged
--HG--
extra : convert_revision :
318a671e6803400d3ed086a90e70d6790e4f6b19
Gabe Black [Fri, 24 Feb 2006 23:33:57 +0000 (18:33 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
c167d2bec89120258124bf34ada3adf23e3e8188
Lisa Hsu [Fri, 24 Feb 2006 23:08:55 +0000 (18:08 -0500)]
Merge zizzer:/bk/m5
into zed.eecs.umich.edu:/z/hsul/work/m5/clean
--HG--
extra : convert_revision :
34314698d4248a078c7b43125b2d048280ff576d
Lisa Hsu [Fri, 24 Feb 2006 23:08:14 +0000 (18:08 -0500)]
1) make it pretty for large clusters
2) make subticks vertical so they can be longer
3) make inner and outer axes farther apart to make room for subtick's vertical labels
--HG--
extra : convert_revision :
91a1aab3f1078921edd53428e6712744210c9f1b
Steve Reinhardt [Fri, 24 Feb 2006 13:52:38 +0000 (08:52 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch
arch/isa_parser.py:
SCCS merged
--HG--
extra : convert_revision :
080cca7616b37db3bf18976b63b3dbcb47d8b918
Gabe Black [Fri, 24 Feb 2006 08:51:21 +0000 (03:51 -0500)]
Removed a stray ::.
--HG--
extra : convert_revision :
f6114b78e30e8cba5af6276042b0f043d8773739
Gabe Black [Fri, 24 Feb 2006 06:51:45 +0000 (01:51 -0500)]
Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
Added news where faults are created.
arch/alpha/ev5.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
Added a new where an UnimplementedFault is created.
base/refcnt.hh:
Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
Added news where MachineCheckFaults are created.
dev/pcidev.hh:
Added news where MachineCheckFaults are generated.
dev/sinic.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
Changed Fault from a FaultBase * to a RefCountingPtr.
--HG--
extra : convert_revision :
b40ccfc42482d5a115e111dd897fa378d23c6c7d
Gabe Black [Fri, 24 Feb 2006 00:32:38 +0000 (19:32 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
77dc4dda9c72c871364e112ae8b10669b8d8fc86
Korey Sewell [Thu, 23 Feb 2006 23:46:12 +0000 (18:46 -0500)]
name changes ...
SConscript:
change to alpha_memory.hh
--HG--
rename : arch/alpha/memory.cc => arch/alpha/alpha_memory.cc
rename : arch/alpha/memory.hh => arch/alpha/alpha_memory.hh
extra : convert_revision :
62b1a41de22701160f04cb7a78242746cfcde819
Steve Reinhardt [Thu, 23 Feb 2006 22:00:29 +0000 (17:00 -0500)]
Enable building only selected CPU models via new scons
CPU_MODELS parameter. For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.
SConscript:
Separate out cpu-model-specific files so they can be conditionally
included based on value of new CPU_MODELS parameter.
Most of these are now handled in cpu/SConscript, except for FullCPU
which is still in this file.
arch/SConscript:
The set of CPU-model-specific execute files must now be
determined from the CPU_MODELS parameter, via the new
cpu_models.py file.
Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
Move CpuModel definition and objects out to a
separate file so they can be shared with scons.
Global list of CPU models to generate code for is now
controlled by command-line parameters (so we can do
only a subset of the available ones).
build/SConstruct:
Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
Rename static_inst_impl.hh to static_inst_exec_sigs.hh.
--HG--
extra : convert_revision :
163df32a76d4c05900490b2bce4c7962a5e3f614
Ali Saidi [Thu, 23 Feb 2006 20:08:08 +0000 (15:08 -0500)]
ev5.cc:
SCCS merged
arch/alpha/ev5.cc:
SCCS merged
--HG--
extra : convert_revision :
9d70c1d461dab0ec016fd0616d74a49942aac659
Ali Saidi [Thu, 23 Feb 2006 20:06:06 +0000 (15:06 -0500)]
Merge zizzer:/bk/m5
into zeep.eecs.umich.edu:/z/saidi/work/m5.head
cpu/simple/cpu.cc:
remove initCPU from constructor
dev/alpha_console.cc:
we are panicing, so no need to return a fault
--HG--
extra : convert_revision :
72389ea0c96e91a55f35b884200325224bfb6ed9
Ali Saidi [Thu, 23 Feb 2006 19:50:16 +0000 (14:50 -0500)]
Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.
arch/alpha/ev5.cc:
Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move the cpu initilization into an init() function since it now needs
the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
instead of the bootstrap variables, add space for 64 cpu stacks in the
alpha access structure.
sim/system.cc:
start all cpus immediately rather than just the first one
--HG--
extra : convert_revision :
28c218af49d885a0f203ada419f16f25d5a3f37b
Steve Reinhardt [Thu, 23 Feb 2006 19:31:15 +0000 (14:31 -0500)]
Create a Builder object for .isa files in arch/SConscript.
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.
SConscript:
Push isa_parser stuff (including .isa scanner) down into
arch/SConscript.
arch/SConscript:
Create a Builder object for .isa files, including existing scanner.
Return file objects generated by isa-specific SConscript
back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
Convert sources to scons File objects, so file names can be specified
relative to the current directory.
Invoke new builder for isa description, and get generated sources from
there (instead of listing them explicitly).
arch/isa_parser.py:
Get rid of third argument ("include_path").
It was a pain to generate this from scons, and it turned out
it's not needed anyway, since the only included file
(decoder.hh) will be in the same directory as the sources.
--HG--
extra : convert_revision :
36861bcef36763f229704d8cb7a642b4486a3581
Kevin Lim [Thu, 23 Feb 2006 18:27:23 +0000 (13:27 -0500)]
Cast enum to int to fix compile error from regression.
--HG--
extra : convert_revision :
2d998ec7393e1c08c7552f7e586160d579eab2b1
Steve Reinhardt [Thu, 23 Feb 2006 13:17:09 +0000 (08:17 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5
--HG--
extra : convert_revision :
38367d6d1fa594b84b64e5930588904719a40c08
Steve Reinhardt [Thu, 23 Feb 2006 13:16:59 +0000 (08:16 -0500)]
Add pipe() syscall to Alpha Linux emulation.
arch/alpha/alpha_linux_process.cc:
Add pipeFunc.
--HG--
extra : convert_revision :
c094d2dff993d5e60bc43b7cd4b9586c15c634a3
Gabe Black [Thu, 23 Feb 2006 09:11:09 +0000 (04:11 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
d92c611475aef2b911f76e2c21be12096e73048a
Gabe Black [Thu, 23 Feb 2006 09:08:55 +0000 (04:08 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
850077a56aead260aa4bbd3df60b672a931d57ed
Nathan Binkert [Thu, 23 Feb 2006 05:21:35 +0000 (00:21 -0500)]
don't add an empty suboption description
--HG--
extra : convert_revision :
594744c3d438aed08a23db376959930071b2c368
Nathan Binkert [Thu, 23 Feb 2006 05:20:32 +0000 (00:20 -0500)]
make it possible to add filters for job names so that
parts of the full crossproduct of jobs can be ignored.
--HG--
extra : convert_revision :
c44b3daea0cf4b487b1d99eae92da16573b15930
Nathan Binkert [Thu, 23 Feb 2006 05:00:01 +0000 (00:00 -0500)]
fix stat name
--HG--
extra : convert_revision :
4c0f8c1b6ba1e77dc302b8ece3c8822b9b4a05ee
Steve Reinhardt [Thu, 23 Feb 2006 03:22:06 +0000 (22:22 -0500)]
Auto-generate arch/foo.hh "switch headers" in scons.
SConscript:
Include new arch/SConscript file.
arch/isa_specific.hh:
Get rid of unnecessary ISA_INCLUDE() macro and other
things that were used only for that purpose.
build/SConstruct:
Move list of ISAs to env var ALL_ISA_LIST.
--HG--
extra : convert_revision :
612c7ee4279d57209662be88dc577d80fdbd692c
Steve Reinhardt [Thu, 23 Feb 2006 02:11:45 +0000 (21:11 -0500)]
Clean excess comments out of SConscripts.
SConscript:
arch/alpha/SConscript:
Clean out excess comments.
--HG--
extra : convert_revision :
7aae68d36f9fce5f236d117d803b5e3cd4a3769d
Gabe Black [Thu, 23 Feb 2006 01:52:03 +0000 (20:52 -0500)]
Cleaned up the mapping of isa_parser.py inputs to outputs.
--HG--
extra : convert_revision :
a8431a67001b2916eb8d0548f1f34e1c948bb356
Korey Sewell [Wed, 22 Feb 2006 09:08:08 +0000 (04:08 -0500)]
make sure alpha still compiles , rename files back to original naming ...
Now that we have decoder.do, add new files so we can start compiling other files
needed for MIPS syscall emulation mode
arch/mips/linux_process.cc:
arch/mips/linux_process.hh:
New MIPS-specific file
--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh
extra : convert_revision :
2bfc27e8772523cbeb95f40684f9a32fe5554f87
Korey Sewell [Wed, 22 Feb 2006 08:44:21 +0000 (03:44 -0500)]
Still builds "../MIPS_SE/arch/mips/decoder.do with no errors!
-----
uncomment out detailed model ... just commented to supress some compile errors
arch/isa_parser.py:
uncomment out detailed model ... just commented to supress some compile errors
--HG--
extra : convert_revision :
e884b9bd47794409f74043ad1aca6dadd1323185
Korey Sewell [Wed, 22 Feb 2006 08:33:35 +0000 (03:33 -0500)]
MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!
arch/mips/faults.hh:
remove nonsense
arch/mips/isa/base.isa:
define R31
arch/mips/isa/bitfields.isa:
forgotten bitfields
arch/mips/isa/decoder.isa:
INT64 -> int64_t
arch/mips/isa/formats.isa:
fix comments
arch/mips/isa/formats/branch.isa:
Branch -> BranchLikely
RB -> RT
arch/mips/isa/formats/fp.isa:
Make FP ops generates
arch/mips/isa/formats/mem.isa:
RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
Rc -> Rd
arch/mips/isa/formats/util.isa:
forgot brace and semicolon
arch/mips/isa/includes.isa:
remove unnecessary files
arch/mips/isa_traits.hh:
spacing
cpu/static_inst.hh:
add cond_delay_slot flag
--HG--
extra : convert_revision :
3bc7353b437f9a764e85cc462bed86c9d654eb37
Korey Sewell [Wed, 22 Feb 2006 03:06:18 +0000 (22:06 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch
--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
extra : convert_revision :
c641ba3c1009829b7276279b2dca441be1da5b30
Korey Sewell [Wed, 22 Feb 2006 03:02:05 +0000 (22:02 -0500)]
Renaming alpha files and changing some MIPS stuff to be more like Alpha version
SConscript:
changed the alpha_memory.hh to memory.hh in SConscript
arch/isa_parser.py:
temporarily comment out o3 model
arch/mips/isa/base.isa:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
Fix Up Base Class to mirror how Alpha generates StaticInsts
arch/mips/faults.cc:
MIPS fault.cc file
arch/mips/faults.hh:
MIPS fault.hh file
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision :
f92d6e765ca96a8b952aef79ed119fa29464563b
Gabe Black [Wed, 22 Feb 2006 01:10:40 +0000 (20:10 -0500)]
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision :
5b2f457401f8ff94fe39fe071288eb117814b7bb
Gabe Black [Tue, 21 Feb 2006 08:38:21 +0000 (03:38 -0500)]
Made Addr a global type
--HG--
extra : convert_revision :
869bd9fa5d8591115ac9b4a7401eb2490986b835
Gabe Black [Tue, 21 Feb 2006 04:55:25 +0000 (23:55 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
da72b3593037c2a67a56c799e292853b8aece907
Gabe Black [Tue, 21 Feb 2006 04:54:38 +0000 (23:54 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
9d386beecc6d13625ff19ca72cbc3628dcd59d3c
Gabe Black [Tue, 21 Feb 2006 04:53:14 +0000 (23:53 -0500)]
Finished the implementing the change of the ISA from a class to a namespace
dev/sinic.cc:
When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail.
--HG--
extra : convert_revision :
c003c714228491e060155070d192521c53d9e929
Nathan Binkert [Tue, 21 Feb 2006 04:41:50 +0000 (23:41 -0500)]
Get rid of the code that delays PIO write accesses
until the cache access occurs. The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
get rid of pio_delay write and the associated code to move
the write to the cache access function
dev/sinicreg.hh:
no more write delays
python/m5/objects/Ethernet.py:
get rid of pio_delay write
--HG--
extra : convert_revision :
1dcb51b8f4514e717bc334a782dfdf06d29ae69d
Korey Sewell [Mon, 20 Feb 2006 19:48:10 +0000 (14:48 -0500)]
make MIPS specific
--HG--
extra : convert_revision :
c019fad60fbf1a316bc6201b8ce8acf5a9875989
Korey Sewell [Mon, 20 Feb 2006 19:30:23 +0000 (14:30 -0500)]
load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision :
5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Korey Sewell [Mon, 20 Feb 2006 06:49:16 +0000 (01:49 -0500)]
Support for All Jump Instructions ...
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision :
63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
Gabe Black [Sun, 19 Feb 2006 09:00:05 +0000 (04:00 -0500)]
Reapplied changes which were undone by a pull
arch/alpha/faults.hh:
kern/linux/linux.hh:
Added typedef for Addr
kern/tru64/tru64.hh:
Fixed up namespaces
--HG--
extra : convert_revision :
bf968e615bc0acc96abeb0eec0872f5b02b5a065
Gabe Black [Sun, 19 Feb 2006 08:20:05 +0000 (03:20 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class dei
\7ff
\7ffinitions
--HG--
extra : convert_revision :
a600950d539be2be73358f072aa5426456bf3d2d
Gabe Black [Sun, 19 Feb 2006 08:04:44 +0000 (03:04 -0500)]
Remade some changes which were undone
cpu/base.hh:
cpu/static_inst.hh:
Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
Changed Fault back to Fault *
--HG--
extra : convert_revision :
410f2e2472f8aa5bf92619a5defdf85f689a5597
Gabe Black [Sun, 19 Feb 2006 07:34:52 +0000 (02:34 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
090b30a7f70294e1aeb13ba0bc15da4061bdf348
Gabe Black [Sun, 19 Feb 2006 07:34:37 +0000 (02:34 -0500)]
Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision :
91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
Ali Saidi [Sun, 19 Feb 2006 05:47:45 +0000 (00:47 -0500)]
Merge zizzer:/bk/m5
into pb15.local:/Users/ali/work/m5.head
--HG--
extra : convert_revision :
774e4afbb0f9c3ae62843138b6d7195ea184ff92
Ali Saidi [Sun, 19 Feb 2006 05:28:53 +0000 (00:28 -0500)]
forgot a negative sign
--HG--
extra : convert_revision :
9cdb00198979fca831d3e6840f9c534671ccead3
Ali Saidi [Sun, 19 Feb 2006 04:44:22 +0000 (23:44 -0500)]
Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way for solaris linux syscall emu.
SConscript:
Add two new files for syscall emulation
Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
Add getDesc function
kern/linux/linux.hh:
move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
Push the function determination and calling stuff down to LiveProcess
and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
fnctl implementation was identical in tru64 and linux so moved to generic
--HG--
extra : convert_revision :
103293dbe6fe2f7892de4929d17dc085def77026
Korey Sewell [Sun, 19 Feb 2006 04:17:45 +0000 (23:17 -0500)]
Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision :
df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Gabe Black [Sun, 19 Feb 2006 01:58:26 +0000 (20:58 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
8b2759d670a6a60142be748817ccef736d61dabf
Gabe Black [Sun, 19 Feb 2006 01:58:08 +0000 (20:58 -0500)]
Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture.
--HG--
extra : convert_revision :
5087333fbaf442efb4b55e70376244629fff507d
Lisa Hsu [Sun, 19 Feb 2006 01:10:42 +0000 (20:10 -0500)]
few changes for nate:
1) cosmetic - removing visibility of meta axes except for the tick labels.
2) unless subticklabels defined, don't do meta axes. (instead of assuming if you have 3D graph, do meta axes)
--HG--
extra : convert_revision :
396011ffaa51ea4066b34257f6fd5b3faac9d242
Lisa Hsu [Sat, 18 Feb 2006 23:39:19 +0000 (18:39 -0500)]
remove print statements
--HG--
extra : convert_revision :
abd635034424eeb9685aea777440a02887ce81a6
Lisa Hsu [Sat, 18 Feb 2006 22:29:43 +0000 (17:29 -0500)]
more changes for subtick labels.
util/stats/barchart.py:
oop forgot this for 1D graph cases.
util/stats/chart.py:
need to add default param to chart.
--HG--
extra : convert_revision :
f4e6c6c614d584e7928ed905e97608716455ab6c
Lisa Hsu [Sat, 18 Feb 2006 22:24:37 +0000 (17:24 -0500)]
Merge zizzer:/bk/m5
into zed.eecs.umich.edu:/z/hsul/work/m5/clean
--HG--
extra : convert_revision :
5f7c75eb3f82d9b04edc0efece3b054b5d0fe81f
Lisa Hsu [Sat, 18 Feb 2006 22:24:23 +0000 (17:24 -0500)]
Now you can have sublabels for every bar using the self.xsubticklabels parameter.
--HG--
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a6bdf3a972e81c84947b7d6ae76f828494a125c8
Korey Sewell [Sat, 18 Feb 2006 19:38:23 +0000 (14:38 -0500)]
changes from mergedmem
arch/mips/isa/formats/branch.isa:
add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
change from mergedmem
--HG--
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d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
Korey Sewell [Sat, 18 Feb 2006 09:17:11 +0000 (04:17 -0500)]
use string name to figure out if we have a "AndLink" instruction
arch/mips/isa/operands.isa:
uq -> uw
--HG--
extra : convert_revision :
eeac6dba813de8174d080a5fa9b5a396b345113a
Korey Sewell [Sat, 18 Feb 2006 08:12:04 +0000 (03:12 -0500)]
MIPS generates ISA code through scons '.../decoder.cc'!!!
Now, must create g++ compilable code ...
arch/mips/isa/decoder.isa:
missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
rearranged #include
arch/mips/isa/formats/branch.isa:
add Branch Likely and Unconditional format
arch/mips/isa/formats/int.isa:
move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
change Alpha to Mips in noop.isa
--HG--
extra : convert_revision :
4bf955fa6dffbbc99fb95fee7878f691e3df5424
Kevin Lim [Fri, 17 Feb 2006 20:07:48 +0000 (15:07 -0500)]
Get rid of deque (poor memory allocation), switch them over to lists.
Beware that using size() on a list is a O(n) operation.
dev/ns_gige.hh:
Remove typedefs that (I assume) were copied over from etherdev.hh. They were unused in the ns_gige code.
--HG--
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577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c
Kevin Lim [Thu, 16 Feb 2006 19:55:15 +0000 (14:55 -0500)]
Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.
arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
Remove fake fault.
arch/alpha/faults.cc:
Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
Remove fake fault, change pointers to const pointers.
--HG--
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01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
Kevin Lim [Thu, 16 Feb 2006 17:03:44 +0000 (12:03 -0500)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new
arch/alpha/isa/mem.isa:
Hand merge.
--HG--
extra : convert_revision :
c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
Kevin Lim [Thu, 16 Feb 2006 16:55:28 +0000 (11:55 -0500)]
Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa:
Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both).
Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
Remove hack for mem ops.
--HG--
extra : convert_revision :
a367797a2cb698762bfc27be1da00bcbe9367150
Korey Sewell [Thu, 16 Feb 2006 07:51:04 +0000 (02:51 -0500)]
Get ISA parser to at least include all the ISA correctly ... crashes with "None" error
arch/mips/isa/decoder.isa:
CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
include util.isa
arch/mips/isa/formats/branch.isa:
erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
util.isa
--HG--
extra : convert_revision :
4fc44a05e2838749e66cd70f210e8a718b34cbf3
Korey Sewell [Thu, 16 Feb 2006 07:40:04 +0000 (02:40 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
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17b164847aee7e21d15d1a9d99aae43f46906c28
Korey Sewell [Thu, 16 Feb 2006 07:39:46 +0000 (02:39 -0500)]
file name changes ... minor ISA changes
arch/mips/isa/base.isa:
restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
add c++ emacs header
arch/mips/isa/formats/branch.isa:
added branch likely format
arch/mips/isa/formats/int.isa:
small change to python code
--HG--
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defd592abb1a724f5f88b19c197b858420e92d17
Gabe Black [Thu, 16 Feb 2006 07:08:13 +0000 (02:08 -0500)]
Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason.
arch/alpha/ev5.cc:
Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
Changed Fault to Fault *, and removed underscores from fault names.
--HG--
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367a58a375f911185ddcc5fc826034af96427461