mesa.git
5 years agovirgl: make alignment smaller when uploading index user buffers
Gurchetan Singh [Thu, 3 Jan 2019 00:27:56 +0000 (16:27 -0800)]
virgl: make alignment smaller when uploading index user buffers

Since we're just uploading to guest memory, let's just align to dword
size.

Fixes: e0f932 ("u_upload_mgr: pass alignment to u_upload_data manually")
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: track level cleanliness rather than resource cleanliness
Gurchetan Singh [Sat, 12 Jan 2019 01:38:55 +0000 (17:38 -0800)]
virgl: track level cleanliness rather than resource cleanliness

This allows a minor optimization for texture upload.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: don't mark unclean after a flush
Gurchetan Singh [Sat, 12 Jan 2019 01:49:59 +0000 (17:49 -0800)]
virgl: don't mark unclean after a flush

The guest memory is still clean until host GL touches it,
which we should track elsewhere.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: use virgl_resource_dirty helper
Gurchetan Singh [Sat, 12 Jan 2019 01:29:49 +0000 (17:29 -0800)]
virgl: use virgl_resource_dirty helper

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: add ability to do finer grain dirty tracking
Gurchetan Singh [Fri, 11 Jan 2019 23:37:15 +0000 (15:37 -0800)]
virgl: add ability to do finer grain dirty tracking

There are levels to cleanliness.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
5 years agopanfrost: Improve logging and patch memory leaks
Alyssa Rosenzweig [Thu, 14 Feb 2019 04:00:19 +0000 (04:00 +0000)]
panfrost: Improve logging and patch memory leaks

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Don't align framebuffer dims
Alyssa Rosenzweig [Fri, 15 Feb 2019 07:43:43 +0000 (07:43 +0000)]
panfrost: Don't align framebuffer dims

Fixes regressions with EGL clients

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Implement PIPE_QUERY_OCCLUSION_COUNTER
Alyssa Rosenzweig [Thu, 14 Feb 2019 02:50:30 +0000 (02:50 +0000)]
panfrost: Implement PIPE_QUERY_OCCLUSION_COUNTER

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Identify MALI_OCCLUSION_PRECISE bit
Alyssa Rosenzweig [Thu, 14 Feb 2019 02:44:03 +0000 (02:44 +0000)]
panfrost: Identify MALI_OCCLUSION_PRECISE bit

Setting this is required for desktop-style occlusion queries.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agodrirc/i965: add option to disable 565 configs and visuals
Tapani Pälli [Tue, 12 Feb 2019 06:08:23 +0000 (08:08 +0200)]
drirc/i965: add option to disable 565 configs and visuals

We have cases where we would not like to expose these.

v2: call the option allow_rgb565_configs for consistency
    with existing allow_rgb10_configs (Eric, Jason)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopanfrost: Backport driver to Mali T600/T700
Alyssa Rosenzweig [Sun, 10 Feb 2019 20:06:21 +0000 (20:06 +0000)]
panfrost: Backport driver to Mali T600/T700

There are a few differenes between Mali T860 (Panfrost's primary
reference target) and the older Midgard generations (T600/T700):

 - Miscellaneous different magic numbers. It's not clear what these
numbers mean on either the old or new configurations yet.

 - Errata fixes. T800 is the final Midgard generation and presumably the
least buggy. Older Midgard has some extra hardware errata we have to
workaround.

- SFBD vs MFBD split. Essentially, older Midgard use a Single
FrameBuffer Descriptor (SFBD), which corresponds to single
render-target rendering. Newer Midgard (T760+) use a Multiple
FrameBuffer Descriptor (MFBD), allowing multiple RTs. On ES 2.0, these
descriptors serve the same function, but we implement both, depending on
the version of the hardware.

- CPU bitness. 32-bit systems generally use 32-bit GPU descriptors, and
vice versa for 64-bit. Our target T760 systems are 32-bit whereas our
target T860 systems are 64-bit. More work is needed in this area.

This patch fixes support in these areas for supporting older Midgard
hardware. It is tested on Mali T760 and Mali T860.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Fix build; depend on libdrm
Alyssa Rosenzweig [Fri, 15 Feb 2019 02:18:39 +0000 (02:18 +0000)]
panfrost: Fix build; depend on libdrm

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agonir/dead_cf: Stop relying on liveness analysis
Jason Ekstrand [Thu, 14 Feb 2019 03:42:39 +0000 (21:42 -0600)]
nir/dead_cf: Stop relying on liveness analysis

The liveness analysis pass is fairly expensive because it has to build
large bit-sets and run a fix-point algorithm on them.  Instead of
requiring liveness for detecting if values escape a CF node, just take
advantage of the structured nature of NIR and use block indices instead.
This only requires the block index metadata which is the fastest we have
metadata to generate.

No shader-db changes on Kaby Lake

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agonir/dead_cf: Inline cf_node_has_side_effects
Jason Ekstrand [Thu, 14 Feb 2019 03:28:07 +0000 (21:28 -0600)]
nir/dead_cf: Inline cf_node_has_side_effects

We want to handle live SSA values differently and it's going to involve
walking the instructions.  We can make it a single instruction walk if
we combine it with cf_node_has_side_effects.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agointel/fs: Bail in optimize_extract_to_float if we have modifiers
Jason Ekstrand [Tue, 12 Feb 2019 04:39:45 +0000 (22:39 -0600)]
intel/fs: Bail in optimize_extract_to_float if we have modifiers

This fixes a bug in runscape where we were optimizing x >> 16 to an
extract and then negating and converting to float.  The NIR to fs pass
was dropping the negate on the floor breaking a geometry shader and
causing it to render nothing.

Fixes: 1f862e923cb "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
5 years agoswr: set PIPE_CAP_MAX_VARYINGS correctly
Ilia Mirkin [Thu, 14 Feb 2019 03:32:25 +0000 (22:32 -0500)]
swr: set PIPE_CAP_MAX_VARYINGS correctly

Unfortunately swr was missed in the original commit. The number of
varyings should generally match up to what's reported as the shader
caps for fragment inputs.

Fixes: 6010d7b8e8be (gallium: add PIPE_CAP_MAX_VARYINGS)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Alok Hota <alok.hota@intel.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
5 years agointel/fs: Silence a compiler warning
Jason Ekstrand [Thu, 14 Feb 2019 20:42:20 +0000 (14:42 -0600)]
intel/fs: Silence a compiler warning

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoanv: Silence some compiler warnings in release builds
Jason Ekstrand [Thu, 14 Feb 2019 20:37:51 +0000 (14:37 -0600)]
anv: Silence some compiler warnings in release builds

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoanv/blorp: Delete a pointless assert
Jason Ekstrand [Thu, 14 Feb 2019 20:36:49 +0000 (14:36 -0600)]
anv/blorp: Delete a pointless assert

Just a little higher up in the function we assert that the aspect masks
are actually equal so there's no reason for the weaker check.  Also, the
temporary variables were causing compiler warnings in release builds.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agonir: Silence a couple of warnings in release builds
Jason Ekstrand [Thu, 14 Feb 2019 20:33:34 +0000 (14:33 -0600)]
nir: Silence a couple of warnings in release builds

[28/716] Compiling C object 'src/compiler/nir/068b2c8@@nir@sta/nir_gather_xfb_info.c.o'.
../src/compiler/nir/nir_gather_xfb_info.c: In function ‘nir_gather_xfb_info’:
../src/compiler/nir/nir_gather_xfb_info.c:171:13: warning: variable ‘max_offset’ set but not used [-Wunused-but-set-variable]
    unsigned max_offset[NIR_MAX_XFB_BUFFERS] = {0};
             ^~~~~~~~~~
[36/716] Compiling C object 'src/compiler/nir/068b2c8@@nir@sta/nir_instr_set.c.o'.
../src/compiler/nir/nir_instr_set.c:502:1: warning: ‘instr_each_src_and_dest_is_ssa’ defined but not used [-Wunused-function]
 instr_each_src_and_dest_is_ssa(nir_instr *instr)
 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agospirv: Eliminate dead input/output variables after translation.
Kenneth Graunke [Thu, 7 Feb 2019 00:45:25 +0000 (16:45 -0800)]
spirv: Eliminate dead input/output variables after translation.

spirv_to_nir can generate input/output variables which are illegal
for the current shader stage, which would cause nir_validate_shader
to balk.  After my recent commit to start decorating arrays as compact,
dEQP-VK.spirv_assembly.instruction.graphics.module.same_module started
hitting validation errors due to outputs in a TCS (not intended for the
TCS at all) not being per-vertex arrays.

Thanks to Jason Ekstrand for suggesting this approach.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109573
Fixes: ef99f4c8d17 compiler: Mark clip/cull distance arrays as compact before lowering.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
5 years agoanv: Put MOCS in the correct location
Kenneth Graunke [Thu, 14 Feb 2019 16:55:37 +0000 (08:55 -0800)]
anv: Put MOCS in the correct location

My patch to switch from struct-based MOCS to numeric MOCS accidentally
divided all MOCS entries by 2 in the Vulkan driver.

MOCS on Gen9+ is just an array index into a table.  But in the hardware
packets, the index starts at bit 1.  So we need to shift it.

Fixes: 0b44644ca68 (genxml: Consistently use a numeric "MOCS" field)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agospirv: Add missing break
Ian Romanick [Wed, 13 Feb 2019 23:01:16 +0000 (15:01 -0800)]
spirv: Add missing break

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics")
CID: 1442555

5 years agoutil/tests: compile to something sensible in release builds
Eric Engestrom [Thu, 14 Feb 2019 10:30:47 +0000 (10:30 +0000)]
util/tests: compile to something sensible in release builds

assert()-based tests make no sense without asserts, so make sure asserts
are compiled in, even if the rest of the code has asserts turned off.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv/tests: compile to something sensible in release builds
Eric Engestrom [Thu, 14 Feb 2019 10:25:26 +0000 (10:25 +0000)]
anv/tests: compile to something sensible in release builds

assert()-based tests make no sense without asserts, so make sure asserts
are compiled in, even if the rest of the code has asserts turned off.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoetnaviv: drop duplicate #define
Eric Engestrom [Tue, 12 Feb 2019 16:13:51 +0000 (16:13 +0000)]
etnaviv: drop duplicate #define

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agost/dri: drop duplicate #define
Eric Engestrom [Tue, 12 Feb 2019 16:13:30 +0000 (16:13 +0000)]
st/dri: drop duplicate #define

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agogbm: drop duplicate #defines
Eric Engestrom [Tue, 12 Feb 2019 16:12:16 +0000 (16:12 +0000)]
gbm: drop duplicate #defines

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agodrm-uapi: use local files, not system libdrm
Eric Engestrom [Tue, 12 Feb 2019 18:18:03 +0000 (18:18 +0000)]
drm-uapi: use local files, not system libdrm

There was an issue recently caused by the system header being included
by mistake, so let's just get rid of this include path and always
explicitly #include "drm-uapi/FOO.h"

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agodrm-uapi/README: remove explicit list of driver names
Eric Engestrom [Tue, 12 Feb 2019 13:17:37 +0000 (13:17 +0000)]
drm-uapi/README: remove explicit list of driver names

These headers are used by a lot more than just the intel drivers nowadays.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agoradv: fix radv_fixup_vertex_input_fetches()
Samuel Pitoiset [Thu, 14 Feb 2019 08:43:36 +0000 (09:43 +0100)]
radv: fix radv_fixup_vertex_input_fetches()

We should check that num_channels is 4, otherwise that breaks
the world. Sorry for the short breakage.

Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex input fetches")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: reduce the number of loaded channels for vertex input fetches
Samuel Pitoiset [Tue, 12 Feb 2019 14:09:32 +0000 (15:09 +0100)]
radv: reduce the number of loaded channels for vertex input fetches

It's unnecessary to load more channels than the vertex attribute
format. The remaining channels are filled with 0 for y and z,
and 1 for w.

29077 shaders in 15096 tests
Totals:
SGPRS: 1321605 -> 1318869 (-0.21 %)
VGPRS: 935236 -> 932252 (-0.32 %)
Spilled SGPRs: 24860 -> 24776 (-0.34 %)
Code Size: 49832348 -> 49819464 (-0.03 %) bytes
Max Waves: 242101 -> 242611 (0.21 %)

Totals from affected shaders:
SGPRS: 93675 -> 90939 (-2.92 %)
VGPRS: 58016 -> 55032 (-5.14 %)
Spilled SGPRs: 172 -> 88 (-48.84 %)
Code Size: 2862740 -> 2849856 (-0.45 %) bytes
Max Waves: 15474 -> 15984 (3.30 %)

This mostly helps Croteam games (Talos/Sam2017).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: store vertex attribute formats as pipeline keys
Samuel Pitoiset [Tue, 12 Feb 2019 14:09:31 +0000 (15:09 +0100)]
radv: store vertex attribute formats as pipeline keys

The formats will be used for reducing the number of loaded channels.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: use MAX_{VBS,VERTEX_ATTRIBS} when defining max vertex input limits
Samuel Pitoiset [Tue, 12 Feb 2019 14:09:30 +0000 (15:09 +0100)]
radv: use MAX_{VBS,VERTEX_ATTRIBS} when defining max vertex input limits

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: make use of ac_build_expand_to_vec4() in visit_image_store()
Samuel Pitoiset [Tue, 12 Feb 2019 14:09:29 +0000 (15:09 +0100)]
ac: make use of ac_build_expand_to_vec4() in visit_image_store()

And make ac_build_expand() a static function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agofreedreno: Use the NIR lowering for isign.
Eric Anholt [Wed, 6 Feb 2019 21:32:21 +0000 (13:32 -0800)]
freedreno: Use the NIR lowering for isign.

I think this will save an instruction and hopefully not increase any other
costs (possibly the immediate -1 and 1?), but I haven't actually tested.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agointel: Use the NIR lowering for isign.
Eric Anholt [Wed, 6 Feb 2019 21:26:17 +0000 (13:26 -0800)]
intel: Use the NIR lowering for isign.

Drops one instruction from fs-sign-int.shader_test.  No change in
shader-db due to it having 0 instances of sign(genIType).  This may hurt
isign64 if algebraic runs before int64 lowering, but I wasn't sure how to
mark the algebraic opt as "every bit size but 64".

v2: Update commit message about shader-db.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
5 years agov3d: Use the NIR lowering for isign instead of rolling our own.
Eric Anholt [Wed, 6 Feb 2019 21:17:21 +0000 (13:17 -0800)]
v3d: Use the NIR lowering for isign instead of rolling our own.

min/max instead of comparisons saves 2 instructions on
fs-sign-int.shader_test.

5 years agonir: Move panfrost's isign lowering to nir_opt_algebraic.
Eric Anholt [Wed, 6 Feb 2019 21:12:25 +0000 (13:12 -0800)]
nir: Move panfrost's isign lowering to nir_opt_algebraic.

I wanted to reuse this from v3d.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agonir: turn an ssa check in nir_search into an assert
Timothy Arceri [Wed, 13 Feb 2019 05:09:20 +0000 (16:09 +1100)]
nir: turn an ssa check in nir_search into an assert

Everything should be in ssa form when we call this. This is a
hotpath so replace the check with an assert.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
5 years agonir: turn ssa check into an assert
Timothy Arceri [Wed, 13 Feb 2019 04:27:29 +0000 (15:27 +1100)]
nir: turn ssa check into an assert

Everthing should be in ssa form when this is called. Checking
for it here is expensive so turn this into an assert instead.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
5 years agonir: prehash instruction in nir_instr_set_add_or_rewrite()
Timothy Arceri [Wed, 13 Feb 2019 04:17:44 +0000 (15:17 +1100)]
nir: prehash instruction in nir_instr_set_add_or_rewrite()

There is no need to hash the instruction twice, especially as we
end up adding it in the majority of cases.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agomeson: Add dependency on genxml to anvil
Dylan Baker [Wed, 13 Feb 2019 17:26:16 +0000 (09:26 -0800)]
meson: Add dependency on genxml to anvil

Currently the Intel "anvil" driver races with the generation of genxml
files, while i965 has an explicit dependency. This patch adds the same
dependency to anvil.

Fixes: d1992255bb29054fa51763376d125183a9f602f
       ("meson: Add build Intel "anv" vulkan driver")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoradv: always export gl_SampleMask when the fragment shader uses it
Samuel Pitoiset [Tue, 12 Feb 2019 08:50:15 +0000 (09:50 +0100)]
radv: always export gl_SampleMask when the fragment shader uses it

For some reasons, this breaks trees rendering in Project Cars.

Fixes: 85010585cde ("radv: only enable gl_SampleMask if MSAA is enabled too")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agogallium/aux: add PIPE_CAP_MAX_VARYINGS to u_screen
Alok Hota [Mon, 11 Feb 2019 18:59:05 +0000 (12:59 -0600)]
gallium/aux: add PIPE_CAP_MAX_VARYINGS to u_screen

Allows drivers using `u_pipe_screen_get_param_defaults` to use a
fallback value for the new pipe cap. Default value of 8 based on GL 2.1
MAX_VARYING_FLOATS

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years ago.mailmap: Add a few more alises for myself
Kristian H. Kristensen [Wed, 13 Feb 2019 20:02:39 +0000 (12:02 -0800)]
.mailmap: Add a few more alises for myself

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agoradv/winsys: fix BO list creation when RADV_DEBUG=allbos is set
Samuel Pitoiset [Wed, 13 Feb 2019 17:51:23 +0000 (18:51 +0100)]
radv/winsys: fix BO list creation when RADV_DEBUG=allbos is set

Fixes: 50fd253bd6e ("radv/winsys: Add priority handling during submit.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agofreedreno/a6xx: Fix point coord
Kristian H. Kristensen [Tue, 12 Feb 2019 18:17:55 +0000 (10:17 -0800)]
freedreno/a6xx: Fix point coord

Use ir3_next_varying() for iterating through varyings and unset the
global point coord invert bit.

Fixes:

  dEQP-GLES3.functional.shaders.builtin_variable.pointcoord

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Front facing needs UNK3 bit
Kristian H. Kristensen [Tue, 12 Feb 2019 05:51:09 +0000 (21:51 -0800)]
freedreno/a6xx: Front facing needs UNK3 bit

We need to set UNK3 in GRAS_CNTL and RB_RENDER_CONTROL0 for the value
to be reliably delivered.

Fixes:

  dEQP-GLES3.functional.shaders.builtin_variable.frontfacing

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Update headers
Kristian H. Kristensen [Tue, 12 Feb 2019 05:50:21 +0000 (21:50 -0800)]
freedreno/a6xx: Update headers

This pulls in changes for compute shaders and a6xx ssbo/image support.
FACENESS bit moved from position 1 to 2 and there's a global invert
bit for point coord.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Clean up mixed use of swap and swizzle for texture state
Kristian H. Kristensen [Mon, 11 Feb 2019 23:09:21 +0000 (15:09 -0800)]
freedreno/a6xx: Clean up mixed use of swap and swizzle for texture state

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: small compiler warning fix
Rob Clark [Wed, 13 Feb 2019 18:54:05 +0000 (13:54 -0500)]
freedreno/a6xx: small compiler warning fix

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agoget-pick-list: Add --pretty=medium to the arguments for Cc patches
Dylan Baker [Tue, 12 Feb 2019 22:03:21 +0000 (14:03 -0800)]
get-pick-list: Add --pretty=medium to the arguments for Cc patches

Because none of them have been picked up for 19.0 due to this bug
being reintroduced.

v2: - Fix fixes tags

Fixes: e6b3a3b2014413366110f6deeced8095e7262b1d
       ("bin/get-pick-list.sh: handle "typod" usecase.")
Fixes: fac10169bbad2da918ef07a62c01e0b321508cfe
       ("bin/get-pick-list.sh: prefix output with "[stable] "")
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agogitlab-ci: limit ninja to 4 threads max
Eric Engestrom [Wed, 13 Feb 2019 14:25:45 +0000 (14:25 +0000)]
gitlab-ci: limit ninja to 4 threads max

I tried bumping the limit on make and scons instead, but that just
thrashed the runners, so let's not do that (sorry @daniels :]).

Instead, remove the automatic thread management from ninja and limit it
to 4 instead, in line with make and scons.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agomapi: work around GCC LTO dropping assembly-defined functions
Konstantin Kharlamov [Sun, 3 Feb 2019 18:36:32 +0000 (21:36 +0300)]
mapi: work around GCC LTO dropping assembly-defined functions

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109391

Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agonir: fix example in opt_peel_loop_initial_if description
Caio Marcelo de Oliveira Filho [Mon, 11 Feb 2019 19:55:19 +0000 (11:55 -0800)]
nir: fix example in opt_peel_loop_initial_if description

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir/opt_if: don't mark progress if nothing changes
Karol Herbst [Tue, 12 Feb 2019 19:59:35 +0000 (20:59 +0100)]
nir/opt_if: don't mark progress if nothing changes

if we have something like this:

loop {
   ...
   if x {
      break;
   } else {
      continue;
   }
}

opt_if_loop_last_continue returns true marking progress allthough nothing
changes.

Fixes: 5921a19d4b0c6 "nir: add if opt opt_if_loop_last_continue()"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradeonsi: Fix guardband computation for large render targets
Oscar Blumberg [Tue, 12 Feb 2019 20:52:51 +0000 (21:52 +0100)]
radeonsi: Fix guardband computation for large render targets

Stop using 12.12 quantization for viewports that are not contained in
the lower 4k corner of the render target as the hardware needs to keep
both absolute and relative coordinates representable.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
5 years agoegl: fix KHR_partial_update without EXT_buffer_age
Chia-I Wu [Thu, 7 Feb 2019 23:11:57 +0000 (15:11 -0800)]
egl: fix KHR_partial_update without EXT_buffer_age

EGL_BUFFER_AGE_EXT can be queried without EXT_buffer_age.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agomesa: Advertise EXT_float_blend in ES 3.0+ contexts.
Kenneth Graunke [Fri, 8 Feb 2019 05:58:57 +0000 (21:58 -0800)]
mesa: Advertise EXT_float_blend in ES 3.0+ contexts.

This extension simply drops a draw time restriction:

    "Furthermore, an INVALID_OPERATION error is generated by
     DrawArrays and the other drawing commands defined in section
     2.8.3 (10.5 in ES 3.1) if blending is enabled (see below) and
     any draw buffer has 32-bit floating-point format components."

We never correctly enforced this restriction anyway, so we were
basically already implementing it.  We just need to advertise it
for our behavior to be correct.

The extension requires EXT_color_buffer_float, but we already enable
that via dummy_true.  So we can dummy_true this one as well.

Found while debugging WebGL conformance tests.  Does not fix any.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
5 years agogallium/swr: Param defaults for unhandled PIPE_CAPs
Alok Hota [Wed, 30 Jan 2019 16:43:40 +0000 (10:43 -0600)]
gallium/swr: Param defaults for unhandled PIPE_CAPs

Without using this function, we fail the -Wswitch flag when compiling
the default debugoptimized mode in Meson

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoanv/cmd_buffer: check for NULL framebuffer
Juan A. Suarez Romero [Tue, 12 Feb 2019 18:19:13 +0000 (19:19 +0100)]
anv/cmd_buffer: check for NULL framebuffer

This can happen when we record a VkCmdDraw in a secondary buffer that
was created inheriting from the primary buffer, but with the framebuffer
set to NULL in the VkCommandBufferInheritanceInfo.

Vulkan 1.1.81 spec says that "the application must ensure (using scissor
if neccesary) that all rendering is contained in the render area [...]
[which] must be contained within the framebuffer dimesions".

While this should be done by the application, commit 465e5a86 added the
clamp to the framebuffer size, in case of application does not do it.
But this requires to know the framebuffer dimensions.

If we do not have a framebuffer at that moment, the best compromise we
can do is to just apply the scissor as it is, and let the application to
ensure the rendering is contained in the render area.

v2: do not clamp to framebuffer if there isn't a framebuffer

v3 (Jason):
- clamp earlier in the conditional
- clamp to render area if command buffer is primary

v4: clamp also x and y to render area (Jason)

v5: rename used variables (Jason)

Fixes: 465e5a86 ("anv: Clamp scissors to the framebuffer boundary")
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradeonsi: use MEM instead of MEM_GRBM in COPY_DATA.DST_SEL
Marek Olšák [Sat, 9 Feb 2019 01:20:41 +0000 (20:20 -0500)]
radeonsi: use MEM instead of MEM_GRBM in COPY_DATA.DST_SEL

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
5 years agoradeonsi: add AMD_DEBUG env var as an alternative to R600_DEBUG
Marek Olšák [Thu, 7 Feb 2019 05:02:33 +0000 (00:02 -0500)]
radeonsi: add AMD_DEBUG env var as an alternative to R600_DEBUG

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
5 years agoradv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
Samuel Pitoiset [Tue, 12 Feb 2019 08:01:50 +0000 (09:01 +0100)]
radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8

This fixes a critical issue.

Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109575
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: add support for push constants inlining when possible
Samuel Pitoiset [Tue, 5 Feb 2019 19:22:01 +0000 (20:22 +0100)]
radv: add support for push constants inlining when possible

This removes some scalar loads from shaders, but it increases
the number of SET_SH_REG packets. This is currently basic but
it could be improved if needed. Inlining dynamic offsets might
also help.

Original idea from Dave Airlie.

29077 shaders in 15096 tests
Totals:
SGPRS: 1321325 -> 1357101 (2.71 %)
VGPRS: 936000 -> 932576 (-0.37 %)
Spilled SGPRs: 24804 -> 24791 (-0.05 %)
Code Size: 49827960 -> 49642232 (-0.37 %) bytes
Max Waves: 242007 -> 242700 (0.29 %)

Totals from affected shaders:
SGPRS: 290989 -> 326765 (12.29 %)
VGPRS: 244680 -> 241256 (-1.40 %)
Spilled SGPRs: 1442 -> 1429 (-0.90 %)
Code Size: 8126688 -> 7940960 (-2.29 %) bytes
Max Waves: 80952 -> 81645 (0.86 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: keep track of the number of remaining user SGPRs
Samuel Pitoiset [Tue, 5 Feb 2019 19:22:00 +0000 (20:22 +0100)]
radv: keep track of the number of remaining user SGPRs

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: gather if shaders load dynamic offsets separately
Samuel Pitoiset [Tue, 5 Feb 2019 19:21:59 +0000 (20:21 +0100)]
radv: gather if shaders load dynamic offsets separately

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: gather more info about push constants
Samuel Pitoiset [Tue, 5 Feb 2019 19:21:58 +0000 (20:21 +0100)]
radv: gather more info about push constants

This is needed in order to inline some push constants when possible.
This also adds a new helper for initializing the pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: fix compiler issues with GCC 9
Samuel Pitoiset [Mon, 11 Feb 2019 09:17:52 +0000 (10:17 +0100)]
radv: fix compiler issues with GCC 9

"The C standard says that compound literals which occur inside of
the body of a function have automatic storage duration associated
with the enclosing block. Older GCC releases were putting such
compound literals into the scope of the whole function, so their
lifetime actually ended at the end of containing function. This
has been fixed in GCC 9. Code that relied on this extended lifetime
needs to be fixed, move the compound literals to whatever scope
they need to accessible in."

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109543
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoi965: add P0x formats and propagate required scaling factors
Tapani Pälli [Mon, 11 Feb 2019 08:12:45 +0000 (10:12 +0200)]
i965: add P0x formats and propagate required scaling factors

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lin Johnson <johnson.lin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/compiler: add scale_factors to sampler_prog_key_data
Tapani Pälli [Mon, 11 Feb 2019 08:06:09 +0000 (10:06 +0200)]
intel/compiler: add scale_factors to sampler_prog_key_data

Patch propagates given scale_factors to lowering options.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agodri: add P010, P012, P016 for 10bit/12bit/16bit YUV420 formats
Tapani Pälli [Mon, 11 Feb 2019 08:01:35 +0000 (10:01 +0200)]
dri: add P010, P012, P016 for 10bit/12bit/16bit YUV420 formats

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lin Johnson <johnson.lin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agonir: add option to use scaling factor when sampling planes YUV lowering
Tapani Pälli [Mon, 11 Feb 2019 07:25:18 +0000 (09:25 +0200)]
nir: add option to use scaling factor when sampling planes YUV lowering

Patch adds nir_lower_tex_options as parameter to sample_plane so that
we don't need to extend nir_tex_instr for this.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoi965: Use info->textures_used instead of prog->SamplersUsed.
Kenneth Graunke [Mon, 11 Feb 2019 03:53:40 +0000 (19:53 -0800)]
i965: Use info->textures_used instead of prog->SamplersUsed.

prog->SamplersUsed is set by the linker when validating resource limits,
while info->textures_used is gathered after NIR optimizations, which may
have eliminated some unused surfaces.

This may let us skip some work.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoi965: Drop unnecessary 'and' with prog->SamplerUnits
Kenneth Graunke [Mon, 11 Feb 2019 03:50:37 +0000 (19:50 -0800)]
i965: Drop unnecessary 'and' with prog->SamplerUnits

textures_used_by_txf is a subset of textures_used which is a subset
of prog->SamplerUnits.  This should do nothing.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agonir: Gather texture bitmasks in gl_nir_lower_samplers_as_deref.
Kenneth Graunke [Sun, 13 Jan 2019 18:39:41 +0000 (10:39 -0800)]
nir: Gather texture bitmasks in gl_nir_lower_samplers_as_deref.

Eric and I would like a bitmask of which samplers are used, similar to
prog->SamplersUsed, but available in NIR.  The linker uses SamplersUsed
for resource limit checking, but later optimizations may eliminate more
samplers.  So instead of propagating it through, we gather a new one.
While there, we also gather the existing textures_used_by_txf bitmask.

Gathering these bitfields in nir_shader_gather_info is awkward at best.
The main reason is that it introduces an ordering dependency between the
two passes.  If gathering runs before lower_samplers_as_deref, it can't
look at var->data.binding.  If the driver doesn't use the full lowering
to texture_index/texture_array_size (like radeonsi), then the gathering
can't use those fields.  Gathering might be run early /and/ late, first
to get varying info, and later to update it after variant lowering.  At
this point, should gathering work on pre-lowered or post-lowered code?
Pre-lowered is also harder due to the presence of structure types.

Just doing the gathering when we do the lowering alleviates these
ordering problems.  This fixes ordering issues in i965 and makes the
txf info gathering work for radeonsi (though they don't use it).

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agonir: Use sampler derefs in drawpixels and bitmap lowering.
Kenneth Graunke [Wed, 6 Feb 2019 07:24:51 +0000 (23:24 -0800)]
nir: Use sampler derefs in drawpixels and bitmap lowering.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoprogram: Make prog_to_nir create texture/sampler derefs.
Kenneth Graunke [Wed, 6 Feb 2019 03:02:44 +0000 (19:02 -0800)]
program: Make prog_to_nir create texture/sampler derefs.

Until now, prog_to_nir has been setting texture_index and sampler_index
directly.  This is different than GLSL shaders, which create variable
dereferences and rely on lowering passes to reach this final form.

radeonsi uses variable dereferences for samplers rather than
texture_index and sampler_index, so it doesn't even make sense to set
them there.  By moving to derefs, we ensure that both GLSL and ARB
programs produce the same final form that the driver desires.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agost/nir: Use sampler derefs in built-in shaders.
Kenneth Graunke [Wed, 6 Feb 2019 03:24:16 +0000 (19:24 -0800)]
st/nir: Use sampler derefs in built-in shaders.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agost/nir: Lower sampler derefs for builtin shaders.
Kenneth Graunke [Wed, 6 Feb 2019 08:06:33 +0000 (00:06 -0800)]
st/nir: Lower sampler derefs for builtin shaders.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agost/nir: Pull sampler lowering into a helper function.
Kenneth Graunke [Wed, 6 Feb 2019 08:03:49 +0000 (00:03 -0800)]
st/nir: Pull sampler lowering into a helper function.

This will make it easier to reuse across GLSL / ARB / built-ins.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoi965: Call nir_lower_samplers for ARB programs.
Kenneth Graunke [Wed, 6 Feb 2019 03:15:46 +0000 (19:15 -0800)]
i965: Call nir_lower_samplers for ARB programs.

An upcoming patch will start building derefs in prog_to_nir, at which
point we'll need to lower them to indexes.

This gets both GLSL and non-GLSL shaders using the same paths.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglsl: Don't look at sampler uniform storage for internal vars
Kenneth Graunke [Wed, 6 Feb 2019 10:05:01 +0000 (02:05 -0800)]
glsl: Don't look at sampler uniform storage for internal vars

Passes like nir_lower_drawpixels add additional sampler variables,
and set an explicit binding which never changes.  These extra samplers
don't have proper uniform storage associated with them, and there is no
way to update bindings via the API.  So, for any 'hidden' variables,
just trust that there's an explicit binding set.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglsl: Allow gl_nir_lower_samplers*() without a gl_shader_program
Kenneth Graunke [Wed, 6 Feb 2019 03:08:04 +0000 (19:08 -0800)]
glsl: Allow gl_nir_lower_samplers*() without a gl_shader_program

I would like to be able to run gl_nir_lower_samplers() to turn texture
and sampler variable dereferences into indexes and offsets, even for
ARB programs, and built-in shaders.  This would make sampler handling
more consistent across the various types of shaders.

For GLSL programs, the gl_nir_lower_samplers_as_deref() pass looks up
the variable bindings in the shader program's uniform storage.  But
ARB programs and built-in shaders don't have a gl_shader_program, and
uniform storage doesn't exist.  In this case, we simply skip that
lookup, and trust var->data.binding to be set correctly by whoever
created the shader.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agost/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048
Kenneth Graunke [Mon, 11 Feb 2019 06:49:20 +0000 (22:49 -0800)]
st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048

Piglit's vp-max-array test creates a vertex program containing a uniform
array sized to the value of GL_MAX_NATIVE_PROGRAM_PARAMETERS_ARB.  Mesa
will then add additional state-var parameters for things like the MVP
matrix.

radeonsi currently exposes a value of 4096, derived from constant buffer
upload size.  This means the array will have 4096 elements, and the
extra MVP state-vars would get a prog_src_register::Index of over 4096.

Unfortunately, prog_src_register::Index is a signed 13-bit integer, so
values beyond 4096 end up turning into negative numbers.  Negative
source indexes are only valid for relative addressing, so this ends up
generating illegal IR.

In prog_to_nir, this would cause an out of bounds array access.
st_mesa_to_tgsi checks for a negative value, assumes it's bogus,
and remaps it to parameter 0 in order to get something in-range.
This isn't right - instead of reading the MVP matrix, it would read
the first element of the vertex program's large array.  But the test
only checks that the program compiles, so we never noticed that it
was broken.

This patch limits the size of the program limits, with the understanding
that we may need to generate additional state-vars internally.  i965 has
exposed 1024 for this limit for years, so I don't expect lowering it to
2048 will cause any practical problems for radeonsi or other drivers.

Fixes vp-max-array with prog_to_nir.c.

Cc: "19.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agointel/dump_gpu: Disambiguate between BOs from different GEM handle spaces.
Francisco Jerez [Fri, 18 Jan 2019 20:51:57 +0000 (12:51 -0800)]
intel/dump_gpu: Disambiguate between BOs from different GEM handle spaces.

This fixes a rather astonishing problem that came up while debugging
an issue in the Vulkan CTS.  Apparently the Vulkan CTS framework has
the tendency to create multiple VkDevices, each one with a separate
DRM device FD and therefore a disjoint GEM buffer object handle space.
Because the intel_dump_gpu tool wasn't making any distinction between
buffers from the different handle spaces, it was confusing the
instruction state pools from both devices, which happened to have the
exact same GEM handle and PPGTT virtual address, but completely
different shader contents.  This was causing the simulator to believe
that the vertex pipeline was executing a fragment shader, which didn't
end up well.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agofreedreno/a6xx: Fall back to masked RGBA blits for depth/stencil
Kristian H. Kristensen [Fri, 8 Feb 2019 23:07:22 +0000 (15:07 -0800)]
freedreno/a6xx: Fall back to masked RGBA blits for depth/stencil

The blitter doesn't seem to have a write mask, so for depth only and
stencil only blits to Z24S8 we cast the Z24S8 buffer to an RGBA UNORM8
buffer and fall back to pipeline blits with corresponding write mask.

Fixes

  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only
  dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_depth
  dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_depth
  dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_depth
  dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_depth
  dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
  dEQP-GLES3.functional.fbo.msaa.4_samples.stencil_index8

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Add format argument to fd6_tex_swiz()
Kristian H. Kristensen [Sat, 9 Feb 2019 00:27:25 +0000 (16:27 -0800)]
freedreno/a6xx: Add format argument to fd6_tex_swiz()

We need to allow overriding the format with that of the image or
sampler view, so we can't take it from the resource in fd6_tex_swiz().

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Support y-inverted blits
Kristian H. Kristensen [Thu, 7 Feb 2019 23:35:07 +0000 (15:35 -0800)]
freedreno/a6xx: Support y-inverted blits

The src coordinates are s24.8. For an inverted blit that ends at y=0
we need to program -1 for sy2, so we need to handle negative values
correctly.

Fixes

  dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_y
  dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_dst_y
  dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_y
  dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_color
  dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_color

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Support some depth/stencil blits on blitter
Kristian H. Kristensen [Sat, 2 Feb 2019 01:15:45 +0000 (17:15 -0800)]
freedreno/a6xx: Support some depth/stencil blits on blitter

We can rewrite almost all depth stencil blits to various red-only
blits.  The exception is depth-only or stencil-only blits into z24s8
combined depth stencil buffer. We can fall back for depth-only, but
stencil-only remains broken.

Fixes

  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_basic
  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_scale
  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_basic
  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_scale
  dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Move blit check so as to restore comment
Kristian H. Kristensen [Fri, 1 Feb 2019 23:28:00 +0000 (15:28 -0800)]
freedreno/a6xx: Move blit check so as to restore comment

The explanation for the compressed format check is broken across two
comments:

/* We can blit if both or neither formats are compressed formats... */
/* ... but only if they're the same compression format. */

but the ok_format() checks were inserted between, breaking up the flow
of the sentence.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno: Don't tell the blitter what it can't do
Kristian H. Kristensen [Fri, 1 Feb 2019 23:20:05 +0000 (15:20 -0800)]
freedreno: Don't tell the blitter what it can't do

Call ctx->blit() and let it reject blits it can't do instead of giving
up on stencil blits and blits u_blitter can't do.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno: Consolidate u_blitter functions in freedreno_blitter.c
Kristian H. Kristensen [Fri, 1 Feb 2019 22:44:17 +0000 (14:44 -0800)]
freedreno: Consolidate u_blitter functions in freedreno_blitter.c

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Combine emit_blit and fd6_blit
Kristian H. Kristensen [Fri, 1 Feb 2019 22:01:15 +0000 (14:01 -0800)]
freedreno/a6xx: Combine emit_blit and fd6_blit

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Use the right resource for separate stencil stride
Kristian H. Kristensen [Thu, 31 Jan 2019 23:00:34 +0000 (15:00 -0800)]
freedreno/a6xx: Use the right resource for separate stencil stride

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno: Log number of draw for sysmem passes
Kristian H. Kristensen [Thu, 24 Jan 2019 19:38:51 +0000 (11:38 -0800)]
freedreno: Log number of draw for sysmem passes

Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
5 years agofreedreno/a6xx: Drop render condition check in blitter
Kristian H. Kristensen [Thu, 7 Feb 2019 19:40:29 +0000 (11:40 -0800)]
freedreno/a6xx: Drop render condition check in blitter

We already check earlier in the call chain in fd_blit().
glBlitFramebuffer always sets render_condition_enable and thus we
would never try the blitter path for that.

Now that we get all of dEQP-GLES3.functional.fbo.blit.conversion.*
down this path, it turs out that the

  fail_if(info->mask != util_format_get_mask(info->src.format));
  fail_if(info->mask != util_format_get_mask(info->dst.format));

conditions weren't accurate.  util_format_get_mask() returns
PIPE_MASK_RGBA for any format with any color channels, while
info->mask is the exact set of channels to blit.  So we reject things
we could blit - for example, PIPE_FORMAT_R16G16_FLOAT where info->mask
is RG while util_format_get_mask() returns RGBA - and accept things we
can't.  It turns out that the blitter is happy to blit different
number of channels, but fails to blit formats with different numerical
formats and srgb formats.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: regen headers
Kristian H. Kristensen [Mon, 11 Feb 2019 18:31:18 +0000 (10:31 -0800)]
freedreno/a6xx: regen headers

Update for a6xx.xml.h to incorporate a few new bits and changes to
blit src rect coordinate types.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agost/va/vp9: set max reference as default of VP9 reference number
Leo Liu [Fri, 8 Feb 2019 14:48:23 +0000 (09:48 -0500)]
st/va/vp9: set max reference as default of VP9 reference number

If there is no information about number of render targets

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>