mem-cache: Make StridePrefetcher use Replacement Policies

Previously StridePrefetcher was only able to use random
replacement policy. This change allows all replacement
policies to be applied to the pc table.

Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14360
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add invalidation function to StrideEntry

Add invalidation function to StrideEntry so that every
entry can be invalidated appropriately.

Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14359
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make PCTable context independent

Move the unordered_map outside of the PCTable, as it
belongs to the StridePrefetcher. By doing so we are
moving towards a table that ressembles the ones of
the Tags classes.

Some functions have been moved from the prefetcher to
the PCTable, as they didn't belong there. As such, they
have been renamed to remove the unnecessary prefix.

Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14358
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Vectorize StridePrefetcher's entries.

Turn StridePrefetcher::PCTable::entries into a vector of vectors.

Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24
Reviewed-on: https://gem5-review.googlesource.com/c/14357
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Return entry in StridePrefetcher::pcTableHit()

Return a pointer to the entry instead of returning a
boolean and passing a pointer reference. As a side
effect, change the name of the function to be more
descriptive of the functionality.

Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14356
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Cleanup prefetchers

Prefetcher code had extra variables, dependencies
that could be removed, code duplication, and missing
overrides.

Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

scons: add --gold-linker to link with the gold linker

This option can significantly speedup link time on Linux systems, which is
the main bottleneck to rebuild after small changes.

Change-Id: I3b0bdd61f7dcef0d73629c8ee2ee98091953fec3
Reviewed-on: https://gem5-review.googlesource.com/c/14075
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal

The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)

Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Remove Cache dependency from Tags

Tags do not need to be aware of caches.

Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move access latency calculation to Cache

Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.

By moving the calculation to the Cache we can use the write/
read information, reduce latency variables duplication and
remove Cache dependency from Tags.

The tag lookup latency is still calculated by the Tags.

Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Print register name when warning on AT instructions

With this patch we don't print anymore the enum value when warning
on any AT instruction usage, but we print the sys reg name instead

Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14316
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: implement a probe-based interface

The HW Prefetcher of a cache can now listen events
from their associated CPUs and from its own cache.

Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3
Reviewed-on: https://gem5-review.googlesource.com/c/14155
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim: Move BitUnion overloading to show/parseParams

This patch is moving template overloading for BitUnions into the
showParam, parseParams functions. Henceforth BitUnion types will use the
common param wrapper.
This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions.

Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13636
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Move paramIn/Out definition to header file

This patch is moving the definitions of paramIn/Out templates to
the header file. In this way we gain:

1) We don't have to do explicit instantiation anymore for user defined
types. This spares us from including data type header files into
serialize.cc

2) We can overload show/parseParam for BitUnions or any other type
that requires special handling when serializing. Just by overloading
the two templates we get all the containers' (list, vector, array..)
serialization for free

2) gtest: With the idea of adding unit tests for Serializable objects,
we can avoid importing serialize.cc and just redefine Serializable
methods in the test source, implementing a Serializable stub

Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13635
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fixed PC shifting on LTAGE branch predictor

The PC needs to be shifted according to the instShiftAmt parameter

Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14035
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Align how we handle requests in atomic with timing

Requests, for which a cache has already committed to respond do not
perform any lookups. Previously in atomic mode the packet would pay
the lookup latency while in timing it wouldn't. This patch aligns
recvAtomic with recvTimingReq and removes the lookup latency from the
the handling of such requests.

Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14175
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

systemc: Push python headers on top of sources

Some build failures has been seen after USE_SYSTEMC being True by
default and that has been caused by double definition of _XOPEN_SOURCE
and _POSIX_C_SOURCE in some python versions (like 2.7.5, 2.7.13) and
/usr/include/features.h (used by gcc)

Python definition should preceed features.h one, since the latter will
manually #undef them before #define them.

Change-Id: I774711aaf8145df9ad7677a393a60cf3662d6816
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14095
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stop using python to set/manage the global time resolution.

Now that that's managed in c++, we can do that directly without having
to depend on the python code being available, the code which lets us
call from c++ to python, or for the embedded python interpretter to
have started running and have loaded the appropriate modules.

Change-Id: Ied110d8f22181095f8c0c645636a9bd67964263e
Reviewed-on: https://gem5-review.googlesource.com/c/14056
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim: Push the global frequency management code into C++.

That makes it available when python is left out, and makes it available
to c++ code without having to call back into python.

Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2
Reviewed-on: https://gem5-review.googlesource.com/c/14055
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Revamp ruby mem test to align with MemTest

The test script was broken as it was based on an older version of
MemTest, this changes revamps the creation of MemTest and removes
parameters that are not any longer valid.

Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13596
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

systemc: Get rid of a duplicated base class initializer for sc_fifo.

These were consistent, but redundant and incorrect none the less.

Change-Id: I9ff7fdb9c83f9a8af6fbe969c6c73b9aab8967ad
Reviewed-on: https://gem5-review.googlesource.com/c/14136
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add a missing "const" on one of the sc_event operators.

Change-Id: I073ccb0f2c6d1bfebadb95869d6acf7f4ce565af
Reviewed-on: https://gem5-review.googlesource.com/c/14135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Only build python utility code if python is enabled.

Change-Id: I58054ddd0d5ef0dbee18028c4218e7418347f959
Reviewed-on: https://gem5-review.googlesource.com/c/13979
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

systemc: Separate and conditionalize exposing sc_main to python.

Change-Id: Ib39dd79c607b277ba94f90dee41c09c1b3b66481
Reviewed-on: https://gem5-review.googlesource.com/c/13978
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

systemc: Seperate out the sc_main fiber and its bookkeeping.

By pulling out the sc_main fiber (scMainFiber), we can make it
available to different entities in the simulator and avoid having to
have parallel bookkeeping.

Also this will make it possible to hook into sc_main without putting
the code in sc_main.cc.

Change-Id: I7689441424238e9b2e4d2b48e945dea35fd8cc5d
Reviewed-on: https://gem5-review.googlesource.com/c/13977
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stop using python init to set up predefined message ids.

We can now be sure register_id will work even mid static initializers,
so we don't have to use python initialization as a hook to install
these predefined message ids.

Change-Id: I2e4d0c678ddda0a9ce5b114bdf1710f36e955f23
Reviewed-on: https://gem5-review.googlesource.com/c/13976
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

systemc: Wrap some report maps in functions.

By declaring the map as a static variable in that function and then
returning it, we can guarantee that it's initialized relative to other
static initializers so that we don't try to use a data structure that
isn't constructed yet. This will let us get rid of the dependence on
python for setting up that mapping.

Change-Id: I031ce2039de8f5f79fbb9d76cf1363f15207b64b
Reviewed-on: https://gem5-review.googlesource.com/c/13975
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

configs: Add missing path to ruby imports

Add missing addToPath to ruby files, so that import
modules from previous folder are visible.

Change-Id: I912d78a2f709974f72fe768e73abac1617126f46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13995
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Use Packet writing functions instead of memcpy

Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.

Change-Id: Iae3fba1351330916ee1d4103809c71e151b1639e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13915
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Update workflow requirements in CONTRIBUTING.md

Change-Id: I5394ef58930fccea343414964c1fc3e18829d609
Reviewed-on: https://gem5-review.googlesource.com/c/13755
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Deprecate usage of legacy bootloader patching

This patch is implicitly deprecating the usage of bootloader patching,
which is injecting instructions from gem5 into the bootloader
binary. This was probably meant to provide a dynamic bootloader
entry point.
This is not needed in ARMv8.0, since we can simply update the
ArmSystem::resetAddress with the bootloader entry point.

Change-Id: I0c469873b8d69f7b49a7383e0754468bc1f2bd72
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14001
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32

ARMv8 differs from ARMv7 with the presence of RVBAR register, which
contains the implementation defined reset address when EL3 is not
implemented.
The entry 0x0 in the AArch32 vector table, once used for the Reset
Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION
DEFINED. An implementation might still use this vector table entry to
hold the Reset vector, but having a Reset address != than the general
vector table (for any other exception) is allowed.

At the moment any Reset exception is still using 0 as a vector table
base address. This patch is extending the ArmSystem::resetAddr64 to
ArmSystem::resetAddr so that it can be used for initializing
MVBAR/RVBAR. In order to do so, we are providing a specialized behavior
for the Reset exception when evaluating the vector base address.

Change-Id: I051a730dc089e194db3b107bbed19251c661f87e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14000
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Implement AArch32 RVBAR

RVBAR has been added to the system register list since ARMv8.0-A.  It is
implemented only if the highest Exception Level is different (minor)
than EL3.  If that's not the case, MVBAR is used. Since the two
registers are mutually exclusive (depending on the presence of EL3),
they share the same coprocessor numbers:

p15, 0, c12, c0, 1

Rather than introducing a new register alias, we overload MVBAR so that
it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is
changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR).

N.B MVBAR is RW, whereas RVBAR is RO

Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13999
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove SCTLR.VE bit

ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.

Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Refactor ISA::clear by adding a ISA::clear32 method

The patch is also moving some initialization code to be used
by AArch64 as well since the registers are mapped to AArch64 ones.

Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13997
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove MISCREG commented numbers

Having an enum number might be useful in case we wanted to know how many
miscregs we have, but on the other hand it makes it tedious to update
the register list, since every commented number must be bumped.  This
patch is removing the comments holding the MISCREG numbers

Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13996
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Fix some paths in the tlm SCons(script|struct).

The code in util/systemc was moved into a subdirectory recently. The
scons support here referred to it, and needed to be updated.

Change-Id: Ib457d9bdafb2bba5058e6ecf99b9d33b3072c5b3
Reviewed-on: https://gem5-review.googlesource.com/c/13955
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mips: Change the integer and fp register widths to be 64 bits.

This makes them more consistent with the other architectures, helping
to facilitate having a single, unified type across ISAs in the future.

Change-Id: I65efb10e39d453281b8429eeedbb46fa6b023a2b
Reviewed-on: https://gem5-review.googlesource.com/c/13620
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mips: Clean up type overrides for operands.

For operands which default to uw (uint32_t), there's no reason to
explicitly specify that all over the place. Also, when assigning to a
32 bit value which is supposed to be the full width of the resulting
register, there's no reason to override the value to be signed. If the
value is expanded into a larger value, then extra bits may get set
unintentionally through sign extension. Even if an instruction
produces a value which should be interpreted as signed, it will still
only produce a value of a certain predefined width, even if that answer
ends up stored in a larger variable.

Change-Id: I048d68c5dd08a1d40e8117ae9d36d70e05ec21c8
Reviewed-on: https://gem5-review.googlesource.com/c/13618
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mips: Explicitly truncate the syscall return value down to 32 bits.

The IntReg type is 32 bits, and using it to cast the syscall return
value is appropriate, but we're attempting to get rid of the ISA
specific register types.

Change-Id: I42496dd2cc086a6b718e1ce087fef81bb897d02f
Reviewed-on: https://gem5-review.googlesource.com/c/13619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

null: Claim to use 64 bit floating point registers.

The NULL ISA doesn't actually have registers, so this setting doesn't
matter. By making it 64 bits the ISA is more compatible with the other
ISAs.

Change-Id: I2c9b6d9a6f612719b8b00eb9dbed55fa2159e9b5
Reviewed-on: https://gem5-review.googlesource.com/c/13617
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

These types aren't used by the ISA itself since they're defined to be
particular primitive types in the ISA description. This just affects
code outside of the ISA which work with those types of registers.

Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747
Reviewed-on: https://gem5-review.googlesource.com/c/13616
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Add standard types for floating and nonfloating point register values.

These should be used instead of the ISA specific ones, and should be
at least as large as the largest primitive register type in all the
ISAs.

Change-Id: Iaac104eef74eabcdd87787b1cdf8bea22d449eda
Reviewed-on: https://gem5-review.googlesource.com/c/13615
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Enable systemc support by default.

Change-Id: I9375518a54e14413a499d065f5bc5e1031834c81
Reviewed-on: https://gem5-review.googlesource.com/c/13535
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

systemc: Explicitly keep the sc_port bind alongside sc_in's version.

The sc_in bind function was hiding the one from sc_port by changing
the const-ness of its parameter. This change explicitly exposes the
underlying sc_port version, and keeps it alongside the new sc_in
version.

This seems mildly dangerous and undesirable because now there are two
very similar functions which would both need to be overridden in order
to get new behavior, but I don't think it's any more dangerous and
undesirable than as (perhaps unintentionally) specified in the
standard.

Change-Id: Ib42a1f8e70bc97abeeeb8d614e71c4019b3a2323
Reviewed-on: https://gem5-review.googlesource.com/c/13880
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Change how SC_BIND_PROXY_NIL is initialized.

The previous implementation dereferenced a null pointer to create a
reference which would then have its address taken in the sc_bind_proxy
constructor. clang says that that uses undefined behavior, so this
change adds a default constructor which initializes the two contained
pointers to null explicitly.

We have to hope systemc code doesn't play around with sc_bind_proxy too
much and doesn't accidentally use this constructor unintentionally, but
it seems like the least bad possible solution which makes clang happy.

Change-Id: Ic59603495fe7a406586a18ce44de979f84089bcd
Reviewed-on: https://gem5-review.googlesource.com/c/13879
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Get rid of implementations for some disabled sc_vector methods.

These don't need to exist, and the specifics of their stub
implementations were upsetting clang.

Change-Id: Ib38a39c5cfbc2e1647cfb6ed14c660e10df2b1c3
Reviewed-on: https://gem5-review.googlesource.com/c/13878
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Move a function after the class it uses internally.

The class was defined, but only later in the file. By putting the
function definition later, clang stops reporting an error.

Change-Id: Id4dd1ec3f3a06f4d1dc10ef4ff8c545d98a6ae12
Reviewed-on: https://gem5-review.googlesource.com/c/13877
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Get rid of an unused private member in sc_clock.

It's not useful, and having it makes clang upset.

Change-Id: I51366fd18a287e186c88f08af5c6ba8692779003
Reviewed-on: https://gem5-review.googlesource.com/c/13876
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Rename the tag class init function to tagsInit.

Since the tag classes are subclasses of SimObject, they inherit an
init function which does generic initialization at simulation startup
and which doesn't take any parameters. A new function was added which
does take a parameter, and which is just for doing tag specific
initialization as triggered by the base cache. These two names clashed,
and clang complained that the tag local name was hiding the SimObject
name (which it was).

Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0
Reviewed-on: https://gem5-review.googlesource.com/c/13875
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use Packet writing functions instead of memcpy

Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.

This also fixes a bug in MemCheckerMonitor, which was using
the incorrect type for the packet pointer.

Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13695
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix double block invalidation

Block was being invalidated twice when not a tempBlock.
Make explicit that the else case is only to be applied
when handling the tempBlock, as otherwise the Tags
should be taking care of the invalidation.

Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch, arm: Return s1Req upon fault in s2Lookup

When a s2Lookup object is created, a new request is created, based
upon the original, stage 1 request sent out by the CPU. When a fault
occurs during the second stage of translation, this new request is
returned. This can lead to issues with the O3 CPU. The O3 fetch stage
will not acknowledge the fault as it is a different request than the
one it sent out and does not contain a contextID. This commit
rectifies this.

Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13782
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, arm: Effect of AT instructions on descriptor handling

Some address translation instructions will stop translation after
the 1st stage and intercept the IPA, even in the presence of
stage 2 (eg AT S1E1).  However, in the case of a TLB miss, the
table descriptors still need to be translated from IPA to PA to
avoid fetching the wrong addresses.  This commit splits whether
IPA->PA translation is required for the VA and/or for the table
descriptors.

Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Add some examples for using systemc code within gem5.

These examples have comments inside them that explain what they do.
There's also a README file which explains how to use the examples
generally, and at a high level what each one does.

Change-Id: I223963dc1c190289986b2ee5705910dbcad4a4c9
Reviewed-on: https://gem5-review.googlesource.com/c/13376
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Move the existing systemc example into a subdirectory.

This example is for how to embed gem5 within systemc and make it use
the systemc event queue. This used to be the only method of using
gem5 and systemc together, but now that there are other options, it's
ambiguous to have it as the only thing in the util/systemc directory.

This change moves it into a gem5_within_systemc subdirectory which
clearly shows what type of integration that example corresponds with.

Change-Id: I426d68ccb618397d820bef492cbb1ff8ef4a979b
Reviewed-on: https://gem5-review.googlesource.com/c/13375
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

syscall_emul: fix openat when directory does not end in "/"

Before this commit, the following code:

    dir_fd = open(".", O_DIRECTORY);
    file_fd = openat(dir_fd, "ble", O_CREAT, S_IRUSR | S_IWUSR);

would create a file called ".ble" in the current working directory,
instead of the correct "ble".

Change-Id: I1525a088d49744e29b760387afabef9f1ac98646
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13005
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

syscall_emul: implement arm openat

This is especially important because the Ubuntu 18.04 packaged
arm-linux-gnueabihf-gcc uses the system call on the program initialization,
which leads all programs to fail with:

fatal: syscall openat (#322) unimplemented.

Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13004
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: FIXUP for the add PRFM PST instruction commit

Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd
Reviewed-on: https://gem5-review.googlesource.com/c/13815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-ruby: Fix MOESI_CMP_directory in ports order

To avoid deadlocks ruby objects typically prioritize the handling of
responses to all other events. The order in which in_port statements
are written determine the order in which they are handled. This patch
fixes the order of in_order statements for the L2 cache in the
MOESI_CMP_directory.

Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13595
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: We add PRFM PST instruction for arm

Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.

Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp>
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}

According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or
15) is implementation defined; this makes it trappable by having
HCR_EL2.TIDCP = 1.

Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13780
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.

Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Refactor AArch64 MSR/MRS trapping

This patch refactors AArch64 MSR/MRS trapping, by moving the trapping
helpers in arch/arm/utility and in the isa code into a MiscRegOp64
class.

This class is the Base class for a generic AArch64 instruction which is
making use of system registers (MiscReg), like MSR,MRS,SYS.  The common
denominator or those instruction is the chance that the system register
access is trapped to an upper Exception level. MiscRegOp64 is providing
that feature.

What do we gain? Other "pseudo" instructions, like access to
implementation defined registers can inherit from this class to make use
of the trapping functionalities even if there is no data movement
between GPRs and system register.

Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13778
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Trap to EL2 only if not in Secure State

MRS/MSR Instructions should trap to EL2 only if we are in non-Secure
state since at the current implementation (Armv8.0) there is no Secure
EL2.

Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13777
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix HVC trapping beahviour

This patch is fixing HVC trapping behaviour, reusing the pseudocode
implementation provided in the arm arm.

Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13776
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1

According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the
CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR,
are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.

Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13775
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Convert AddrRangeMap unit test to a GTest

Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

tests: Convert CircleBuf unit test to a GTest

Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13735
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base

Move evictBlock(CacheBlk*, PacketList&) to base cache,
as it is both sub-classes implementations are equal.

Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13656
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

config: add --param to fs.py, se.py and fs_bigLITTLE.py

The option allows to set SimObject params from the CLI.

The existing config scripts have a large number of options that simply set
a single SimObject parameter, and many still are not exposed.

This commit allows users to pass arbitrary parameters from the command
line to prevent the need for this kind of trivial option.

Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Reviewed-on: https://gem5-review.googlesource.com/c/12985
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Add utility function to override config parameters

Add a utility method, SimObject.apply_config that can be used to
implement SimObject param overrides from the command line. This
function provides safe and convenient semantics for CLI assignment:

* The override expression is evaluated in a restricted environment. The
  only global variables are the child objects and params from the root
  object.

* Only params can be overridden. For example, calling methods or setting
  attributes on SimObjects isn't possible.

* Vectors use non-standard list semantics which enable something similar
  to glob expansion on the shell. For example, setting:

      root.system.cpu[0:2].numThreads = 2

  will override numThreads for cpu 0 and 1 and:

      root.system.cpus[0,2].numThreads = 2

  sets it for cpus 0 and 2.

The intention is that the helper method is called to override default
values before calling m5.instantiate.

Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799
Reviewed-on: https://gem5-review.googlesource.com/c/12984
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: treat aarch64 hints as NOPs instead of panic

Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13476
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: update hint instruction decoding to match ARMv8.5

This fixes:

- unallocated hints that have since been allocated
- unallocated and unimplemented hint instructions being treated as
  Unknown instead of the correct NOP
- missing encoding for DBG on A32

Unallocated and unimplemented hints give a warning if executed.

The most important fix was for the CSDB Spectre mitigation
instruction, which was added recently and previously unallocated and
treated as Unknown.

The Linux kernel v4.18 ARMv7 uses CSDB it and boot would
fail with "undefined instruction" since Linux commit
1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613

Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13475
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Fix unused variable warning in FALRU:invalidate()

Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13600
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem: Add write coalescing and write-no-allocate to the caches

Enable the cache to detect contiguous writes and hold on to the MSHR
long enough to allow the entire line to be written. If the whole line
is written, the MSHR will be sent out as an invalidation requests, as
it is part of a whole-line write, i.e. no-fetch-on-write.

The cache is also able to switch to a write-no-allocate policy on the
actual completion of the writes, and instead use the tempBlock and
turn the write operation into a writeback.

These policies are all well-known, and described in works such as
Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993.

Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae
Reviewed-on: https://gem5-review.googlesource.com/c/12907
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Delay servicing an MSHR after its allocation

An MSHR is allocated and the computed latency determines when the MSHR
will be ready and can be serviced by the cache. This patch adds a
function that allows changing the time that an MSHR is ready and
adjusts the queue such that other MSHRs can be serviced first if they
are ready.

Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff
Reviewed-on: https://gem5-review.googlesource.com/c/12906
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Determine if an MSHR does a whole-line write

This patch adds support for determining whether the targets in an MSHR
are 1) only writes and 2) whether these writes are effectively a
whole-line write. This patch adds the necessary functions in the MSHR
to allow for write coalescing in the cache.

Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4
Reviewed-on: https://gem5-review.googlesource.com/c/12904
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Mark the guest endianness packet accessors as deprecated.

Change-Id: Iebefeb5b1ce905f2b45b30b7656d6a01d0724584
Reviewed-on: https://gem5-review.googlesource.com/c/13575
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

null: Stop specifying an endianness in isa_traits.hh.

The NULL ISA doesn't really have an endianness. Now that the packet
accessors which consumed that endianness are gone, we can get rid of
that setting as well.

Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4
Reviewed-on: https://gem5-review.googlesource.com/c/13466
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Explicitly specify the endianness in the abstract memory.

The accessors are used for debugging output. If we're using an ISA
where there's an endianness, we use that explicitly, falling back to a
binary dump if the size isn't supported. If not, then we just dump the
data without interpretation regardless of size.

Change-Id: Ib050c4c876ee41f17cfd14ad657150bf6ab1de39
Reviewed-on: https://gem5-review.googlesource.com/c/13464
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

gpu-compute: Explicitly use little endian packet accessors.

The gpu ISA doesn't have a well defined endianness, but it really
should. It seems that the GPU is only used with x86, and in that
context it would be little endian.

Change-Id: I1620906564a77f44553fbf6d788866e017b6054b
Reviewed-on: https://gem5-review.googlesource.com/c/13463
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch: Include some additional headers in arch/generic/mmapped_ipr.cc.

These had been included transitively before.

Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0
Reviewed-on: https://gem5-review.googlesource.com/c/13538
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Remove using namespace TheISA in uart8250.cc.

Nothing in that file is in the TheISA namespace, so there's no reason
to use using on it.

Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4
Reviewed-on: https://gem5-review.googlesource.com/c/13537
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Stop conditionally excluding code from pyobject.cc

Now that the Ether* classes are included in all builds, there's no
reason to conditionally compile code in pyobject.cc.

Change-Id: If94602af71774b1f090a3344a633207f4b37d308
Reviewed-on: https://gem5-review.googlesource.com/c/13470
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Build most of the networking devices in the NULL_ISA build.

The only part of these devices which are incompatible with other ISAs,
with the possible exception of endianness transformation, is that
the dist_iface implementation refers to ThreadContext methods and
that class is heavily tied to the guest ISA. Only those few lines are
excluded in a NULL_ISA build.

Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460
Reviewed-on: https://gem5-review.googlesource.com/c/13469
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Build the PCI device models even in NULL_ISA builds.

There are some minor ISA dependencies in the PCI device models,
specifically that they use the set<> accessors on the packet objects.
This actually compiles fine because the NULL ISA claims to be little
endian, but really these accessors should be changed to use little
endian all the time since that's what PCI is defined to use, not
the guest endianness.

The other types of accessors, specifically the ones that default to
what the guest wants, should be excluded when building NULL_ISA, and,
pending other dependencies, the NULL_ISA should no longer have an
endianness associated with it.

Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4
Reviewed-on: https://gem5-review.googlesource.com/c/13468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Get rid of the unused type AnyReg.

This type is defined for all the ISAs but isn't used by anything.

Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Don't panic when EOIR a non active PPI

GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.

Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Fix Gicv2 distributor group register

For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.

Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Get rid of leftovers from unimplemented warnings past.

These warnings were removed when the functionality they warned about
was implemented, but there were some leftovers like unnecessary
includes and some helper functions which hid gem5 specific headers
from the ext directory.

Change-Id: Ic886ac0f1264687524e3a7b7eaab8836f318a5a2
Reviewed-on: https://gem5-review.googlesource.com/c/13398
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Implement Object::simcontext().

Implement it as a nonstandard alias for the also non-standard
sc_get_curr_simcontext.

Change-Id: Ic9a51efa93f687e4b57d622247a5510136fab221
Reviewed-on: https://gem5-review.googlesource.com/c/13397
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stop filtering out warnings about unimplemented features.

These no longer cause any of the tests to break, so there's no reason
to filter them out.

Change-Id: I9c0b25fc42eb3060ac7d6d6a46ded130227c302d
Reviewed-on: https://gem5-review.googlesource.com/c/13396
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Warn about using deprecated sc_port constructors.

This gets rid of one of the last instances of a warning about
unimplemented functionality.

Change-Id: I3d8e50ea45554cba969118ce873ed3d2b041ec43
Reviewed-on: https://gem5-review.googlesource.com/c/13395
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add a python config class for sc_modules.

This class doesn't really add anything, but it provides a consistent
base class for sc_modules vs. generic sc_objects.

Change-Id: I3fbd4f6b5d1be0b5419f5cbd304aec61d404a341
Reviewed-on: https://gem5-review.googlesource.com/c/13355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Don't include the scheduler in an external header file.

The scheduler is an internal detail and shouldn't be exposed to the
headers in ext. It would transitively include more headers which are
not in ext, making it not self contained.

Change-Id: I8384cde9d19363953ffd0c91e7d8d27f8f79a570
Reviewed-on: https://gem5-review.googlesource.com/c/13336
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add an accessor for getting the current process.

This is to avoid having to expose the scheduler (which tracks the
current process) to header files which should be independent of gem5
and the underlying implementation.

Change-Id: I1b0810ab66c3ce52b5b94236d7df86da66a62472
Reviewed-on: https://gem5-review.googlesource.com/c/13335
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Don't re-schedule a process which is already scheduled.

Change-Id: I8e12713c49aad03d0bfb779883adcbfa8fd4b42e
Reviewed-on: https://gem5-review.googlesource.com/c/13334
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>