Eddie Hung [Sat, 23 Nov 2019 18:01:09 +0000 (10:01 -0800)]
More sane naming of submod
Eddie Hung [Sat, 23 Nov 2019 17:52:17 +0000 (09:52 -0800)]
Add -set_attr option, -unpart to take attr name
Eddie Hung [Sat, 23 Nov 2019 07:29:10 +0000 (23:29 -0800)]
Do not use log_signal() for empty SigSpec to prevent "{ }"
Eddie Hung [Sat, 23 Nov 2019 07:16:15 +0000 (23:16 -0800)]
Call submod once, more meaningful submod names, ignore largest domain
Eddie Hung [Sat, 23 Nov 2019 01:25:53 +0000 (17:25 -0800)]
Move clkpart into passes/hierarchy
Eddie Hung [Sat, 23 Nov 2019 01:00:11 +0000 (17:00 -0800)]
Only action if there is more than one clock domain
Eddie Hung [Sat, 23 Nov 2019 00:58:08 +0000 (16:58 -0800)]
Replace TODO
Eddie Hung [Fri, 22 Nov 2019 23:41:34 +0000 (15:41 -0800)]
Brackets
Eddie Hung [Fri, 22 Nov 2019 23:41:23 +0000 (15:41 -0800)]
Entry in Makefile.inc
Eddie Hung [Fri, 22 Nov 2019 23:35:08 +0000 (15:35 -0800)]
Add to CHANGELOG
Eddie Hung [Fri, 22 Nov 2019 23:33:51 +0000 (15:33 -0800)]
New 'clkpart' to {,un}partition design according to clock/enable
Clifford Wolf [Fri, 22 Nov 2019 17:11:58 +0000 (18:11 +0100)]
Merge pull request #1517 from YosysHQ/clifford/optmem
Add "opt_mem" pass
Clifford Wolf [Fri, 22 Nov 2019 17:10:34 +0000 (18:10 +0100)]
Merge pull request #1515 from YosysHQ/clifford/svastuff
Add Verific/SVA support for "always" and "nexttime" properties
Clifford Wolf [Fri, 22 Nov 2019 15:58:49 +0000 (16:58 +0100)]
Add "opt_mem" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 15:11:56 +0000 (16:11 +0100)]
Add Verific support for SVA nexttime properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 15:00:07 +0000 (16:00 +0100)]
Improve handling of verific primitives in "verific -import -V" mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 14:52:21 +0000 (15:52 +0100)]
Add Verific SVA support for "always" properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 14:32:29 +0000 (15:32 +0100)]
Merge pull request #1511 from YosysHQ/dave/always
sv: Error checking for always_comb, always_latch and always_ff
Marcin Kościelnicki [Fri, 22 Nov 2019 11:15:33 +0000 (12:15 +0100)]
gowin: Remove show command from tests.
Marcin Kościelnicki [Fri, 22 Nov 2019 11:10:57 +0000 (12:10 +0100)]
gowin: Add missing .gitignore entries
David Shah [Fri, 22 Nov 2019 12:46:19 +0000 (12:46 +0000)]
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 21:06:28 +0000 (21:06 +0000)]
sv: Add tests for SV always types
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 20:46:41 +0000 (20:46 +0000)]
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 20:27:19 +0000 (20:27 +0000)]
sv: Correct parsing of always_comb, always_ff and always_latch
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Wed, 20 Nov 2019 12:49:27 +0000 (13:49 +0100)]
Merge pull request #1507 from YosysHQ/clifford/verificfixes
Some fixes in our Verific integration
Clifford Wolf [Wed, 20 Nov 2019 11:56:31 +0000 (12:56 +0100)]
Correctly treat empty modules as blackboxes in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Nov 2019 11:54:10 +0000 (12:54 +0100)]
Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 19 Nov 2019 16:29:27 +0000 (17:29 +0100)]
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Pepijn de Vos [Tue, 19 Nov 2019 14:53:44 +0000 (15:53 +0100)]
Remove dff init altogether
The hardware does not actually support it.
In reality it is always initialised to its reset value.
Marcin Kościelnicki [Mon, 18 Nov 2019 07:19:53 +0000 (08:19 +0100)]
Fix #1462, #1480.
Marcin Kościelnicki [Mon, 18 Nov 2019 02:47:56 +0000 (03:47 +0100)]
xilinx: Add simulation models for MULT18X18* and DSP48A*.
This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
Pepijn de Vos [Mon, 18 Nov 2019 13:25:46 +0000 (14:25 +0100)]
add help for nowidelut and abc9 options
Clifford Wolf [Mon, 18 Nov 2019 09:53:14 +0000 (10:53 +0100)]
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
Fix #1496.
whitequark [Mon, 18 Nov 2019 09:37:14 +0000 (09:37 +0000)]
Merge pull request #1494 from whitequark/write_verilog-extmem
write_verilog: add -extmem option, to write split memory init files
Marcin Kościelnicki [Mon, 18 Nov 2019 03:16:48 +0000 (04:16 +0100)]
Fix #1496.
whitequark [Fri, 15 Nov 2019 03:11:46 +0000 (03:11 +0000)]
write_verilog: add -extmem option, to write split memory init files.
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
Clifford Wolf [Sun, 17 Nov 2019 09:42:30 +0000 (10:42 +0100)]
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
Pepijn de Vos [Sat, 16 Nov 2019 11:43:17 +0000 (12:43 +0100)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
David Shah [Fri, 15 Nov 2019 21:03:11 +0000 (21:03 +0000)]
ecp5: Use new autoname pass for better cell/net names
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 14 Nov 2019 18:43:15 +0000 (18:43 +0000)]
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Thu, 14 Nov 2019 17:03:44 +0000 (18:03 +0100)]
Merge pull request #1490 from YosysHQ/clifford/autoname
Add "autoname" pass and use it in "synth_ice40"
Clifford Wolf [Thu, 14 Nov 2019 11:10:12 +0000 (12:10 +0100)]
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
Python Wrappers: Expose global variables and allow logging to python streams
Clifford Wolf [Thu, 14 Nov 2019 11:07:25 +0000 (12:07 +0100)]
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
ice40: Support for post-place-and-route timing simulations
Clifford Wolf [Thu, 14 Nov 2019 10:57:53 +0000 (11:57 +0100)]
Merge branch 'makaimann-label-bads-btor'
Clifford Wolf [Thu, 14 Nov 2019 10:57:38 +0000 (11:57 +0100)]
Use cell name for btor bad state props when it is a public name
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 14 Nov 2019 10:52:41 +0000 (11:52 +0100)]
Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor
Clifford Wolf [Wed, 13 Nov 2019 12:41:16 +0000 (13:41 +0100)]
Add "autoname" pass and use it in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Wed, 13 Nov 2019 11:57:17 +0000 (11:57 +0000)]
Merge pull request #1488 from whitequark/flowmap-fixes
flowmap: fix a few crashes
Clifford Wolf [Wed, 13 Nov 2019 11:34:27 +0000 (12:34 +0100)]
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
Bugfix in fsm_detect
Clifford Wolf [Tue, 12 Nov 2019 16:31:30 +0000 (17:31 +0100)]
Update fsm_detect bugfix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Nov 2019 13:26:02 +0000 (14:26 +0100)]
Bugfix in fsm_detect
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Nov 2019 09:24:12 +0000 (10:24 +0100)]
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
Makai Mann [Tue, 12 Nov 2019 00:40:51 +0000 (16:40 -0800)]
Add an info string symbol for bad states in btor backend
whitequark [Tue, 12 Nov 2019 00:15:43 +0000 (00:15 +0000)]
flowmap: when doing mincut, ensure source is always in X, not X̅.
Fixes #1475.
whitequark [Mon, 11 Nov 2019 23:13:00 +0000 (23:13 +0000)]
flowmap: don't break if that creates a k+2 (and larger) LUT either.
Fixes #1405.
Pepijn de Vos [Mon, 11 Nov 2019 16:51:26 +0000 (17:51 +0100)]
fix fsm test with proper clock enable polarity
Pepijn de Vos [Mon, 11 Nov 2019 16:08:40 +0000 (17:08 +0100)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Miodrag Milanovic [Mon, 11 Nov 2019 14:41:33 +0000 (15:41 +0100)]
Fixed tests
Clifford Wolf [Mon, 11 Nov 2019 14:07:29 +0000 (15:07 +0100)]
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 10 Nov 2019 10:00:38 +0000 (11:00 +0100)]
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
Add CodingReadme section on script passes
Clifford Wolf [Thu, 7 Nov 2019 12:30:03 +0000 (13:30 +0100)]
Add check for valid macro names in macro definitions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Pepijn de Vos [Wed, 6 Nov 2019 18:48:18 +0000 (19:48 +0100)]
fix wide luts
Marcin Kościelnicki [Fri, 1 Nov 2019 14:00:15 +0000 (14:00 +0000)]
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
Clifford Wolf [Mon, 4 Nov 2019 13:25:13 +0000 (14:25 +0100)]
Fix write_aiger bug added in
524af21
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 31 Oct 2019 09:46:20 +0000 (10:46 +0100)]
Add CodingReadme section on script passes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Pepijn de Vos [Wed, 30 Oct 2019 13:58:25 +0000 (14:58 +0100)]
don't cound exact luts in big muxes; futile and fragile
Pepijn de Vos [Mon, 28 Oct 2019 14:33:05 +0000 (15:33 +0100)]
add IOBUF
Pepijn de Vos [Mon, 28 Oct 2019 14:18:01 +0000 (15:18 +0100)]
add tristate buffer and test
Pepijn de Vos [Mon, 28 Oct 2019 13:40:12 +0000 (14:40 +0100)]
do not use wide luts in testcase
Pepijn de Vos [Mon, 28 Oct 2019 13:28:03 +0000 (14:28 +0100)]
actually run the gowin tests
Pepijn de Vos [Mon, 28 Oct 2019 12:10:12 +0000 (13:10 +0100)]
More formatting
Pepijn de Vos [Mon, 28 Oct 2019 12:01:20 +0000 (13:01 +0100)]
really really fix formatting maybe
Pepijn de Vos [Mon, 28 Oct 2019 11:57:12 +0000 (12:57 +0100)]
undo formatting fuckup
Pepijn de Vos [Mon, 28 Oct 2019 11:49:08 +0000 (12:49 +0100)]
add wide luts
Pepijn de Vos [Mon, 28 Oct 2019 09:33:27 +0000 (10:33 +0100)]
add 32-bit BRAM and byte-enables
Clifford Wolf [Sun, 27 Oct 2019 09:25:01 +0000 (10:25 +0100)]
Merge pull request #1393 from whitequark/write_verilog-avoid-init
write_verilog: do not print (*init*) attributes on regs
Pepijn de Vos [Thu, 24 Oct 2019 11:39:43 +0000 (13:39 +0200)]
ALU sim tweaks
Clifford Wolf [Thu, 24 Oct 2019 10:13:37 +0000 (12:13 +0200)]
Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Thu, 24 Oct 2019 07:14:20 +0000 (08:14 +0100)]
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
Add BRAM and URAM mapping for UltraScale[+]
Clifford Wolf [Thu, 24 Oct 2019 07:14:03 +0000 (09:14 +0200)]
Add "verific -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Wed, 23 Oct 2019 17:44:34 +0000 (18:44 +0100)]
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Sun, 20 Oct 2019 09:24:47 +0000 (10:24 +0100)]
ice40: Support for post-pnr timing simulation
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 18 Oct 2019 13:02:57 +0000 (14:02 +0100)]
xilinx: Add URAM288 mapping for xcup
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 18 Oct 2019 12:24:19 +0000 (13:24 +0100)]
xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Tue, 22 Oct 2019 22:04:34 +0000 (00:04 +0200)]
Bugfix in smtio vcd handling of $-identifiers
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Marcin Kościelnicki [Tue, 8 Oct 2019 17:00:30 +0000 (17:00 +0000)]
xilinx: Support multiplier mapping for all families.
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
Clifford Wolf [Tue, 22 Oct 2019 15:36:54 +0000 (17:36 +0200)]
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
Pepijn de Vos [Mon, 21 Oct 2019 14:25:15 +0000 (16:25 +0200)]
Add some tests
Copied from Efinix.
* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
Pepijn de Vos [Mon, 21 Oct 2019 14:08:13 +0000 (16:08 +0200)]
add a few more missing dff
Clifford Wolf [Mon, 21 Oct 2019 11:35:31 +0000 (13:35 +0200)]
Add "verilog_defines -list" and "verilog_defines -reset"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 21 Oct 2019 10:39:28 +0000 (12:39 +0200)]
Fix handling of "restrict" in Verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Pepijn de Vos [Mon, 21 Oct 2019 10:31:11 +0000 (12:31 +0200)]
add negedge DFF
Pepijn de Vos [Mon, 21 Oct 2019 10:00:27 +0000 (12:00 +0200)]
use ADDSUB ALU mode to remove inverters
Pepijn de Vos [Mon, 21 Oct 2019 08:51:34 +0000 (10:51 +0200)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
David Shah [Sun, 20 Oct 2019 09:30:41 +0000 (10:30 +0100)]
ecp5: Pass -nomfs to abc9
Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
Miodrag Milanović [Sat, 19 Oct 2019 06:58:02 +0000 (08:58 +0200)]
Merge pull request #1457 from xobs/python-binary-name
Makefile: don't assume python is called `python3`
Sean Cross [Sat, 19 Oct 2019 06:04:52 +0000 (14:04 +0800)]
Makefile: don't assume python is called `python3`
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
Miodrag Milanović [Fri, 18 Oct 2019 12:29:44 +0000 (14:29 +0200)]
Merge pull request #1454 from YosysHQ/mmicko/common_tests
Share common tests
Miodrag Milanovic [Fri, 18 Oct 2019 11:15:36 +0000 (13:15 +0200)]
fixed error
Miodrag Milanovic [Fri, 18 Oct 2019 10:50:24 +0000 (12:50 +0200)]
Unify verilog style