yosys.git
4 years agoMerge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign
clairexen [Thu, 20 Aug 2020 14:19:37 +0000 (16:19 +0200)]
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign

peepopt.muldiv: Add a signedness check.

4 years agoMerge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
clairexen [Thu, 20 Aug 2020 14:18:40 +0000 (16:18 +0200)]
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern

techmap: Add support for [] wildcards in techmap_celltype.

4 years agoBump version
Yosys Bot [Thu, 20 Aug 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2122 from PeterCrozier/struct_array2
clairexen [Wed, 19 Aug 2020 15:58:37 +0000 (17:58 +0200)]
Merge pull request #2122 from PeterCrozier/struct_array2

Support 2D bit arrays in structures. Optimise array indexing.

4 years agoBump version
Yosys Bot [Wed, 19 Aug 2020 00:10:09 +0000 (00:10 +0000)]
Bump version

4 years agoEnsure \A_SIGNED is never used with $shiftx
Xiretza [Fri, 3 Jul 2020 11:13:21 +0000 (13:13 +0200)]
Ensure \A_SIGNED is never used with $shiftx

It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.

4 years agoRespect \A_SIGNED for $shift
Xiretza [Fri, 3 Jul 2020 11:13:21 +0000 (13:13 +0200)]
Respect \A_SIGNED for $shift

This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).

4 years agoinclude both power-of-two and non-power-of-two testcases
N. Engelhardt [Tue, 18 Aug 2020 16:54:22 +0000 (18:54 +0200)]
include both power-of-two and non-power-of-two testcases

4 years agoMerge pull request #2339 from zachjs/display-format-0s
clairexen [Tue, 18 Aug 2020 15:39:01 +0000 (17:39 +0200)]
Merge pull request #2339 from zachjs/display-format-0s

Allow %0s $display format specifier

4 years agoMerge pull request #2338 from zachjs/const-branch-finish
clairexen [Tue, 18 Aug 2020 15:38:07 +0000 (17:38 +0200)]
Merge pull request #2338 from zachjs/const-branch-finish

Propagate const_fold through generate blocks and branches

4 years agoMerge pull request #2317 from zachjs/expand-genblock
clairexen [Tue, 18 Aug 2020 15:37:11 +0000 (17:37 +0200)]
Merge pull request #2317 from zachjs/expand-genblock

Fix generate scoping issues

4 years agoMerge branch 'zachjs-const-func-block-var'
Claire Wolf [Tue, 18 Aug 2020 15:32:00 +0000 (17:32 +0200)]
Merge branch 'zachjs-const-func-block-var'

4 years agoMerge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs...
Claire Wolf [Tue, 18 Aug 2020 15:27:51 +0000 (17:27 +0200)]
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2281 from zachjs/const-real
clairexen [Tue, 18 Aug 2020 15:22:20 +0000 (17:22 +0200)]
Merge pull request #2281 from zachjs/const-real

Allow reals as constant function parameters

4 years agoBump version
Yosys Bot [Fri, 14 Aug 2020 00:10:13 +0000 (00:10 +0000)]
Bump version

4 years agointel_alm: fix typo in MISTRAL_MUL27X27 cell name
Dan Ravensloft [Thu, 13 Aug 2020 14:30:03 +0000 (15:30 +0100)]
intel_alm: fix typo in MISTRAL_MUL27X27 cell name

4 years agoBump version
Yosys Bot [Thu, 13 Aug 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout
whitequark [Wed, 12 Aug 2020 20:02:18 +0000 (20:02 +0000)]
Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout

cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False

4 years agocxxrtl.h: Fix incorrect CarryOut in alu()
Andy Knowles [Wed, 12 Aug 2020 19:04:34 +0000 (21:04 +0200)]
cxxrtl.h: Fix incorrect CarryOut in alu()

4 years agointel_alm: add more megafunctions. NFC.
Dan Ravensloft [Wed, 12 Aug 2020 13:55:42 +0000 (14:55 +0100)]
intel_alm: add more megafunctions. NFC.

4 years agocxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
Andy Knowles [Wed, 12 Aug 2020 09:32:57 +0000 (11:32 +0200)]
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False

4 years agoBump version
Yosys Bot [Mon, 10 Aug 2020 09:30:51 +0000 (09:30 +0000)]
Bump version

4 years agoPropagate const_fold through generate blocks and branches
Zachary Snow [Sun, 9 Aug 2020 15:52:55 +0000 (09:52 -0600)]
Propagate const_fold through generate blocks and branches

4 years agoAllow %0s $display format specifier
Zachary Snow [Sun, 9 Aug 2020 15:31:57 +0000 (09:31 -0600)]
Allow %0s $display format specifier

4 years agoReplace opt_rmdff with opt_dff.
Marcelina Kościelnicka [Mon, 20 Jul 2020 21:19:51 +0000 (23:19 +0200)]
Replace opt_rmdff with opt_dff.

4 years agopeepopt.muldiv: Add a signedness check.
Marcelina Kościelnicka [Tue, 4 Aug 2020 14:30:24 +0000 (16:30 +0200)]
peepopt.muldiv: Add a signedness check.

Fixes #2318.

4 years agotechmap: Add support for [] wildcards in techmap_celltype.
Marcelina Kościelnicka [Sun, 2 Aug 2020 10:31:25 +0000 (12:31 +0200)]
techmap: Add support for [] wildcards in techmap_celltype.

Fixes #1826.

4 years agoFix generate scoping issues
Zachary Snow [Sat, 1 Aug 2020 02:13:05 +0000 (20:13 -0600)]
Fix generate scoping issues

- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456

4 years agoBump YOSYS_VER
Claire Wolf [Fri, 31 Jul 2020 18:57:41 +0000 (20:57 +0200)]
Bump YOSYS_VER

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoAdd dffunmap pass.
Marcelina Kościelnicka [Mon, 27 Jul 2020 13:24:57 +0000 (15:24 +0200)]
Add dffunmap pass.

To be used with backends that cannot deal with fancy FF types (like blif
or smt).

4 years agoopt_expr: Remove -clkinv option, make it the default.
Marcelina Kościelnicka [Fri, 24 Jul 2020 11:08:54 +0000 (13:08 +0200)]
opt_expr: Remove -clkinv option, make it the default.

Adds -noclkinv option just in case the old behavior was actually useful
to someone.

4 years agosynth_ice40: Use opt_dff.
Marcelina Kościelnicka [Wed, 22 Jul 2020 11:34:11 +0000 (13:34 +0200)]
synth_ice40: Use opt_dff.

The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.

4 years agosynth_xilinx: Use opt_dff.
Marcelina Kościelnicka [Wed, 22 Jul 2020 10:27:15 +0000 (12:27 +0200)]
synth_xilinx: Use opt_dff.

The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.

4 years agoasync2sync: Support all FF types.
Marcelina Kościelnicka [Fri, 24 Jul 2020 15:01:26 +0000 (17:01 +0200)]
async2sync: Support all FF types.

4 years agoAdd opt_dff pass.
Marcelina Kościelnicka [Tue, 14 Jul 2020 22:58:07 +0000 (00:58 +0200)]
Add opt_dff pass.

4 years agoverilog_backend: Add handling for all FF types.
Marcelina Kościelnicka [Tue, 23 Jun 2020 21:46:00 +0000 (23:46 +0200)]
verilog_backend: Add handling for all FF types.

4 years agoMerge pull request #2314 from YosysHQ/verifix_errorfix
Miodrag Milanović [Wed, 29 Jul 2020 13:41:26 +0000 (15:41 +0200)]
Merge pull request #2314 from YosysHQ/verifix_errorfix

Verific - prevent exit yosys due to stored error

4 years agoClear last error message
Miodrag Milanovic [Wed, 29 Jul 2020 13:28:33 +0000 (15:28 +0200)]
Clear last error message

4 years agoopt_expr: Fix handling of $_XNOR_ cells with A = B.
Marcelina Kościelnicka [Wed, 29 Jul 2020 08:00:01 +0000 (10:00 +0200)]
opt_expr: Fix handling of $_XNOR_ cells with A = B.

Fixes #2311.

4 years agoffinit: Fortify the code a bit.
Marcelina Kościelnicka [Tue, 28 Jul 2020 00:11:29 +0000 (02:11 +0200)]
ffinit: Fortify the code a bit.

This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.

4 years agoMerge pull request #2301 from zachjs/for-loop-errors
clairexen [Tue, 28 Jul 2020 12:07:26 +0000 (14:07 +0200)]
Merge pull request #2301 from zachjs/for-loop-errors

Clearer for loop error messages

4 years agoMerge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
clairexen [Tue, 28 Jul 2020 10:56:22 +0000 (12:56 +0200)]
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef

equiv_induct: Fix up assumption for $equiv cells in -undef mode.

4 years agoequiv_induct: Fix up assumption for $equiv cells in -undef mode.
Marcelina Kościelnicka [Mon, 27 Jul 2020 16:28:01 +0000 (18:28 +0200)]
equiv_induct: Fix up assumption for $equiv cells in -undef mode.

Before this fix, equiv_induct only assumed that one of the following is
true:

- defined value of A is equal to defined value of B
- A is undefined

This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A.  Instead, tighten this up to OR of the following:

- defined value of A is equal to defined value of B, and B is not
  undefined
- A is undefined

4 years agointel_alm: direct M10K instantiation
Dan Ravensloft [Sun, 26 Jul 2020 18:28:10 +0000 (19:28 +0100)]
intel_alm: direct M10K instantiation

This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.

4 years agointel_alm: increase abc9 -W
Dan Ravensloft [Sun, 26 Jul 2020 18:11:55 +0000 (19:11 +0100)]
intel_alm: increase abc9 -W

4 years agoMerge pull request #2299 from zachjs/arg-loop
clairexen [Sun, 26 Jul 2020 19:34:55 +0000 (21:34 +0200)]
Merge pull request #2299 from zachjs/arg-loop

Avoid generating wires for function args which are constant

4 years agoClearer for loop error messages
Zachary Snow [Sat, 25 Jul 2020 16:35:03 +0000 (10:35 -0600)]
Clearer for loop error messages

4 years agoAllow blocks with declarations within constant functions
Zachary Snow [Sat, 25 Jul 2020 16:16:12 +0000 (10:16 -0600)]
Allow blocks with declarations within constant functions

4 years agoAvoid generating wires for function args which are constant
Zachary Snow [Sat, 25 Jul 2020 03:18:24 +0000 (21:18 -0600)]
Avoid generating wires for function args which are constant

4 years agoasync2sync: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:25:30 +0000 (03:25 +0200)]
async2sync: Refactor to use FfInitVals.

4 years agomemory_dff: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:28:55 +0000 (02:28 +0200)]
memory_dff: Refactor to use FfInitVals.

4 years agoproc_dlatch: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:25:32 +0000 (02:25 +0200)]
proc_dlatch: Refactor to use FfInitVals.

4 years agopmux2shift: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:19:38 +0000 (02:19 +0200)]
pmux2shift: Refactor to use FfInitVals.

4 years agowreduce: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:19:23 +0000 (02:19 +0200)]
wreduce: Refactor to use FfInitVals.

4 years agotechmap: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:17:31 +0000 (02:17 +0200)]
techmap: Refactor to use FfInitVals.

4 years agoshregmap: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:14:15 +0000 (02:14 +0200)]
shregmap: Refactor to use FfInitVals.

4 years agoabc: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:07:24 +0000 (02:07 +0200)]
abc: Refactor to use FfInitVals.

4 years agodffinit: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:06:25 +0000 (02:06 +0200)]
dffinit: Refactor to use FfInitVals.

4 years agozinit: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:05:32 +0000 (02:05 +0200)]
zinit: Refactor to use FfInitVals.

4 years agodfflegalize: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:04:38 +0000 (02:04 +0200)]
dfflegalize: Refactor to use FfInitVals.

4 years agoclk2fflogic: Support all FF types.
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:25:41 +0000 (03:25 +0200)]
clk2fflogic: Support all FF types.

4 years agosatgen: Add support for dffe, sdff, sdffe, sdffce cells.
Marcelina Kościelnicka [Mon, 20 Jul 2020 20:49:30 +0000 (22:49 +0200)]
satgen: Add support for dffe, sdff, sdffe, sdffce cells.

4 years agoAdd utility module for representing flip-flops.
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:51:05 +0000 (03:51 +0200)]
Add utility module for representing flip-flops.

4 years agomemory_dff: recognize more dff cells
Marcelina Kościelnicka [Mon, 20 Jul 2020 21:58:00 +0000 (23:58 +0200)]
memory_dff: recognize more dff cells

4 years agoAdd utility module for dealing with init attributes.
Marcelina Kościelnicka [Sat, 18 Jul 2020 23:59:47 +0000 (01:59 +0200)]
Add utility module for dealing with init attributes.

4 years agoMerge pull request #2285 from YosysHQ/mwk/techmap-cellname
clairexen [Thu, 23 Jul 2020 16:39:42 +0000 (18:39 +0200)]
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname

techmap: Add _TECHMAP_CELLNAME_ special parameter.

4 years agoMerge pull request #2294 from Ravenslofty/intel_alm_timings
clairexen [Thu, 23 Jul 2020 16:21:20 +0000 (18:21 +0200)]
Merge pull request #2294 from Ravenslofty/intel_alm_timings

intel_alm: add additional ABC9 timings

4 years agointel_alm: add additional ABC9 timings
Dan Ravensloft [Tue, 21 Jul 2020 12:58:38 +0000 (13:58 +0100)]
intel_alm: add additional ABC9 timings

4 years agoRemove EXPLICIT_CARRY logic.
Keith Rothman [Mon, 19 Aug 2019 15:42:09 +0000 (08:42 -0700)]
Remove EXPLICIT_CARRY logic.

The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
4 years agotechmap: Add _TECHMAP_CELLNAME_ special parameter.
Marcelina Kościelnicka [Tue, 21 Jul 2020 13:00:54 +0000 (15:00 +0200)]
techmap: Add _TECHMAP_CELLNAME_ special parameter.

This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.

4 years agoMerge pull request #2215 from boqwxp/qbfsat-solver-options
clairexen [Tue, 21 Jul 2020 12:43:33 +0000 (14:43 +0200)]
Merge pull request #2215 from boqwxp/qbfsat-solver-options

qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands

4 years agosmtio: Emit `mode: start` options before `set-logic` command and any other options...
Alberto Gonzalez [Mon, 20 Jul 2020 22:09:44 +0000 (22:09 +0000)]
smtio: Emit `mode: start` options before `set-logic` command and any other options after it.

Refer to the SMT-LIB specification, section 4.1.7.  According to the spec, some options can only be specified in `start` mode.  Once the solver sees `set-logic`, it moves to `assert` mode.

4 years agosmtio: Add support for parsing `yosys-smt2-solver-option` info statements.
Alberto Gonzalez [Wed, 1 Jul 2020 20:04:56 +0000 (20:04 +0000)]
smtio: Add support for parsing `yosys-smt2-solver-option` info statements.

4 years agoqbfsat: Add `-solver-option` option.
Alberto Gonzalez [Mon, 29 Jun 2020 04:41:18 +0000 (04:41 +0000)]
qbfsat: Add `-solver-option` option.

4 years agosmt2: Add `-solver-option` option.
Alberto Gonzalez [Wed, 1 Jul 2020 20:51:14 +0000 (20:51 +0000)]
smt2: Add `-solver-option` option.

4 years agoMerge pull request #2282 from YosysHQ/claire/satunsat
clairexen [Mon, 20 Jul 2020 21:06:36 +0000 (23:06 +0200)]
Merge pull request #2282 from YosysHQ/claire/satunsat

Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc

4 years agocelltypes: Fix EN port name for some FF types.
Marcelina Kościelnicka [Mon, 20 Jul 2020 19:43:05 +0000 (21:43 +0200)]
celltypes: Fix EN port name for some FF types.

4 years agoOnly allow "sat" and "unsat" smt solver responses in yosys-smtbmc
Claire Wolf [Mon, 20 Jul 2020 17:35:32 +0000 (19:35 +0200)]
Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2276 from YosysHQ/mwk/satgen-cc
clairexen [Mon, 20 Jul 2020 13:23:14 +0000 (15:23 +0200)]
Merge pull request #2276 from YosysHQ/mwk/satgen-cc

satgen: Move importCell out of the header.

4 years agoAllow reals as constant function parameters
Zachary Snow [Mon, 20 Jul 2020 02:27:09 +0000 (20:27 -0600)]
Allow reals as constant function parameters

4 years agosatgen: Move importCell out of the header.
Marcelina Kościelnicka [Sat, 18 Jul 2020 22:17:02 +0000 (00:17 +0200)]
satgen: Move importCell out of the header.

This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.

4 years agoMerge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix
Miodrag Milanović [Fri, 17 Jul 2020 13:05:46 +0000 (15:05 +0200)]
Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix

sf2: Emit CLKINT even if -clkbuf not passed

4 years agosf2: Emit CLKINT even if -clkbuf not passed
Marcelina Kościelnicka [Fri, 17 Jul 2020 13:01:45 +0000 (15:01 +0200)]
sf2: Emit CLKINT even if -clkbuf not passed

This restores pre #2229 behavior.

4 years agoMerge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
Miodrag Milanović [Fri, 17 Jul 2020 12:39:31 +0000 (14:39 +0200)]
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix

anlogic: Fix FF mapping.

4 years agoanlogic: Fix FF mapping.
Marcelina Kościelnicka [Fri, 17 Jul 2020 12:03:21 +0000 (14:03 +0200)]
anlogic: Fix FF mapping.

4 years agoMerge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs
clairexen [Thu, 16 Jul 2020 16:33:56 +0000 (18:33 +0200)]
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs

sf2: replace sf2_iobs with {clkbuf,iopad}map

4 years agoMerge pull request #2273 from whitequark/write-verilog-always-star-initial
clairexen [Thu, 16 Jul 2020 16:30:50 +0000 (18:30 +0200)]
Merge pull request #2273 from whitequark/write-verilog-always-star-initial

verilog_backend: in non-SV mode, add a trigger for `always @*`

4 years agoMerge pull request #2272 from whitequark/write-verilog-sv
clairexen [Thu, 16 Jul 2020 16:28:24 +0000 (18:28 +0200)]
Merge pull request #2272 from whitequark/write-verilog-sv

verilog_backend: add `-sv` option, make `-o <filename>.sv` work

4 years agoMerge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
Miodrag Milanović [Thu, 16 Jul 2020 16:07:58 +0000 (18:07 +0200)]
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic

anlogic: Use dfflegalize.

4 years agoMerge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf
Miodrag Milanović [Thu, 16 Jul 2020 16:07:41 +0000 (18:07 +0200)]
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf

efinix: Nuke efinix_gbuf in favor of clkbufmap.

4 years agoverilog_backend: in non-SV mode, add a trigger for `always @*`.
whitequark [Thu, 16 Jul 2020 11:26:31 +0000 (11:26 +0000)]
verilog_backend: in non-SV mode, add a trigger for `always @*`.

This commit only affects translation of RTLIL processes (for which
there is limited support).

Due to the event-driven nature of Verilog, processes like

    reg x;
    always @*
        x <= 1;

may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:

    reg init = 0;
    reg x;
    always @* begin
        if (init) begin end
        x <= 1;
    end

Fixes #2271.

4 years agoverilog_backend: add `-sv` option, make `-o <filename>.sv` work.
whitequark [Thu, 16 Jul 2020 10:34:21 +0000 (10:34 +0000)]
verilog_backend: add `-sv` option, make `-o <filename>.sv` work.

See #2271.

4 years agoMerge pull request #2270 from whitequark/cxxrtl-fix-typo
whitequark [Thu, 16 Jul 2020 09:48:10 +0000 (09:48 +0000)]
Merge pull request #2270 from whitequark/cxxrtl-fix-typo

cxxrtl: fix typo

4 years agoMerge pull request #2269 from YosysHQ/claire/bisonwall
whitequark [Wed, 15 Jul 2020 19:20:33 +0000 (19:20 +0000)]
Merge pull request #2269 from YosysHQ/claire/bisonwall

Use "bison -Wall -Werror" for verilog front-end

4 years agoTreat all bison warnings as errors in verilog front-end
Claire Wolf [Wed, 15 Jul 2020 09:57:31 +0000 (11:57 +0200)]
Treat all bison warnings as errors in verilog front-end

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoUse %precedence in verilog_parser.y
Claire Wolf [Wed, 15 Jul 2020 09:54:28 +0000 (11:54 +0200)]
Use %precedence in verilog_parser.y

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoFix bison warnings for missing %empty
Claire Wolf [Tue, 14 Jul 2020 22:04:23 +0000 (00:04 +0200)]
Fix bison warnings for missing %empty

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoRun bison with -Wall for verilog front-end
Claire Wolf [Tue, 14 Jul 2020 22:04:04 +0000 (00:04 +0200)]
Run bison with -Wall for verilog front-end

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2257 from antmicro/fix-conflicts
clairexen [Wed, 15 Jul 2020 09:49:09 +0000 (11:49 +0200)]
Merge pull request #2257 from antmicro/fix-conflicts

Restore #2203 and #2244 and fix parser conflicts

4 years agoAdd missing semicolons
Kamil Rakoczy [Wed, 15 Jul 2020 08:15:13 +0000 (10:15 +0200)]
Add missing semicolons

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>