nvc0/ir: insn can never be null

Reported by Coverity.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: size is a uint16_t, remove unnecessary assertion

Reported by Coverity.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: avoid null deref of screen when collecting stats

Reported by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: use 64-bit math when scaling the query results

Reported by Coverity.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallivm: (trivial) don't try to use rcp when the division 1/x is integer

This would just crash. Noticed by accident while checking int divisions by zero
with a quickly hacked piglit test.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

docs: (trivial) mark softpipe, llvmpipe as done for GL_ARB_base_instance

Forgot to add it when I fixed up the start instance handling in (llvm) draw.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: (trivial) fix min / max variable names

Calling the variable min when it's really max and vice versa seems a bit
confusing.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

i965: Handle ir_binop_ubo_load in boolean expression code.

UBO loads can be boolean-valued expressions, too, so we need to handle
them in emit_bool_to_cond_code() and emit_if_gen6().

However, unlike most expressions, it doesn't make sense to evaluate
their operands, then do something with the results.  We just want to
evaluate the UBO load as a whole---which performs the read from
memory---then load the boolean result into the flag register.

Instead of adding code to handle it, we can simply bypass the
ir_expression handling, and fall through to the default code, which will
do exactly that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83468
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

i965/fs: Make emit_if_gen6 never fall back to emit_bool_to_cond_code.

Matt and I believe that Sandybridge actually uses 0xFFFFFFFF for a
"true" comparison result, similar to Ivybridge.  This matches the
internal documentation, and empirical results, but contradicts the PRM.

So, the comment is inaccurate, and we can actually just handle these
directly without ever needing to fall through to the condition code
path.

Also, the vec4 backend has always done it this way, and has apparently
been working fine.  This patch makes the FS backend match the vec4
backend's behavior.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Handle ir_triop_csel in emit_if_gen6().

ir_triop_csel can return a boolean expression, so we need to handle it
here; we simply forgot when we added ir_triop_csel, and forgot again
when adding it to emit_bool_to_cond_code.

Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool on Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

mesa/st: don't advertise NV_vdpau_interop if it doesn't work.

As long as we don't have a workaround for frame based
decoding in VDPAU we should not advertise NV_vdpau_interop.

v2: fix commit message, check if get_video_param is present

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

docs: add news link to 10.2.7 release notes

i965/fs: Remove direct fs_visitor gl_fragment_program dependence

Instead we cast backend_visitor::prog for fragment shader specific code paths.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallivm: Fix Altivec pack intrinsics for little-endian

This patch fixes use of Altivec pack intrinsics on little-endian PowerPC
systems.  Since little-endian operation only affects the load and store
instructions, the semantics of pack (and other) instructions that take
two input vectors implicitly change: the pack instructions still fill
a register placing values from the first operand into the "high" parts
of the register, and values from the second operand into the "low" parts
of the register, but since vector loads and stores perform an endian swap,
the high parts end up at high memory addresses.

To still achieve the desired effect, we have to swap the two inputs to
the pack instruction on little-endian systems.  This is done automatically
by the back-end for instructions generated by LLVM, but needs to be done
manually when emitting intrisincs (which still result in that instruction
being emitted directly).

Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Maarten Lankhorst <dev@mblankhorst.nl>

i965/fs: Remove direct fs_generator brw_wm_prog_key dependence

Instead we store a void pointer to the key, and cast it to
brw_wm_prog_key for fragment shader specific code paths.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Remove direct fs_generator brw_wm_prog_data dependence

Instead we store a brw_stage_prog_data pointer, and cast it to
brw_wm_prog_data for fragment shader specific code paths.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Don't store gl_fragment_program* in fs_generator

gl_program* is named prog similar to backend_visitor.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add uses_kill to brw_wm_prog_data

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Rename fs_generator::prog to shader_prog

This matches backend_visitor, and will allow gl_program to be named prog.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add stage variable to fs_generator

This will allow for stage specific code paths.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Adjust fast-clear resolve rect for BDW

The scale factors for the resolve rectangle change for BDW and we have
to look at brw->gen now to figure out how big it should be.

Fixes: https://bugs.freedesktop.org/attachment.cgi?id=105777
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nvc0/ir: clarify recursion fix to finding first tex uses

This is a simple shader for reproducing the case mentioned:

FRAG
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.0000,    -1.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].x, CONST[0].wwww
  1: MOV TEMP[1].x, CONST[0].wwww
  2: BGNLOOP
  3:   IF TEMP[0].xxxx
  4:     BRK
  5:   ENDIF
  6:   ADD TEMP[0].x, TEMP[0], IMM[0].zzzz
  7:   IF CONST[0].xxxx
  8:     TEX TEMP[1].x, CONST[0], SAMP[0], 2D
  9:   ENDIF
 10:   IF CONST[0].zzzz
 11:     MOV TEMP[1].x, CONST[0].zzzz
 12:   ENDIF
 13: ENDLOOP
 14: MOV OUT[0], TEMP[1].xxxx
 15: END

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir/util: fix BitSet issues

BitSet::allocate() is being used with the expectation that it would
leave the bitfield untouched if its size hasn't changed, however,
the function always zeroed the last word, which led to obscure bugs
with live set computation.

This also fixes BitSet::resize(), which was broken, but luckily not
being used.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: remove nvc0_push, replaced with nvc0_vbo_translate

Fixes build.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50,nvc0: get rid of draw module support

This hasn't been enabled in a long time and is completely stale and
unnecessary. Remove, esp since it doesn't build.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/fs: Don't look at virtual_grf_sizes for uniforms

Uniform values are in the UNIFORM register file, not the GRF register file.
Looking in virtual_grf_sizes makes no sense and only makes the output of
dump_instructions confusing.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

loader: fds can be 0

Possible resource leak reported by coverity.

Reported-by: Coverity scanner.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

docs: Import 10.2.7 release notes, add news item.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/vc4: ship all files in the tarball

 - include all headers in Makefile.sources

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/trace: ship all files in the tarball

 - include all headers in Makefile.sources
 - bundle the scons buildscript, README and trace.xsl

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/svga: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android & scons buildscript
 - include the headers' README & svga_dump.py

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/softpipe: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android & scons buildscript

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/rbug: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript & README

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/radeonsi: ship all files in the tarball

 - include all headers in Makefile.sources
 - bundle the android buildscript

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/radeon: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript & LLVM note

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/r600: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript & custom include

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/r300: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript & the tests

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/nouveau: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript

v2: Don't double-include the compiler sources.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/noop: ship all files in the tarball

 - include all headers in Makefile.sources
 - bundle the scons buildscript

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/llvmpipe: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the scons buildscript

v2: Don't double include the test sources.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/identity: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the scons buildscript

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/ilo: ship all files in the tarball

 - include all headers in Makefile.sources
 - bundle the android buildscript

Cc: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/i915: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android buildscript & TODO

Cc: Stephane Marchesin <stephane.marchesin@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/galahad: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the scons buildscript

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/freedreno: ship all files in the tarball

 - include all headers in Makefile.sources
 - sort the list(s)
 - bundle the android build

Cc: freedreno@lists.freedesktop.org
Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/tools: pick up the tools for distribution

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/tests: ship all the tests in the release tarball

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/vega: ship the final headers

Commit 60d772cd9d1(st/vega: add headers and SConscript in
the tarball) meant to pick all the headers to be included in
the release tarball yet it missed a few.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/egl: include the remaining files in the tarball

A few files were missing, namely:
 - a few of the common headers
 - the android + gdi sources

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/glx/xlib: ship the SConscript in the release tarball

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/dri: ship the scons buildscript in the release tarball

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/clover: ship Doxyfile in the release tarball

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium: ship state-tracker/README in the release tarball

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium: ship the non-automaked state-trackers & targets

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

winsys/intel: drop intel_winsys.h from makefile.sources

With the last revisions of commit 664c2d76947(gallium/ilo: cleanup
intel_winsys.h) we moved the header from winsys to drivers, but we
forgot to update the makefile.sources to reflect this.

Cc: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

meta: Store precompiled msaa shaders for all supported sample counts

Currently, BLIT_MSAA_SHADER_2D_MULTISAMPLE_RESOLVE* and
BLIT_MSAA_SHADER_2D_MULTISAMPLE_ARRAY_RESOLVE* shaders
in setup_glsl_msaa_blit_shader() are not recompiled
when the source buffer sample count changes. For example,
implementation continued using a 4X msaa shader, even if
source buffer changes from 4X msaa to 8x msaa. It causes
incorrect rendering.

This patch adds new enums in blit_msaa_shader, one for
each supported sample count, and uses them to store
msaa shaders.

Fixes following piglit tests on Broadwell:
ext_framebuffer_multisample-accuracy all_samples color
ext_framebuffer_multisample-accuracy all_samples depth_draw
ext_framebuffer_multisample-accuracy all_samples depth_resolve
ext_framebuffer_multisample-accuracy all_samples stencil_draw
ext_framebuffer_multisample-accuracy all_samples stencil_resolve
ext_framebuffer_multisample-formats all_samples

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstarnd <jason@jlekstrand.net>

configure: check for core xcb and link the VL targets against it

Make sure to check the presence of the module in order to pick the
correct libs flag and before feeding them to the compiler/linker.

Current libXvMC*, libvdpau* and libomx_mesa depends unconditionally
upon xcb, due to their usage of the aux/vl gallium module.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

configure: check for core xcb and link libEGL against it

Make sure to check the presence of the module in order to pick the
correct libs flag and before feeding them to the compiler/linker.

Current libEGL depends conditionally (when building with x11 platform)
upon xcb.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

configure: check for core xcb and link libGL against it

Make sure to check the presence of the module in order to pick the
correct libs flag and before feeding them to the compiler/linker.

Current libGL depends conditionally (when building with dri3) upon
xcb 1.9.3 and unconditionally on ancient xcb functions -
xcb_generate_id and xcb_request_check amongst others.

v2: Use PKG_CHECK_EXISTS() when checking for dri3 xcb.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80848
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/blorp: Pass image formats seperately from the miptree

When a texture is wrapped in a texture view, we can't trust the format in
the miptree itself.  This patch allows us to pass the format seperately
through blorp so we can proprerly handled wrapped textures.

It's worth noting here that we can use the miptree format directly for
depth/stencil formats because they cannot be reinterpreted by a texture
view.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
CC: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Brown bag fix.

i965/vec4: Add ability to reswizzle arbitrary swizzles.

Before commit 04895f5c we would only reswizzle dot product instructions
(since they wrote the same value into all channels, and we didn't have
to think about anything else). That commit extended reswizzling to cases
when the swizzle was single valued -- i.e., writing the same result into
all channels.

But allowing reswizzling of arbitrary things is actually really easy and
is even less code. (Why didn't we do this in the first place?!)

total instructions in shared programs: 4266079 -> 4261000 (-0.12%)
instructions in affected programs:     351933 -> 346854 (-1.44%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Reswizzle sources when necessary.

Despite the comment above the function claiming otherwise, the function
did not reswizzle sources, which would lead to bad code generation since
commit 04895f5c, which began claiming we could do such swizzling when we
could not.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82932
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Clean up emitting of untyped atomic and surface reads

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Fix basic block tracking in try_rep_send().

The 'start' instruction is always in the current block, except for the
case of shader time, which emits code in a pattern seen no where else.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass block to insert and remove functions missed earlier.

Otherwise, the basic block start/end IPs don't get updated properly,
leading to a broken CFG.  This usually results in the following
assertion failure:

brw_fs_live_variables.cpp:141:
void brw::fs_live_variables::setup_def_use():
Assertion `ip == block->start_ip' failed.

Fixes KWin, WebGL demos, and a score of Piglit tests on Sandybridge and
earlier hardware.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Mark cfg dumping functions const.

The dump() methods don't alter the CFG or basic blocks, so we should
mark them as const.  This lets you call them even if you have a const
cfg_t - which is the case in certain portions of the code (such as live
interval handling).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Update if_block/else_block in the dead control flow pass.

I think this bug crept in only recently.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Connect cfg properly in predicated break peephole.

If the ENDIF instruction was the only instruction in its block, we'd
leave the successors of the merged if+jump block in a bad state.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83080
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: use 1.0f as boolean true on drivers without integer support

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82882

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: set UniformBooleanTrue = 1.0f by default

because NativeIntegers is 0 by default.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82882

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

automake: check if the linker supports --dynamic-list

As older versions of gnu ld did not support --dynamic-list check to see
if it is supported before using it.  Non gnu linkers such the apple one
likely lack this option as well.

Fixes the build on OpenBSD which has binutils 2.15 and 2.17.
The --dynamic-list option seems to been have introduced sometime after
binutils 2.17 was released as it is present in 2.18.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

st/xvmc/tests: avoid non portable error.h functions

To improve compatibility with OpenBSD.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

kms-swrast: Support Prime fd handling

Allows using prime fds as display target and from display target.
Test for PRIME capability after initializing kms_swrast screen.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Andreas Pokorny <andreas.pokorny@canonical.com>

configure.ac: Add AC_SYS_LARGEFILE

Making sure large file support is enabled across the tree even on 32-bit
systems.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

clover/util: Null-terminate the result of compat::string::c_str().

Reported-by: EdB <edb+mesa@sigluy.net>

clover/util: Implement compat::string using aggregation instead of inheritance.

clover/util: Have compat::vector track separate size and capacity.

In order to make the behaviour of resize() and reserve() closer to the
standard.

Reported-by: EdB <edb+mesa@sigluy.net>

clover: Use conversion operator to initialize build log from compat::string.

Fixes binary garbage in the compilation logs caused by
compat::string::c_str() not being null-terminated (which is a bug on
its own that will be fixed in another commit).

Reported-by: EdB <edb+mesa@sigluy.net>

Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404

Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
   8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
   373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
   c5bdf9be1eca190417998d548fd140c1eca37a54
   Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
   6f56e1424d923fd80c84090fbf4506c9eaaffea1
   Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
   88e3d404dad009d8cff5124cf8acee7daeaceb64

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

freedreno/ir3: fix constlen with relative addressing

We can't rely on the value from the assembler if relative addressing is
used.  So instead use the max of declared-consts (which does not include
compiler immediates) and what we get from the assembler (which does).

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix error in bail logic

all_delayed will also be true if we didn't attempt to schedule anything
due to no more instructions using current addr/pred.  We rely on coming
in to block_sched_undelayed() to detect and clean up when there are no
more uses of the current addr/pred, which isn't necessarily an error.

This fixes a regression introduced in b823abed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: bit of debug

Make it easier to figure out which compiler stage failed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

vc4: Merge qcompile and tgsi_to_qir

The split between these two didn't make much sense.  I'm going to want the
chance to look at uniform contents in optimization passes, and the QPU
emit I think is going to end up rewriting the uniforms stream.

i965/fs: Use prog rather than fp->Base in fs_visitor

Reduce fs_visitor's dependence on gl_fragment_program.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use stage_prog_data instead of prog_data->base in fs_visitor

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add init function to fs_visitor

This common init routine can be used by constructors for multiple program
types.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

vc4: Add a CSE optimization pass.

Debugging a regression in discard support was just too full of duplicate
instructions, so I decided to remove them instead of re-analyzing each of
them as I dumped their outputs in simulation.

vc4: Switch to using native integers.

There were troubles with bools without using native integers
(st_glsl_to_tgsi seemed to think bool true was 1.0f sometimes, when as a
uniform it's stored as ~0), and since I've got native integers other than
divide, I might as well just support them.

vc4: Expose compares at a lower level in QIR.

Before, we had some special opcodes like CMP and SNE that emitted multiple
instructions.  Now, we reduce those operations significantly, giving
optimization more to look at for reducing redundant operations.

The downside is that QOP_SF is pretty special -- we're going to have to
track it separately when we're doing instruction scheduling, and we want
to peephole it into the instruction generating the destination write in
most cases (and not allocate the destination reg, probably.  Unless it's
used for some other purpose, as well).

vc4: Stop being so clever in CMP handling.

This kind of cleverness should be in a general merging-of-ADD-and-MUL
instruction scheduler, rather than individual opcodes.

state_tracker: Fix bug in conditional discards with native ints.

A bool is 0 or ~0, and KILL_IF takes a float arg that's <0 for discard or
>= 0 for not.  By negating it, we ended up doing a floating point subtract
of (0 - ~0), which ended up as an inf.  To make this actually work, we
need to convert the bool to a float.

Reviewed-by: Brian Paul <brianp@vmware.com>

swrast: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

osmesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

xlib: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meta: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600g,radeonsi: make sure there's enough CS space before resuming queries

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83432

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

mesa: invalidate draw state in glPopClientAttrib

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82538

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>

Revert "r600g,radeonsi: initialize HTILE to fully-expanded state"

This reverts commit f05fe294e7e8dfb08be172f426252192c0ba17ab.

Apparently the hw doesn't like this. Revert to the "cleared" state.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83418