litex.git
5 years agoboards/platforms/sp605: apply same simplifications than on others platforms
Florent Kermarrec [Tue, 23 Apr 2019 09:21:55 +0000 (11:21 +0200)]
boards/platforms/sp605: apply same simplifications than on others platforms

5 years agoboards/platforms: add SP605
Michael Betz [Tue, 23 Apr 2019 09:15:42 +0000 (11:15 +0200)]
boards/platforms: add SP605

5 years agocores/cpu/vexriscv: fix wrong revert
Florent Kermarrec [Tue, 23 Apr 2019 09:13:19 +0000 (11:13 +0200)]
cores/cpu/vexriscv: fix wrong revert

5 years agotargets/ac701: cleanup and make it similar to others targets.
Florent Kermarrec [Tue, 23 Apr 2019 09:10:35 +0000 (11:10 +0200)]
targets/ac701: cleanup and make it similar to others targets.

Still supports EthernetSoC with RGMII and 1000BaseX.

5 years agotargets/xilinx: remove keep attribute on clock going to idelayctrl
Florent Kermarrec [Tue, 23 Apr 2019 08:51:36 +0000 (10:51 +0200)]
targets/xilinx: remove keep attribute on clock going to idelayctrl

Causes P&R issues with Vivado.

5 years agoboards/platform/ac701: add proper copyright, cleanup to be similar to others platforms
Florent Kermarrec [Tue, 23 Apr 2019 08:02:07 +0000 (10:02 +0200)]
boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms

5 years agoboards/platforms/kc705: provide only one default programmer as others platforms
Florent Kermarrec [Tue, 23 Apr 2019 08:00:52 +0000 (10:00 +0200)]
boards/platforms/kc705: provide only one default programmer as others platforms

5 years agoboards: Xilinx ac701 dev board support
Vamsi K Vytla [Tue, 23 Apr 2019 07:48:16 +0000 (09:48 +0200)]
boards: Xilinx ac701 dev board support

5 years agobuild/xilinx/ise.py: write .v file for post synthesis sim
Michael Betz [Tue, 23 Apr 2019 07:22:48 +0000 (09:22 +0200)]
build/xilinx/ise.py: write .v file for post synthesis sim

5 years agobuild/xilinx/programmer: cleanup XC3SProg position parameter
Florent Kermarrec [Tue, 23 Apr 2019 07:20:42 +0000 (09:20 +0200)]
build/xilinx/programmer: cleanup XC3SProg position parameter

5 years agobuild/xilinx/programmer: add position parameter to XC3SProg
Michael Betz [Tue, 23 Apr 2019 07:16:42 +0000 (09:16 +0200)]
build/xilinx/programmer: add position parameter to XC3SProg

5 years ago.gitignore: ignore tilde files
Vamsi K Vytla [Tue, 23 Apr 2019 07:10:11 +0000 (09:10 +0200)]
.gitignore: ignore tilde files

5 years agotargets/minispartan6: use S6PLL in CRG
Florent Kermarrec [Tue, 23 Apr 2019 04:44:29 +0000 (06:44 +0200)]
targets/minispartan6: use S6PLL in CRG

5 years agocores/clock: add divclk_divide_range on S6PLL/S6DCM
Florent Kermarrec [Tue, 23 Apr 2019 04:43:48 +0000 (06:43 +0200)]
cores/clock: add divclk_divide_range on S6PLL/S6DCM

5 years agocores/clock: use common XilinxClocking class for all Xilinx clocking modules
Florent Kermarrec [Tue, 23 Apr 2019 04:35:39 +0000 (06:35 +0200)]
cores/clock: use common XilinxClocking class for all Xilinx clocking modules

5 years agocores/clock: add initial Spartan6 PLL/DCM support
Michael Betz [Tue, 23 Apr 2019 04:23:00 +0000 (06:23 +0200)]
cores/clock: add initial Spartan6 PLL/DCM support

5 years agobuild: add git version (sha-1) used to create the scripts
Florent Kermarrec [Tue, 23 Apr 2019 04:03:12 +0000 (06:03 +0200)]
build: add git version (sha-1) used to create the scripts

5 years agobuild: scripts are generated by LiteX
Florent Kermarrec [Tue, 23 Apr 2019 03:38:33 +0000 (05:38 +0200)]
build: scripts are generated by LiteX

5 years agobuild/xilinx/vivado: cleanup pull request #170
Florent Kermarrec [Tue, 23 Apr 2019 03:33:56 +0000 (05:33 +0200)]
build/xilinx/vivado: cleanup pull request #170

5 years agoMerge pull request #170 from ldoolitt/master
enjoy-digital [Tue, 23 Apr 2019 03:26:54 +0000 (05:26 +0200)]
Merge pull request #170 from ldoolitt/master

build/xilinx/vivado: only try Xilinx setup if vivado is not already i…

5 years agobuild/xilinx/vivado: only try Xilinx setup if vivado is not already in the path
Larry Doolittle [Mon, 22 Apr 2019 22:42:31 +0000 (15:42 -0700)]
build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path

Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.

5 years agoglobal: switch to VexRiscv as the default CPU
Florent Kermarrec [Mon, 22 Apr 2019 07:37:00 +0000 (09:37 +0200)]
global: switch to VexRiscv as the default CPU

VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.

5 years agoci: fix test_targets/test_simple
Florent Kermarrec [Mon, 22 Apr 2019 06:53:43 +0000 (08:53 +0200)]
ci: fix test_targets/test_simple

5 years agotest: remove waveforms generation
Florent Kermarrec [Mon, 22 Apr 2019 06:41:28 +0000 (08:41 +0200)]
test: remove waveforms generation

5 years agotravis: simplify, enable and add RISC-V toolchain to build targets
Florent Kermarrec [Mon, 22 Apr 2019 06:32:00 +0000 (08:32 +0200)]
travis: simplify, enable and add RISC-V toolchain to build targets

5 years agoboards/platforms: add separators, cleanup imports
Florent Kermarrec [Sat, 20 Apr 2019 22:44:23 +0000 (00:44 +0200)]
boards/platforms: add separators, cleanup imports

5 years agoboards/platforms: provide only one default programmer per platform.
Florent Kermarrec [Sat, 20 Apr 2019 22:17:03 +0000 (00:17 +0200)]
boards/platforms: provide only one default programmer per platform.

create_programmer is not really longer used, so try to keep it simple.

5 years agoboards/platforms/kc705: only keep Vivado support
Florent Kermarrec [Sat, 20 Apr 2019 22:04:56 +0000 (00:04 +0200)]
boards/platforms/kc705: only keep Vivado support

There is no reason still using ISE on 7-Series.

5 years agoboards: always define timing constraints the same way (1e9/freq_mhz)
Florent Kermarrec [Sat, 20 Apr 2019 21:56:27 +0000 (23:56 +0200)]
boards: always define timing constraints the same way (1e9/freq_mhz)

5 years agoboards/targets/ulx3s: allow running test_targets on it
Florent Kermarrec [Sat, 20 Apr 2019 21:47:05 +0000 (23:47 +0200)]
boards/targets/ulx3s: allow running test_targets on it

5 years agoboards/targets: add keep attribute directly in crg
Florent Kermarrec [Sat, 20 Apr 2019 21:43:44 +0000 (23:43 +0200)]
boards/targets: add keep attribute directly in crg

This makes it systematic and avoid having to add it later.

5 years agoMerge pull request #167 from xobs/network-flag-check
enjoy-digital [Sat, 20 Apr 2019 10:23:24 +0000 (12:23 +0200)]
Merge pull request #167 from xobs/network-flag-check

litex_server: check socket flags exist before using them

5 years agolitex_server: check socket flags exist before using them
Sean Cross [Sat, 20 Apr 2019 09:28:26 +0000 (17:28 +0800)]
litex_server: check socket flags exist before using them

Some flags are only available on certain platforms.  Verify these flags
exist prior to using them when opening a socket.

See
https://stackoverflow.com/questions/14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information

Signed-off-by: Sean Cross <sean@xobs.io>
5 years agotools: move from litex.soc.tools to litex.tools and fix usb.core import
Florent Kermarrec [Sat, 20 Apr 2019 08:44:53 +0000 (10:44 +0200)]
tools: move from litex.soc.tools to litex.tools and fix usb.core import

5 years agoMerge pull request #165 from xobs/vexriscv-cpu-reset-address
enjoy-digital [Fri, 19 Apr 2019 17:16:16 +0000 (19:16 +0200)]
Merge pull request #165 from xobs/vexriscv-cpu-reset-address

Vexriscv cpu reset address

5 years agoMerge pull request #164 from xobs/litex-usb-server
enjoy-digital [Fri, 19 Apr 2019 17:14:15 +0000 (19:14 +0200)]
Merge pull request #164 from xobs/litex-usb-server

Litex usb server support

5 years agoutils: litex_server: add usb support
Sean Cross [Fri, 19 Apr 2019 14:56:39 +0000 (15:56 +0100)]
utils: litex_server: add usb support

Add `--usb` and associated arguments to create a litex bridge over
USB.  This makes use of the new CommUSB module.

Signed-off-by: Sean Cross <sean@xobs.io>
5 years agotools: remote: add usb communications protocol
Sean Cross [Fri, 19 Apr 2019 14:54:48 +0000 (15:54 +0100)]
tools: remote: add usb communications protocol

This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.

Signed-off-by: Sean Cross <sean@xobs.io>
5 years agosoc/interconnect/axi: add AXIBurst2Beat
Florent Kermarrec [Fri, 19 Apr 2019 10:13:16 +0000 (12:13 +0200)]
soc/interconnect/axi: add AXIBurst2Beat

Converts AXI bursts commands to AXI beats.

5 years agosoc/interconnect/avalon: add description
Florent Kermarrec [Fri, 19 Apr 2019 09:43:15 +0000 (11:43 +0200)]
soc/interconnect/avalon: add description

5 years agoMerge branch 'master' of https://github.com/enjoy-digital/litex
Sean Cross [Fri, 19 Apr 2019 08:47:55 +0000 (16:47 +0800)]
Merge branch 'master' of https://github.com/enjoy-digital/litex

5 years agosoc/integration/soc_zynq: fix HP0 connections
Florent Kermarrec [Fri, 19 Apr 2019 08:21:56 +0000 (10:21 +0200)]
soc/integration/soc_zynq: fix HP0 connections

5 years agobuild/xilinx/vivado: only set library for vhdl files (not supported for verilog/syste...
Florent Kermarrec [Fri, 19 Apr 2019 07:18:25 +0000 (09:18 +0200)]
build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)

5 years agocpu: vexriscv: allow cpu_reset_address to be overridden
Sean Cross [Fri, 19 Apr 2019 05:04:57 +0000 (13:04 +0800)]
cpu: vexriscv: allow cpu_reset_address to be overridden

Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
5 years agosoc/interconnect: add avalon with converters to/from native streams
Florent Kermarrec [Thu, 18 Apr 2019 16:42:29 +0000 (18:42 +0200)]
soc/interconnect: add avalon with converters to/from native streams

5 years agoMerge pull request #162 from antmicro/full-conf-vexriscv
enjoy-digital [Wed, 17 Apr 2019 17:01:55 +0000 (19:01 +0200)]
Merge pull request #162 from antmicro/full-conf-vexriscv

Add full and full_debug CPU variant of VexRiscv

5 years agoMerge pull request #163 from gsomlo/gls-verilated-cmdargs
enjoy-digital [Wed, 17 Apr 2019 16:59:28 +0000 (18:59 +0200)]
Merge pull request #163 from gsomlo/gls-verilated-cmdargs

build/sim/core: Initialize Verilator commandArgs

5 years agobuild/sim/core: Initialize Verilator commandArgs
Gabriel L. Somlo [Wed, 17 Apr 2019 14:39:35 +0000 (10:39 -0400)]
build/sim/core: Initialize Verilator commandArgs

Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".

5 years agovexriscv: Add full and full_debug CPU variant
Joanna Brozek [Fri, 12 Apr 2019 15:23:23 +0000 (17:23 +0200)]
vexriscv: Add full and full_debug CPU variant

5 years agobuild/altera: switch to sdc constraints, add add_false_path_constraints method
Florent Kermarrec [Tue, 16 Apr 2019 14:57:23 +0000 (16:57 +0200)]
build/altera: switch to sdc constraints, add add_false_path_constraints method

5 years agobuild/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints
Florent Kermarrec [Mon, 15 Apr 2019 14:48:47 +0000 (16:48 +0200)]
build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints

MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.

5 years agosoc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
Florent Kermarrec [Mon, 15 Apr 2019 09:36:42 +0000 (11:36 +0200)]
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale

5 years agosoc/cores/clock: improve presentation
Florent Kermarrec [Mon, 15 Apr 2019 08:57:00 +0000 (10:57 +0200)]
soc/cores/clock: improve presentation

5 years agobuild/xilinx/vivado: round period constraints to lowest picosecond
Florent Kermarrec [Mon, 15 Apr 2019 08:51:17 +0000 (10:51 +0200)]
build/xilinx/vivado: round period constraints to lowest picosecond

Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.

5 years agoMerge pull request #161 from enjoy-digital/litex_server_arguments
enjoy-digital [Mon, 15 Apr 2019 06:24:28 +0000 (08:24 +0200)]
Merge pull request #161 from enjoy-digital/litex_server_arguments

litex_server: refactor parameters and to allow setting bind address

5 years agolitex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination
Florent Kermarrec [Mon, 15 Apr 2019 06:23:27 +0000 (08:23 +0200)]
litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination

5 years agolitex_server: add message and exit when mandarory arguments are missing.
Florent Kermarrec [Sun, 14 Apr 2019 12:00:35 +0000 (14:00 +0200)]
litex_server: add message and exit when mandarory arguments are missing.

5 years agolitex_server: allow setting bind port, remove auto-incrementing on bind_port
Florent Kermarrec [Sun, 14 Apr 2019 10:11:37 +0000 (12:11 +0200)]
litex_server: allow setting bind port, remove auto-incrementing on bind_port

5 years agolitex_server: refactor parameters and to allow setting bind address
Florent Kermarrec [Sun, 14 Apr 2019 06:56:51 +0000 (08:56 +0200)]
litex_server: refactor parameters and to allow setting bind address

In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.

5 years agosoftware/libnet/microudp: simplify txbuffer managment
Florent Kermarrec [Fri, 12 Apr 2019 16:10:44 +0000 (18:10 +0200)]
software/libnet/microudp: simplify txbuffer managment

5 years agosoftware/libnet/microudp: cleanup eth_init
Florent Kermarrec [Fri, 12 Apr 2019 15:15:09 +0000 (17:15 +0200)]
software/libnet/microudp: cleanup eth_init

5 years agosoftware/libnet/microudp: simplify rxbuffer managment
Florent Kermarrec [Fri, 12 Apr 2019 15:14:07 +0000 (17:14 +0200)]
software/libnet/microudp: simplify rxbuffer managment

5 years agosoftware/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE
Florent Kermarrec [Fri, 12 Apr 2019 15:09:50 +0000 (17:09 +0200)]
software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE

5 years agosoftware/libnet: remove use of ethmac_mem.h
Florent Kermarrec [Fri, 12 Apr 2019 15:08:29 +0000 (17:08 +0200)]
software/libnet: remove use of ethmac_mem.h

5 years agobios/sdram: add __attribute__((unused)) on cdelay
Florent Kermarrec [Thu, 11 Apr 2019 20:26:58 +0000 (22:26 +0200)]
bios/sdram: add __attribute__((unused)) on cdelay

5 years agolitex_setup: add litesata
Florent Kermarrec [Wed, 10 Apr 2019 16:04:48 +0000 (18:04 +0200)]
litex_setup: add litesata

5 years agoboards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)
Florent Kermarrec [Wed, 10 Apr 2019 14:36:49 +0000 (16:36 +0200)]
boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)

5 years agosoftware/libnet: add #ifdef on eth_init
Florent Kermarrec [Wed, 10 Apr 2019 14:16:47 +0000 (16:16 +0200)]
software/libnet: add #ifdef on eth_init

5 years agoMerge pull request #158 from vbuitvydas/altera-contrib
enjoy-digital [Mon, 8 Apr 2019 12:32:44 +0000 (14:32 +0200)]
Merge pull request #158 from vbuitvydas/altera-contrib

Changes for litepcie support for Altera Cyclone V

5 years agolitex/build/altera/quartus: changes to make top level assigment in .qsf file with...
vytautasb [Mon, 8 Apr 2019 10:34:59 +0000 (13:34 +0300)]
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name

5 years agolitex/build/altera/common: added reset synchronizer
vytautasb [Mon, 8 Apr 2019 10:28:25 +0000 (13:28 +0300)]
litex/build/altera/common: added reset synchronizer

5 years agointegration/soc_zynq: fix missing SoCCore.do_finalize
Florent Kermarrec [Mon, 1 Apr 2019 12:44:37 +0000 (14:44 +0200)]
integration/soc_zynq: fix missing SoCCore.do_finalize

Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
5 years agointegration/soc_zynq: add add_hp0 method
Florent Kermarrec [Mon, 1 Apr 2019 09:07:30 +0000 (11:07 +0200)]
integration/soc_zynq: add add_hp0 method

5 years agointegration/soc_zynq: use add methods to add optional peripherals
Florent Kermarrec [Mon, 1 Apr 2019 08:50:04 +0000 (10:50 +0200)]
integration/soc_zynq: use add methods to add optional peripherals

5 years agointegration/soc_zynq: connect axi signals that were missing
Florent Kermarrec [Mon, 1 Apr 2019 08:31:33 +0000 (10:31 +0200)]
integration/soc_zynq: connect axi signals that were missing

5 years agointerconnect/axi: add missing axi signals
Florent Kermarrec [Mon, 1 Apr 2019 08:23:05 +0000 (10:23 +0200)]
interconnect/axi: add missing axi signals

5 years agoMerge pull request #157 from CBJamo/master
enjoy-digital [Sun, 31 Mar 2019 16:46:07 +0000 (18:46 +0200)]
Merge pull request #157 from CBJamo/master

Add ifdef check for MAIN_RAM_SIZE

5 years agoAdd ifdef check for MAIN_RAM_SIZE
Caleb Jamison [Sun, 31 Mar 2019 15:33:39 +0000 (10:33 -0500)]
Add ifdef check for MAIN_RAM_SIZE

5 years agoREADME: bump copyright year
Florent Kermarrec [Sat, 30 Mar 2019 11:27:06 +0000 (12:27 +0100)]
README: bump copyright year

5 years agobios/main: align SoC info, show CPU speed on CPU line, show L2
Florent Kermarrec [Sat, 30 Mar 2019 10:49:39 +0000 (11:49 +0100)]
bios/main: align SoC info, show CPU speed on CPU line, show L2

5 years agobios/main: move sdrinit
Florent Kermarrec [Sat, 30 Mar 2019 09:56:17 +0000 (10:56 +0100)]
bios/main: move sdrinit

5 years agobios/main: print boot sequence only if sdr_ok
Florent Kermarrec [Sat, 30 Mar 2019 09:19:00 +0000 (10:19 +0100)]
bios/main: print boot sequence only if sdr_ok

5 years agobios/main: remove csr functions (not used and only supported by lm32), improve help...
Florent Kermarrec [Fri, 29 Mar 2019 18:40:24 +0000 (19:40 +0100)]
bios/main: remove csr functions (not used and only supported by lm32), improve help presentation

5 years agosoftware/bios: improve readibility, add soc informations
Florent Kermarrec [Thu, 28 Mar 2019 23:51:16 +0000 (00:51 +0100)]
software/bios: improve readibility, add soc informations

5 years agoMerge pull request #156 from gsomlo/gls-axi-width
enjoy-digital [Thu, 28 Mar 2019 17:27:36 +0000 (18:27 +0100)]
Merge pull request #156 from gsomlo/gls-axi-width

soc/interconnect/axi: address length cleanup

5 years agosoc/interconnect/axi: data/address length cleanup
Gabriel L. Somlo [Wed, 27 Mar 2019 20:38:25 +0000 (16:38 -0400)]
soc/interconnect/axi: data/address length cleanup

Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.

5 years agosoc/interconnect/axi: remove dead code (thanks gsomlo)
Florent Kermarrec [Wed, 27 Mar 2019 20:15:14 +0000 (21:15 +0100)]
soc/interconnect/axi: remove dead code (thanks gsomlo)

5 years agoMerge pull request #154 from daveshah1/yosys_xilinx_edif
enjoy-digital [Fri, 22 Mar 2019 16:43:40 +0000 (17:43 +0100)]
Merge pull request #154 from daveshah1/yosys_xilinx_edif

build/xilinx: Update Yosys write_edif parameters

5 years agobuild/xilinx: Update Yosys write_edif parameters
David Shah [Fri, 22 Mar 2019 16:06:52 +0000 (16:06 +0000)]
build/xilinx: Update Yosys write_edif parameters

5 years agoutils/litex_sim: fix main_ram_size
Florent Kermarrec [Sat, 16 Mar 2019 20:25:02 +0000 (21:25 +0100)]
utils/litex_sim: fix main_ram_size

5 years agosoc_core/get_mem_data: add json support
Florent Kermarrec [Sat, 16 Mar 2019 20:23:36 +0000 (21:23 +0100)]
soc_core/get_mem_data: add json support

example of json file:
{
    "vmlinux.bin":    "0x00000000",
    "vmlinux.dtb":    "0x01000000",
    "initramdisk.gz": "0x01002000"
}

5 years agobuild/microsemi/libero_soc: add linux build script support
Florent Kermarrec [Sat, 16 Mar 2019 08:33:16 +0000 (09:33 +0100)]
build/microsemi/libero_soc: add linux build script support

5 years agovexriscv: allow user to use an external variant
Florent Kermarrec [Fri, 15 Mar 2019 17:16:25 +0000 (18:16 +0100)]
vexriscv: allow user to use an external variant

5 years agovexriscv/core: fix min variant
Florent Kermarrec [Fri, 15 Mar 2019 16:49:39 +0000 (17:49 +0100)]
vexriscv/core: fix min variant

5 years agoutils/litex_sim: handle cpu_endianness for rom-init/ram-init
Florent Kermarrec [Wed, 13 Mar 2019 09:56:09 +0000 (10:56 +0100)]
utils/litex_sim: handle cpu_endianness for rom-init/ram-init

5 years agoutils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically...
Florent Kermarrec [Wed, 13 Mar 2019 09:42:10 +0000 (10:42 +0100)]
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified

5 years agoMerge pull request #153 from railnova/fix_utils
enjoy-digital [Thu, 7 Mar 2019 20:12:00 +0000 (21:12 +0100)]
Merge pull request #153 from railnova/fix_utils

[fix] utils was omitted when installed from pip

5 years ago[fix] utils was not installed from pip
chmousset [Thu, 7 Mar 2019 08:40:58 +0000 (09:40 +0100)]
[fix] utils was not installed from pip

5 years agoMerge pull request #152 from gsomlo/gls-trellis-svf
enjoy-digital [Wed, 6 Mar 2019 22:41:20 +0000 (23:41 +0100)]
Merge pull request #152 from gsomlo/gls-trellis-svf

build/lattice/trellis: generate bitstream directly in svf format

5 years agobuild/lattice/trellis: also generate bitstream in svf format
Gabriel L. Somlo [Wed, 6 Mar 2019 17:59:49 +0000 (12:59 -0500)]
build/lattice/trellis: also generate bitstream in svf format

Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.