yosys.git
4 years agoopt_expr: restore consume_x; use for coarse grained too
Eddie Hung [Fri, 8 May 2020 18:07:44 +0000 (11:07 -0700)]
opt_expr: restore consume_x; use for coarse grained too

4 years agotests: opt_expr tests that depend on consumex
Eddie Hung [Fri, 8 May 2020 18:07:11 +0000 (11:07 -0700)]
tests: opt_expr tests that depend on consumex

4 years agotests: fsm to use a randomly-generated seed
Eddie Hung [Fri, 24 Apr 2020 21:31:33 +0000 (14:31 -0700)]
tests: fsm to use a randomly-generated seed

4 years agoopt_expr: const_xnor replacement to pad Y with 1'b1
Eddie Hung [Fri, 24 Apr 2020 21:13:45 +0000 (14:13 -0700)]
opt_expr: const_xnor replacement to pad Y with 1'b1

4 years agotests: opt_expr update xnor/xor tests
Eddie Hung [Fri, 24 Apr 2020 18:16:25 +0000 (11:16 -0700)]
tests: opt_expr update xnor/xor tests

4 years agoopt_expr: more fixes for $xor/$xnor
Eddie Hung [Fri, 24 Apr 2020 18:15:29 +0000 (11:15 -0700)]
opt_expr: more fixes for $xor/$xnor

4 years agoopt_expr: do not group by X, more fixes
Eddie Hung [Fri, 24 Apr 2020 01:15:07 +0000 (18:15 -0700)]
opt_expr: do not group by X, more fixes

4 years agotests: add opt_expr tests
Eddie Hung [Thu, 23 Apr 2020 22:58:36 +0000 (15:58 -0700)]
tests: add opt_expr tests

4 years agoopt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
Eddie Hung [Thu, 23 Apr 2020 22:57:48 +0000 (15:57 -0700)]
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too

4 years agoMerge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs
Eddie Hung [Thu, 23 Apr 2020 13:43:30 +0000 (06:43 -0700)]
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs

abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)

4 years agoMerge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs
Claire Wolf [Thu, 23 Apr 2020 09:34:19 +0000 (11:34 +0200)]
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs

qbfsat: Make hole name recovery from source locations more robust.

4 years agoMerge pull request #1988 from boqwxp/qbfsat
Claire Wolf [Thu, 23 Apr 2020 09:33:54 +0000 (11:33 +0200)]
Merge pull request #1988 from boqwxp/qbfsat

qbfsat: Add `-assume-negative-polarity` option.

4 years agoMerge pull request #1986 from YosysHQ/eddie/verific_enum
Claire Wolf [Thu, 23 Apr 2020 09:28:05 +0000 (11:28 +0200)]
Merge pull request #1986 from YosysHQ/eddie/verific_enum

verific: import enum attributes from verific

4 years agointel_alm: work around a Quartus ICE
Dan Ravensloft [Wed, 22 Apr 2020 23:56:49 +0000 (00:56 +0100)]
intel_alm: work around a Quartus ICE

4 years agoqbfsat: Make hole name recovery more robust. Allow multiple cell types to share the...
Alberto Gonzalez [Thu, 23 Apr 2020 05:42:18 +0000 (05:42 +0000)]
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one `$anyconst` or `$anyseq` has that location.

4 years agoMerge pull request #1984 from YosysHQ/eddie/getParam_exception
Eddie Hung [Thu, 23 Apr 2020 05:12:41 +0000 (22:12 -0700)]
Merge pull request #1984 from YosysHQ/eddie/getParam_exception

kernel: Cell::getParam() to throw exception again if not found

4 years agoqbfsat: Add `-assume-negative-polarity` option.
Alberto Gonzalez [Thu, 23 Apr 2020 04:06:15 +0000 (04:06 +0000)]
qbfsat: Add `-assume-negative-polarity` option.

4 years agoecp5: ecp5_gsr to skip cells that don't have GSR parameter again
Eddie Hung [Thu, 23 Apr 2020 00:53:08 +0000 (17:53 -0700)]
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again

4 years agotests: read +/xilinx/cell_sim.v before xilinx_dsp test
Eddie Hung [Thu, 23 Apr 2020 00:50:30 +0000 (17:50 -0700)]
tests: read +/xilinx/cell_sim.v before xilinx_dsp test

4 years agoxilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
Eddie Hung [Thu, 23 Apr 2020 00:43:25 +0000 (17:43 -0700)]
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only

4 years agoverific: import enum attributes from verific
Eddie Hung [Thu, 23 Apr 2020 00:26:56 +0000 (17:26 -0700)]
verific: import enum attributes from verific

4 years agotest: ice40_dsp test to read +/ice40/cells_sim.v for default params
Eddie Hung [Wed, 22 Apr 2020 23:35:35 +0000 (16:35 -0700)]
test: ice40_dsp test to read +/ice40/cells_sim.v for default params

4 years agoxilinx: improve xilinx_dffopt message
Eddie Hung [Wed, 22 Apr 2020 20:59:56 +0000 (13:59 -0700)]
xilinx: improve xilinx_dffopt message

4 years agoxilinx: xilinx_dffopt to read cells_sim.v; fix test
Eddie Hung [Wed, 22 Apr 2020 20:57:09 +0000 (13:57 -0700)]
xilinx: xilinx_dffopt to read cells_sim.v; fix test

4 years agokernel: Cell::getParam() to throw exception again if not found
Eddie Hung [Wed, 22 Apr 2020 19:07:08 +0000 (12:07 -0700)]
kernel: Cell::getParam() to throw exception again if not found

As it did before #1945

4 years agoMerge pull request #1949 from YosysHQ/eddie/select_blackbox
Eddie Hung [Wed, 22 Apr 2020 22:35:05 +0000 (15:35 -0700)]
Merge pull request #1949 from YosysHQ/eddie/select_blackbox

select: do not select inside black-/white- boxes unless '=' prefix used

4 years agoMerge pull request #1983 from YosysHQ/eddie/use_default_param
Eddie Hung [Wed, 22 Apr 2020 21:37:27 +0000 (14:37 -0700)]
Merge pull request #1983 from YosysHQ/eddie/use_default_param

Cleanup use of hard-coded default parameters in light of #1945

4 years agoMerge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-opt
whitequark [Wed, 22 Apr 2020 20:29:08 +0000 (20:29 +0000)]
Merge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-opt

cxxrtl: keep the memory write queue sorted on insertion.

4 years agoUpdate passes/cmds/select.cc
Claire Wolf [Wed, 22 Apr 2020 19:31:32 +0000 (21:31 +0200)]
Update passes/cmds/select.cc

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
4 years agoMerge pull request #1969 from boqwxp/pool_emplace
Eddie Hung [Wed, 22 Apr 2020 19:10:42 +0000 (12:10 -0700)]
Merge pull request #1969 from boqwxp/pool_emplace

kernel: Add `pool` support for rvalue references and C++11 move semantics.

4 years agoCleanup use of hard-coded default parameters in light of #1945
Eddie Hung [Wed, 22 Apr 2020 19:02:30 +0000 (12:02 -0700)]
Cleanup use of hard-coded default parameters in light of #1945

4 years agocxxrtl: keep the memory write queue sorted on insertion.
Asu [Wed, 22 Apr 2020 18:50:13 +0000 (20:50 +0200)]
cxxrtl: keep the memory write queue sorted on insertion.

Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.

The Minerva SRAM SoC runs ~7% faster as a result.

4 years agoMerge pull request #1973 from YosysHQ/eddie/fix1966
Eddie Hung [Wed, 22 Apr 2020 17:19:30 +0000 (10:19 -0700)]
Merge pull request #1973 from YosysHQ/eddie/fix1966

tests: fix various/plugin.sh when PREFIX != /usr/local/share

4 years agotests: update select black/white-box tests
Eddie Hung [Wed, 22 Apr 2020 17:16:14 +0000 (10:16 -0700)]
tests: update select black/white-box tests

4 years agoselect: do not select black/white boxes by default, '=' prefix to do so
Eddie Hung [Wed, 22 Apr 2020 17:15:56 +0000 (10:15 -0700)]
select: do not select black/white boxes by default, '=' prefix to do so

4 years agoMerge pull request #1950 from YosysHQ/eddie/design_import
Eddie Hung [Wed, 22 Apr 2020 16:32:13 +0000 (09:32 -0700)]
Merge pull request #1950 from YosysHQ/eddie/design_import

design: -import to not count black/white-boxes as candidates for top

4 years agoyosys-config: spelling
Eddie Hung [Wed, 22 Apr 2020 15:30:03 +0000 (08:30 -0700)]
yosys-config: spelling

4 years agotests: use `yosys-config --datdir` instead of hard-coded
Eddie Hung [Wed, 22 Apr 2020 15:29:45 +0000 (08:29 -0700)]
tests: use `yosys-config --datdir` instead of hard-coded

4 years agopool: add emplace() function
Eddie Hung [Wed, 22 Apr 2020 15:14:07 +0000 (08:14 -0700)]
pool: add emplace() function

4 years agoMerge pull request #1976 from YosysHQ/dave/fix-sim-const
Claire Wolf [Wed, 22 Apr 2020 14:57:34 +0000 (16:57 +0200)]
Merge pull request #1976 from YosysHQ/dave/fix-sim-const

sim: Fix handling of constant-connected cell inputs at startup

4 years agoMerge pull request #1979 from whitequark/cxxrtl-go-faster
Claire Wolf [Wed, 22 Apr 2020 14:50:45 +0000 (16:50 +0200)]
Merge pull request #1979 from whitequark/cxxrtl-go-faster

cxxrtl: Gas gas gas! I'm gonna step on the gas! Tonight I'll fly!

4 years agocxxrtl: run edge detectors only once in eval().
whitequark [Wed, 22 Apr 2020 12:45:19 +0000 (12:45 +0000)]
cxxrtl: run edge detectors only once in eval().

As a result, Minerva SRAM SoC runs ~15% faster.

4 years agocxxrtl: add an unsupported knob for manipulating clock trees.
whitequark [Wed, 22 Apr 2020 01:15:27 +0000 (01:15 +0000)]
cxxrtl: add an unsupported knob for manipulating clock trees.

This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.

It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.

4 years agocxxrtl: use log_id() where appropriate. NFC.
whitequark [Tue, 21 Apr 2020 23:42:56 +0000 (23:42 +0000)]
cxxrtl: use log_id() where appropriate. NFC.

4 years agobugpoint: Don't remove modules or cells while iterating over them.
Marcelina Kościelnicka [Tue, 21 Apr 2020 17:56:28 +0000 (19:56 +0200)]
bugpoint: Don't remove modules or cells while iterating over them.

Reported by @ZirconiumX.

4 years agocxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.
whitequark [Tue, 21 Apr 2020 21:48:17 +0000 (21:48 +0000)]
cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.

If the annotations are not used, this commit does not alter semantics
at all, other than removing elision of outputs of black box cells.
(Elision of such outputs is expected to be too rare to have any
noticeable benefit, and the implementation was somewhat of a hack.)

The (* cxxrtl.comb *) annotation alters the semantics of the output
of the black box it is applied to such that, if the black box
converges immediately, no additional delta cycle is necessary to
propagate the computed combinatorial value upwards in hierarchy.

The (* cxxrtl.sync *) annotation alters the semantics of the output
of the black box it is applied to such as to remove any uses of
the black box by the wires connected to this output, and break false
feedback arcs arising from conservative modeling of dependencies of
the black box.

Although currently these attributes are only recognized on black
boxes, if separate compilation is added in the future, it could also
emit and consume them.

4 years agocxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
whitequark [Tue, 21 Apr 2020 18:46:36 +0000 (18:46 +0000)]
cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.

The attribute for this is called (* cxxrtl.edge *), and there is
a planned attribute (* cxxrtl.sync *) that would cause blackbox
cell outputs to be added to sync defs rather than comb defs.
Rename the edge detector related stuff to avoid confusion.

4 years agointel_alm: Documentation improvements
Dan Ravensloft [Tue, 21 Apr 2020 15:43:21 +0000 (16:43 +0100)]
intel_alm: Documentation improvements

4 years agokernel: Rename arguments to rvalue-reference-accepting functions.
Alberto Gonzalez [Tue, 21 Apr 2020 17:17:47 +0000 (17:17 +0000)]
kernel: Rename arguments to rvalue-reference-accepting functions.

4 years agowrite_json: dump default parameter values
Marcelina Kościelnicka [Thu, 16 Apr 2020 13:57:03 +0000 (15:57 +0200)]
write_json: dump default parameter values

Fixes #1823.

This will allow nextpnr to reuse the default value information already
present in yosys cells_sim.v and avoid duplicating (and probably
desyncing) this information.

4 years agoUse default parameter value in getParam
Marcelina Kościelnicka [Thu, 16 Apr 2020 19:48:21 +0000 (21:48 +0200)]
Use default parameter value in getParam

Fixes #1822.

4 years agohierarchy: Convert positional parameters to named.
Marcelina Kościelnicka [Thu, 16 Apr 2020 15:38:55 +0000 (17:38 +0200)]
hierarchy: Convert positional parameters to named.

Fixes #1821.

4 years agoilang, ast: Store parameter order and default value information.
Marcelina Kościelnicka [Thu, 16 Apr 2020 13:51:03 +0000 (15:51 +0200)]
ilang, ast: Store parameter order and default value information.

Fixes #1819, #1820.

4 years agoidict: Make iterator go forward.
Marcelina Kościelnicka [Thu, 16 Apr 2020 19:48:03 +0000 (21:48 +0200)]
idict: Make iterator go forward.

Previously, iterating over an idict returned its contents in reverse.

4 years agoMerge pull request #1971 from YosysHQ/claire/edifkeep
Claire Wolf [Tue, 21 Apr 2020 17:04:55 +0000 (19:04 +0200)]
Merge pull request #1971 from YosysHQ/claire/edifkeep

Ignore conflicting keep attributes, unless asked not to

4 years agoMerge pull request #1851 from YosysHQ/claire/bitselwrite
Claire Wolf [Tue, 21 Apr 2020 16:46:52 +0000 (18:46 +0200)]
Merge pull request #1851 from YosysHQ/claire/bitselwrite

Improved rewrite code for writing to bit slice

4 years agocxxrtl: use one delta cycle for immediately converging netlists.
whitequark [Tue, 21 Apr 2020 15:51:09 +0000 (15:51 +0000)]
cxxrtl: use one delta cycle for immediately converging netlists.

If it is statically known that eval() will converge in one delta
cycle (that is, the second commit() will always return `false`)
because the design contains no feedback or buffered wires, then
there is no need to run the second delta cycle at all.

After this commit, the case where eval() always converges immediately
is detected and the second delta cycle is omitted. As a result,
Minerva SRAM SoC runs ~25% faster.

4 years agocxxrtl: add -O6, a shortcut for running `proc; flatten`.
whitequark [Tue, 21 Apr 2020 15:33:12 +0000 (15:33 +0000)]
cxxrtl: add -O6, a shortcut for running `proc; flatten`.

People judge a compiler backend by the first impression, and
the metric they judge it for is speed. -O6 does severely impact
debuggability, but it provides equally massive gains in performance,
so use it by default.

4 years agocxxrtl: unbuffer module input wires.
whitequark [Tue, 21 Apr 2020 14:49:36 +0000 (14:49 +0000)]
cxxrtl: unbuffer module input wires.

Module input wires are never set by the module, so it is unnecessary
to buffer them. Although important for all inputs, this is especially
critical for clocks, since after this commit, hierarchy levels no
longer add delta cycles. As a result, Minerva SRAM SoC runs ~73%
faster when flattened, and ~264% (!!) faster when hierarchical.

4 years agocxxrtl: simplify generated edge detection logic.
whitequark [Tue, 21 Apr 2020 13:59:42 +0000 (13:59 +0000)]
cxxrtl: simplify generated edge detection logic.

This commit changes the way edge detectors are represented in
generated code from a variable that is set in commit() and reset in
eval() to a function that considers .curr and .next of the clock
wire. Behavior remains the same. Besides being simpler to generate
and providing more opportunities for optimization, this commit paves
way for unbuffering module inputs.

4 years agocxxrtl: localize wires with multiple comb drivers, too.
whitequark [Tue, 21 Apr 2020 13:33:42 +0000 (13:33 +0000)]
cxxrtl: localize wires with multiple comb drivers, too.

Before this commit, any wire that was not driven by an output port of
exactly one comb cell would not be localized, even if there were no
feedback arcs through that wire. This would cause the wire to become
buffered and require (often quite a few) extraneous delta cycles
during evaluation. To alleviate this problem, -O5 was running
`splitnets -driver`.

However, this solution was mistaken. Because `splitnets -driver`
followed by `opt_clean -purge` would produce more nets with multiple
drivers, it would have to be iterated to fixpoint. Moreover, even if
this was done, it would not be sufficient because `opt_clean -purge`
does not currently remove wires with the `\init` attribute (and it
is not desirable to remove such wires, since they correspond to
registers and may be useful for debugging).

The proper solution is to consider the condition in which a wire
may be localized. Specifically, if there are no feedback arcs through
this wire, and no part of the wire is driven by an output of a sync
cell, then the wire holds no state and is localizable.

After this commit, the original condition for not localizing a wire
is replaced by a check for any sync cell driving it. This makes it
unnecessary to run `splitnets -driver` in the majority of cases
to get a design with no buffered wires, and -O5 no longer includes
that pass. As a result, Minerva SRAM SoC no longer has any buffered
wires, and runs ~27% faster.

In addition, this commit prepares the flow graph for introduction
of sync outputs of black boxes.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
4 years agocxxrtl: detect buffered comb wires, not just feedback wires.
whitequark [Mon, 20 Apr 2020 16:44:51 +0000 (16:44 +0000)]
cxxrtl: detect buffered comb wires, not just feedback wires.

Any buffered combinatorial wires (including, as a subset, feedback
wires) will prevent the design from always converging in one delta
cycle. Before this commit, only feedback wires were detected. After
this commit, any buffered combinatorial wires, including feedback
wires, are detected.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
4 years agoAdd '=' selection pattern prefix for non-blackbox only patterns
Claire Wolf [Tue, 21 Apr 2020 12:23:24 +0000 (14:23 +0200)]
Add '=' selection pattern prefix for non-blackbox only patterns

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoImprove net priorities in EDIF back-end
Claire Wolf [Tue, 21 Apr 2020 10:35:25 +0000 (12:35 +0200)]
Improve net priorities in EDIF back-end

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agosim: Fix handling of constant-connected cell inputs at startup
David Shah [Tue, 21 Apr 2020 07:58:52 +0000 (08:58 +0100)]
sim: Fix handling of constant-connected cell inputs at startup

Signed-off-by: David Shah <dave@ds0.me>
4 years agoMerge pull request #1961 from whitequark/paramod-original-name
whitequark [Tue, 21 Apr 2020 01:43:20 +0000 (01:43 +0000)]
Merge pull request #1961 from whitequark/paramod-original-name

ast, rpc: record original name of $paramod\* as \hdlname attribute

4 years agotests: remove write_ilang
Eddie Hung [Mon, 20 Apr 2020 22:42:29 +0000 (15:42 -0700)]
tests: remove write_ilang

4 years agoMerge pull request #1975 from dh73/claire/bitselwrite
Eddie Hung [Mon, 20 Apr 2020 22:34:31 +0000 (15:34 -0700)]
Merge pull request #1975 from dh73/claire/bitselwrite

Adding tests to Claire/bitselwrite branch

4 years agoRemove '-ignore_unknown_cells' option from 'sat'
Eddie Hung [Mon, 20 Apr 2020 18:58:23 +0000 (11:58 -0700)]
Remove '-ignore_unknown_cells' option from 'sat'

4 years agoSimplify test case script
Eddie Hung [Mon, 20 Apr 2020 18:54:10 +0000 (11:54 -0700)]
Simplify test case script

4 years agoRemove ununsed files
Eddie Hung [Mon, 20 Apr 2020 18:53:48 +0000 (11:53 -0700)]
Remove ununsed files

4 years agoMerge pull request #1972 from YosysHQ/eddie/bug1970
Eddie Hung [Mon, 20 Apr 2020 18:39:13 +0000 (11:39 -0700)]
Merge pull request #1972 from YosysHQ/eddie/bug1970

 abc9_ops: -prep_lut to be more robust

4 years agoabc9: tolerate ABC nonzero exit code if output.aig; write before &mfs
Eddie Hung [Mon, 20 Apr 2020 18:26:11 +0000 (11:26 -0700)]
abc9: tolerate ABC nonzero exit code if output.aig; write before &mfs

Re-enable mfs for xilinx/ecp5 speculatively -- if it fails, use pre-mfs
result

4 years agoModifications of tests as per Eddie's request
diego [Mon, 20 Apr 2020 17:45:35 +0000 (12:45 -0500)]
Modifications of tests as per Eddie's request

4 years agoxilinx/ecp5: disable abc9's "&mfs" optimisation
Eddie Hung [Mon, 20 Apr 2020 17:30:10 +0000 (10:30 -0700)]
xilinx/ecp5: disable abc9's "&mfs" optimisation

Can sometimes fire an assertion, e.g. #1962

4 years agoabc9: -prep_lut to be more robust
Eddie Hung [Mon, 20 Apr 2020 16:39:35 +0000 (09:39 -0700)]
abc9: -prep_lut to be more robust

4 years agoabc9: add testcase reduced from #1970
Eddie Hung [Mon, 20 Apr 2020 16:38:29 +0000 (09:38 -0700)]
abc9: add testcase reduced from #1970

4 years agoIgnore conflicting keep attributes, unless asked not to. Fixes #1733
Claire Wolf [Mon, 20 Apr 2020 14:00:37 +0000 (16:00 +0200)]
Ignore conflicting keep attributes, unless asked not to. Fixes #1733

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #1964 from YosysHQ/claire/sformatf
Claire Wolf [Mon, 20 Apr 2020 12:51:40 +0000 (14:51 +0200)]
Merge pull request #1964 from YosysHQ/claire/sformatf

Extend support for format strings in Verilog front-end

4 years agoAdd rvalue-reference-accepting `entry_t` constructor for `pool`.
Alberto Gonzalez [Mon, 20 Apr 2020 05:37:10 +0000 (05:37 +0000)]
Add rvalue-reference-accepting `entry_t` constructor for `pool`.

4 years agoIn `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding...
Alberto Gonzalez [Mon, 20 Apr 2020 02:16:55 +0000 (02:16 +0000)]
In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding `insert()` method.

4 years agoMerge pull request #1967 from whitequark/cxxrtl-blackbox-attributes
whitequark [Sun, 19 Apr 2020 19:59:42 +0000 (19:59 +0000)]
Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributes

cxxrtl: provide attributes to black box factories, too

4 years agocxxrtl: provide attributes to black box factories, too.
whitequark [Sun, 19 Apr 2020 16:22:02 +0000 (16:22 +0000)]
cxxrtl: provide attributes to black box factories, too.

Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.

4 years agoExtend support for format strings in Verilog front-end
Claire Wolf [Sat, 18 Apr 2020 12:08:51 +0000 (14:08 +0200)]
Extend support for format strings in Verilog front-end

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #1963 from whitequark/cxxrtl-blackboxes
whitequark [Sat, 18 Apr 2020 09:21:14 +0000 (09:21 +0000)]
Merge pull request #1963 from whitequark/cxxrtl-blackboxes

cxxrtl: add support for simple and templated C++ black boxes

4 years agocxxrtl: add templated black box support.
whitequark [Sat, 18 Apr 2020 08:04:57 +0000 (08:04 +0000)]
cxxrtl: add templated black box support.

4 years agocxxrtl: make eval() and commit() inline in blackboxes.
whitequark [Sat, 18 Apr 2020 02:14:20 +0000 (02:14 +0000)]
cxxrtl: make eval() and commit() inline in blackboxes.

This change is a preparation for template blackboxes. It has no
effect on current generated code.

4 years agocxxrtl: add simple black box support.
whitequark [Fri, 17 Apr 2020 01:41:08 +0000 (01:41 +0000)]
cxxrtl: add simple black box support.

This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.

4 years agocxxrtl: use ID::X instead of ID(X). NFC.
whitequark [Wed, 15 Apr 2020 17:39:14 +0000 (17:39 +0000)]
cxxrtl: use ID::X instead of ID(X). NFC.

4 years agoast, rpc: record original name of $paramod\* as \hdlname attribute.
whitequark [Sat, 18 Apr 2020 03:43:15 +0000 (03:43 +0000)]
ast, rpc: record original name of $paramod\* as \hdlname attribute.

The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.

4 years agoMerge pull request #1955 from whitequark/cxxrtl-sync_always
whitequark [Fri, 17 Apr 2020 21:36:59 +0000 (21:36 +0000)]
Merge pull request #1955 from whitequark/cxxrtl-sync_always

cxxrtl: correctly handle `sync always` rules

4 years agoMerge pull request #1952 from boqwxp/add_edge_location
whitequark [Fri, 17 Apr 2020 18:57:00 +0000 (18:57 +0000)]
Merge pull request #1952 from boqwxp/add_edge_location

Verilog frontend: add source location in more parser rules

4 years agoWrong fixed value
diego [Fri, 17 Apr 2020 15:15:22 +0000 (10:15 -0500)]
Wrong fixed value

4 years agocxxrtl: correctly handle `sync always` rules.
whitequark [Fri, 17 Apr 2020 09:43:13 +0000 (09:43 +0000)]
cxxrtl: correctly handle `sync always` rules.

Fixes #1948.

4 years agoMerge pull request #1954 from YosysHQ/dave/fix-stdout-conflict
whitequark [Fri, 17 Apr 2020 09:07:49 +0000 (09:07 +0000)]
Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflict

qbfsat: Fix illegal use of 'stdout' identifier

4 years agoMerge pull request #1951 from whitequark/rtlil-string_attribute
whitequark [Fri, 17 Apr 2020 09:06:40 +0000 (09:06 +0000)]
Merge pull request #1951 from whitequark/rtlil-string_attribute

rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute

4 years agoqbfsat: Fix illegal use of 'stdout' identifier
David Shah [Fri, 17 Apr 2020 07:42:39 +0000 (08:42 +0100)]
qbfsat: Fix illegal use of 'stdout' identifier

Signed-off-by: David Shah <dave@ds0.me>
4 years agoSet Verilog source location for explicit blocks (`begin` ... `end`).
Alberto Gonzalez [Fri, 17 Apr 2020 06:23:03 +0000 (06:23 +0000)]
Set Verilog source location for explicit blocks (`begin` ... `end`).

4 years agoAdd Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
Alberto Gonzalez [Fri, 17 Apr 2020 06:16:59 +0000 (06:16 +0000)]
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.

4 years agoMerge pull request #1898 from boqwxp/locations
whitequark [Fri, 17 Apr 2020 02:27:13 +0000 (02:27 +0000)]
Merge pull request #1898 from boqwxp/locations

Verilog frontend: add location information to parsed constants