Steve Reinhardt [Sat, 30 Jan 2010 04:29:17 +0000 (20:29 -0800)]
scons: ignore blank lines in .slicc files
Steve Reinhardt [Sat, 30 Jan 2010 04:29:17 +0000 (20:29 -0800)]
ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
Steve Reinhardt [Sat, 30 Jan 2010 04:29:17 +0000 (20:29 -0800)]
ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
Steve Reinhardt [Sat, 30 Jan 2010 04:29:14 +0000 (20:29 -0800)]
ruby: get rid of obsolete, unused CustomTopology class.
Steve Reinhardt [Sat, 30 Jan 2010 04:29:14 +0000 (20:29 -0800)]
tests: added M5_TEST_PROGS environment variable
to allow override of global location for regression test binaries.
Brad Beckmann [Sat, 30 Jan 2010 04:29:14 +0000 (20:29 -0800)]
ruby: fix out_port declaration
Brad Beckmann [Sat, 30 Jan 2010 04:29:13 +0000 (20:29 -0800)]
ruby: Added message type check to OutPortDeclAST.py
Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
Derek Hower [Mon, 25 Jan 2010 17:53:06 +0000 (11:53 -0600)]
Automated merge with ssh://hg@m5sim.org/m5
Derek Hower [Mon, 25 Jan 2010 17:51:16 +0000 (11:51 -0600)]
config: changed default ruby config file for regression
Nathan Binkert [Sat, 23 Jan 2010 22:02:03 +0000 (14:02 -0800)]
build: need to include cstdio
Nathan Binkert [Sat, 23 Jan 2010 17:43:18 +0000 (09:43 -0800)]
style_hook: Fix the style hook
Re-enable it and update it for more modern versions of mercurial.
Derek Hower [Fri, 22 Jan 2010 23:23:21 +0000 (17:23 -0600)]
Automated merge with ssh://hg@m5sim.org/m5
Lisa Hsu [Thu, 21 Jan 2010 00:47:40 +0000 (16:47 -0800)]
copyrights: add copyright info to the files I added.
checkpoint-aggregator.py was written at UM so I added a UM copyright, agg_se.py was
written at AMD so I added the AMD copyright.
Lisa Hsu [Wed, 20 Jan 2010 06:03:44 +0000 (22:03 -0800)]
util: do checkpoint aggregation more cleanly, fix last changeset.
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
Derek Hower [Tue, 19 Jan 2010 23:17:19 +0000 (17:17 -0600)]
memtest differences from Derek's changes
Derek Hower [Tue, 19 Jan 2010 23:11:36 +0000 (17:11 -0600)]
ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
Derek Hower [Tue, 19 Jan 2010 21:48:12 +0000 (15:48 -0600)]
merge
Lisa Hsu [Mon, 18 Jan 2010 22:33:02 +0000 (14:33 -0800)]
Automated merge with ssh://hsul@localhost:4444//repo/m5
Lisa Hsu [Mon, 18 Jan 2010 22:30:31 +0000 (14:30 -0800)]
util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
Gabe Black [Sun, 17 Jan 2010 10:22:30 +0000 (02:22 -0800)]
SCons: Make --help reflect the arguments to scons.
The arguments were added to the global_sticky_vars Variables object after the
basic help text was generated. As a result, the "actual:" value wouldn't
reflect the arguments to scons and wouldn't really be the "actual" value used
by the build. This change fixes that by updating global_sticky_vars slightly
earlier.
Lisa Hsu [Tue, 12 Jan 2010 18:53:02 +0000 (10:53 -0800)]
cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.
Lisa Hsu [Tue, 12 Jan 2010 18:22:46 +0000 (10:22 -0800)]
since totalInstructions() is impl'ed by all the cpus, make it an abstract base class.
Lisa Hsu [Tue, 12 Jan 2010 18:17:19 +0000 (10:17 -0800)]
faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way.
Gabe Black [Sat, 2 Jan 2010 12:06:26 +0000 (07:06 -0500)]
MIPS: Update the stats of the RUBY version of the regressions.
Gabe Black [Thu, 31 Dec 2009 20:30:51 +0000 (15:30 -0500)]
MIPS: Update stats for updated initial environment.
Matt DeVuyst [Thu, 31 Dec 2009 20:30:51 +0000 (15:30 -0500)]
MIPS: Beef up process initialization.
Gabe Black [Thu, 31 Dec 2009 20:30:51 +0000 (15:30 -0500)]
MIPS: Implement the SE mode version of rdhwr.
Gabe Black [Thu, 31 Dec 2009 20:30:51 +0000 (15:30 -0500)]
MIPS: Fix decoding of the rdhwr instruction.
Gabe Black [Thu, 31 Dec 2009 20:30:50 +0000 (15:30 -0500)]
MIPS: Implement the set_thread_area system call.
Gabe Black [Thu, 31 Dec 2009 20:30:50 +0000 (15:30 -0500)]
MIPS: Create an artificial control register to hold the thread pointer.
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
Gabe Black [Thu, 31 Dec 2009 20:30:50 +0000 (15:30 -0500)]
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
Gabe Black [Mon, 21 Dec 2009 22:59:40 +0000 (14:59 -0800)]
MIPS: Add missing syscall slots.
These are all after the existing ones, suggesting they were added after the
original list was created.
Soumyaroop Roy [Sun, 20 Dec 2009 21:03:23 +0000 (15:03 -0600)]
Alpha: Implement MVI and remaining BWX instructions.
Gabe Black [Sat, 19 Dec 2009 09:50:06 +0000 (01:50 -0800)]
X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.
Gabe Black [Sat, 19 Dec 2009 09:49:34 +0000 (01:49 -0800)]
X86: Record the memory mode when building an X86 system.
Gabe Black [Sat, 19 Dec 2009 09:48:31 +0000 (01:48 -0800)]
X86: Add a common named flag for signed media operations.
Gabe Black [Sat, 19 Dec 2009 09:48:07 +0000 (01:48 -0800)]
X86: Create a common flag with a name to indicate high multiplies.
Gabe Black [Sat, 19 Dec 2009 09:47:30 +0000 (01:47 -0800)]
X86: Create a common flag with a name to indicate scalar media instructions.
Derek Hower [Fri, 4 Dec 2009 19:12:40 +0000 (13:12 -0600)]
ruby: cleaned up ruby-lang configuration
Brad Beckmann [Thu, 19 Nov 2009 02:00:41 +0000 (18:00 -0800)]
m5: refreshed the ruby memtest regression stats
Brad Beckmann [Thu, 19 Nov 2009 00:34:33 +0000 (16:34 -0800)]
Resurrection of the CMP token protocol to GEM5
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
m5: improvements to the ruby_fs.py file
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: removed the chip pointer from MessageBuffer
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: added error message to isinstance check
Added error message when a symbol is not an instance of a particular expected
type.
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: Added boolean to State Machine parameters
* * *
ruby: Removed primitive .hh includes
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
m5: Added the default m5out directory to the hg ignore list
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: The persistent table files from GEMS
These files are need by the MOESI_CMP_token protocol.
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: MOESI hammer support for DMA reads and writes
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: Added a memory controller feature to MOESI hammer
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: Hammer ruby configuration support
Brad Beckmann [Thu, 19 Nov 2009 00:34:32 +0000 (16:34 -0800)]
ruby: Changes necessary to get the hammer protocol to work in GEM5
Brad Beckmann [Thu, 19 Nov 2009 00:34:31 +0000 (16:34 -0800)]
ruby: added the original hammer protocols from old ruby
Brad Beckmann [Thu, 19 Nov 2009 00:34:31 +0000 (16:34 -0800)]
ruby: returns the number of LLC needed for broadcast
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
Brad Beckmann [Thu, 19 Nov 2009 00:34:31 +0000 (16:34 -0800)]
ruby: cache configuration fix to use bytes
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
Brad Beckmann [Thu, 19 Nov 2009 00:33:35 +0000 (16:33 -0800)]
ruby: fix CacheMemory destructor
Brad Beckmann [Thu, 19 Nov 2009 00:33:35 +0000 (16:33 -0800)]
ruby: split CacheMemory.hh into a .hh and a .cc
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: Added default names to message buffers
Added default names to message buffers created by the simple network.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: slicc method error fix
Added error message when a method call is not supported by an object.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: slicc action error fix
Small fix to the State Machine error message when duplicate actions are defined.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: slicc state machine error fixes
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: Removed unused action z_stall
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: Added option to take a checkpoint at the end of simulation
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: Fixed bug in atomic cpu destructor
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: fixed dma mi example to work with multiple dma ports
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: removed master and slave deletions.
The unresolved destructor call caused a seg fault when called.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: fixed destructor to deschedule the tickEvent and event
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: getPort function fix
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: Fixed Directory memory destructor
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: Moved profile option since Simulation depends on it.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
m5: Added isValidSrc and isValidDest calls to packet.hh
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: Added error check for openning the ruby config file
Brad Beckmann [Wed, 18 Nov 2009 21:55:58 +0000 (13:55 -0800)]
ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
Brad Beckmann [Wed, 18 Nov 2009 21:55:57 +0000 (13:55 -0800)]
ruby: Added more info to bridge error message
Brad Beckmann [Wed, 18 Nov 2009 21:55:57 +0000 (13:55 -0800)]
ruby: Ruby 64-bit address output fixes.
Brad Beckmann [Wed, 18 Nov 2009 21:55:57 +0000 (13:55 -0800)]
ruby: Ruby destruction fix.
Brad Beckmann [Wed, 18 Nov 2009 21:55:57 +0000 (13:55 -0800)]
ruby: Ruby debug print fixes.
Brad Beckmann [Wed, 18 Nov 2009 21:55:57 +0000 (13:55 -0800)]
ruby: Ruby memtest python script.
Derek Hower [Wed, 18 Nov 2009 17:55:42 +0000 (11:55 -0600)]
Added tag Calvin_Submission for changeset
5de565c4b7bd
Derek Hower [Wed, 18 Nov 2009 17:55:30 +0000 (11:55 -0600)]
ruby: added sequencer stats to track what requests are waiting on
Derek Hower [Wed, 18 Nov 2009 17:53:43 +0000 (11:53 -0600)]
ruby: turned off randomization by default, turned on memory controller random arbitrate
Ali Saidi [Wed, 18 Nov 2009 00:02:09 +0000 (18:02 -0600)]
ARM: Begin implementing CP15
Ali Saidi [Wed, 18 Nov 2009 00:02:08 +0000 (18:02 -0600)]
ARM: Differentiate between LDM exception return and LDM user regs.
Ali Saidi [Wed, 18 Nov 2009 00:02:08 +0000 (18:02 -0600)]
ARM: Boilerplate full-system code.
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
Ali Saidi [Mon, 16 Nov 2009 17:37:03 +0000 (11:37 -0600)]
imported patch isa_fixes2.diff
Gabe Black [Sun, 15 Nov 2009 08:23:14 +0000 (00:23 -0800)]
ARM: Make the exception return form of ldm restore CPSR.
Gabe Black [Sun, 15 Nov 2009 08:15:42 +0000 (00:15 -0800)]
ARM: Create a new type of load uop that restores spsr into cpsr.
Gabe Black [Sun, 15 Nov 2009 05:03:10 +0000 (21:03 -0800)]
ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in it.
Gabe Black [Sun, 15 Nov 2009 04:57:59 +0000 (20:57 -0800)]
ARM: Switch the immediate and register versions of msr.
These were accidently transposed. This change straightens them out.
Gabe Black [Sun, 15 Nov 2009 03:22:30 +0000 (19:22 -0800)]
ARM: Fix up the implmentation of the msr instruction.
Gabe Black [Sun, 15 Nov 2009 03:22:30 +0000 (19:22 -0800)]
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
Gabe Black [Sun, 15 Nov 2009 03:22:30 +0000 (19:22 -0800)]
ARM: Add a bitfield to indicate if an immediate should be used.
Gabe Black [Sun, 15 Nov 2009 03:22:30 +0000 (19:22 -0800)]
ARM: Write some functions to write to the CPSR and SPSR for instructions.
Gabe Black [Sun, 15 Nov 2009 03:22:29 +0000 (19:22 -0800)]
ARM: Fix up the implmentation of the mrs instruction.
Gabe Black [Sun, 15 Nov 2009 03:22:29 +0000 (19:22 -0800)]
ARM: More accurately describe the effects of using the control operands.
Gabe Black [Sun, 15 Nov 2009 03:22:29 +0000 (19:22 -0800)]
ARM: Hook up the moded versions of the SPSR.
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
Ali Saidi [Sat, 14 Nov 2009 17:49:01 +0000 (11:49 -0600)]
SE: Fix SE mode OS X compilation.
Ali Saidi [Sat, 14 Nov 2009 17:25:00 +0000 (11:25 -0600)]
ARM: Move around decoder to properly decode CP15
Derek Hower [Fri, 13 Nov 2009 15:45:23 +0000 (09:45 -0600)]
ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size
Derek Hower [Fri, 13 Nov 2009 15:44:51 +0000 (09:44 -0600)]
ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer