mesa.git
9 years agoi965/fs: Import image memory offset calculation code.
Francisco Jerez [Wed, 22 Apr 2015 13:44:18 +0000 (16:44 +0300)]
i965/fs: Import image memory offset calculation code.

Define a function to calculate the memory address of the image
location given by a vector of coordinates.  This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and swizzling.  They are still useful
because typed surface reads don't support any 64 or 128-bit formats on
IVB, and they don't support any 128-bit formats on HSW and BDW.

The tiling algorithm is implemented based on a number of parameters
which are passed in as uniforms and determine whether the surface
layout is X-tiled, Y-tiled or untiled.  This allows binding surfaces
of different tiling layouts to the pipeline without recompiling the
program.

v2: Drop VEC4 suport.
v3: Rebase.
v4: Add plenty of comments (Jason).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Import image access validity checks.
Francisco Jerez [Wed, 22 Apr 2015 13:43:51 +0000 (16:43 +0300)]
i965/fs: Import image access validity checks.

These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results.  Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB and untyped messages elsewhere) we need to
implement it in software to work around lacking hardware support.

v2: Drop VEC4 suport.
v3: Rebase.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Define implementation constants for ARB_shader_image_load_store.
Francisco Jerez [Sat, 23 Nov 2013 00:00:33 +0000 (16:00 -0800)]
i965: Define implementation constants for ARB_shader_image_load_store.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
v2: Drop VS support pre-Gen8, drop GS support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
Francisco Jerez [Mon, 9 Feb 2015 19:04:53 +0000 (21:04 +0200)]
i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.

v2: Store early fragment test mode in brw_wm_prog_data instead of
    getting it from core mesa data structures (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/gen7-8: Poke the 3DSTATE UAV access enable bits.
Francisco Jerez [Mon, 13 Jul 2015 11:21:07 +0000 (14:21 +0300)]
i965/gen7-8: Poke the 3DSTATE UAV access enable bits.

v2: Set the PS UAV-only bit on HSW (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/gen7: Enable fragment shader dispatch if the program has image uniforms.
Francisco Jerez [Tue, 3 Feb 2015 15:14:10 +0000 (17:14 +0200)]
i965/gen7: Enable fragment shader dispatch if the program has image uniforms.

Shaders with image uniforms may have side effects.  Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.

v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
    has image uniforms instead of checking core mesa data structures
    (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Hook up image state upload.
Francisco Jerez [Mon, 20 Jul 2015 14:13:17 +0000 (17:13 +0300)]
i965: Hook up image state upload.

v2: Add CS support.  Move the image_params array back to
    brw_stage_prog_data.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965: Reserve enough parameter entries for all image uniforms used in the program.
Francisco Jerez [Mon, 13 Jul 2015 14:19:29 +0000 (17:19 +0300)]
i965: Reserve enough parameter entries for all image uniforms used in the program.

v2: Add CS support.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965: Define and initialize image parameter structure.
Francisco Jerez [Wed, 21 Jan 2015 15:34:49 +0000 (17:34 +0200)]
i965: Define and initialize image parameter structure.

This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes.  All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass.  size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too.  surface_idx
is always used.

v2: Add CS support.  Move the image_params array back to
    brw_stage_prog_data.
v3: Improve documentation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965: Implement surface state set-up for shader images.
Francisco Jerez [Sat, 2 May 2015 13:58:24 +0000 (16:58 +0300)]
i965: Implement surface state set-up for shader images.

v2: Add SKL support.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Fix brw_memory_barrier() for SKL.
Francisco Jerez [Tue, 12 May 2015 12:56:54 +0000 (15:56 +0300)]
i965: Fix brw_memory_barrier() for SKL.

This works as-is on SKL, only the assertion needs to be relaxed.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
Francisco Jerez [Tue, 12 May 2015 13:10:07 +0000 (16:10 +0300)]
i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoglsl: Add missing spec quote about atomic counter in structs
Timothy Arceri [Sun, 9 Aug 2015 04:44:30 +0000 (14:44 +1000)]
glsl: Add missing spec quote about atomic counter in structs

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
9 years agoradeonsi: add new OLAND pci id
Alex Deucher [Mon, 10 Aug 2015 19:35:21 +0000 (15:35 -0400)]
radeonsi: add new OLAND pci id

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
9 years agonouveau: no need to do tnl wakeup, state updates are always hooked up
Ilia Mirkin [Mon, 10 Aug 2015 21:41:36 +0000 (17:41 -0400)]
nouveau: no need to do tnl wakeup, state updates are always hooked up

A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
9 years agoi965/fs: Make resolve_source_modifiers consistent with the vec4 version
Jason Ekstrand [Mon, 10 Aug 2015 18:52:50 +0000 (11:52 -0700)]
i965/fs: Make resolve_source_modifiers consistent with the vec4 version

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4_visitor: Make some function arguments const references
Jason Ekstrand [Mon, 10 Aug 2015 18:48:14 +0000 (11:48 -0700)]
i965/vec4_visitor: Make some function arguments const references

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Don't do redundant RA setup on IVB+
Jason Ekstrand [Fri, 31 Jul 2015 15:36:35 +0000 (08:36 -0700)]
i965/fs: Don't do redundant RA setup on IVB+

Acked-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Use dispatch_width instead of reg_width in alloc_reg_sets
Jason Ekstrand [Fri, 31 Jul 2015 15:35:57 +0000 (08:35 -0700)]
i965/fs: Use dispatch_width instead of reg_width in alloc_reg_sets

reg_width is kind of an outdated concept.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agora: Delete the conflict lists in ra_set_finalize
Jason Ekstrand [Fri, 31 Jul 2015 03:53:04 +0000 (20:53 -0700)]
ra: Delete the conflict lists in ra_set_finalize

They are never used after the set is finalized so there's no reason to keep
them around.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agora: Refactor ra_set_finalize
Jason Ekstrand [Fri, 31 Jul 2015 03:49:22 +0000 (20:49 -0700)]
ra: Refactor ra_set_finalize

All this commit does is change an early return to an if with an else
clause.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4_nir: Properly handle integer multiplies on BDW+
Jason Ekstrand [Mon, 3 Aug 2015 22:21:59 +0000 (15:21 -0700)]
i965/vec4_nir: Properly handle integer multiplies on BDW+

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4_nir: Do boolean source modifier resolves on BDW+
Jason Ekstrand [Mon, 3 Aug 2015 21:37:41 +0000 (14:37 -0700)]
i965/vec4_nir: Do boolean source modifier resolves on BDW+

On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
a boolean negate and not an integer negate.  However, NIR's soruce
modifiers are the integer version.  We have to resolve it with a MOV prior
to emitting the actual instruction.  This is basically the same thing we do
in the FS backend.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4-nir: Handle boolean resolvese on ILK-
Jason Ekstrand [Mon, 3 Aug 2015 17:00:38 +0000 (10:00 -0700)]
i965/vec4-nir: Handle boolean resolvese on ILK-

The analysis code was already there and running, we just weren't doing
anything with the result of it yet.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Don't mark bany or ball instructions for resolve
Jason Ekstrand [Mon, 3 Aug 2015 23:25:18 +0000 (16:25 -0700)]
i965/nir: Don't mark bany or ball instructions for resolve

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Use nir_op_info.output_type for determining when to resolve
Jason Ekstrand [Mon, 3 Aug 2015 21:12:35 +0000 (14:12 -0700)]
i965/nir: Use nir_op_info.output_type for determining when to resolve

Previously, we were explicitly listing every instruction that needs a
resolve.  However, those instructions were precicely the ones that returned
booleans so there's no reason why we shouldn't just have that check.  Also,
all of the reduction opcodes such as bany and ball were missing so it
didn't properly flag stuff on vec4.  If an opcode gets added in the future
that returns a bool but doesn't need a resolve, we can special-case that.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agomesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unorm
Jason Ekstrand [Mon, 10 Aug 2015 05:03:00 +0000 (22:03 -0700)]
mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unorm

This better ensures that the src_bits == dst_bits case gets optimized away.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agogallium/radeon: add a debug flag not to use write combining (v2)
Marek Olšák [Sun, 2 Aug 2015 14:22:43 +0000 (16:22 +0200)]
gallium/radeon: add a debug flag not to use write combining (v2)

v2: just clear the flag before the allocation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agofreedreno/a4xx: add s8/z32/z32_s8x24 support
Rob Clark [Wed, 5 Aug 2015 22:14:49 +0000 (18:14 -0400)]
freedreno/a4xx: add s8/z32/z32_s8x24 support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: update generated headers
Rob Clark [Wed, 5 Aug 2015 18:21:06 +0000 (14:21 -0400)]
freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a4xx: fix vpsrepl for blit shaders
Rob Clark [Sun, 9 Aug 2015 13:03:25 +0000 (09:03 -0400)]
freedreno/a4xx: fix vpsrepl for blit shaders

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a4xx: clear cached fp when switching blit prog
Rob Clark [Mon, 10 Aug 2015 11:11:56 +0000 (07:11 -0400)]
freedreno/a4xx: clear cached fp when switching blit prog

For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore.  But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a3xx: clear cached fp when switching blit prog
Rob Clark [Sun, 9 Aug 2015 12:38:25 +0000 (08:38 -0400)]
freedreno/a3xx: clear cached fp when switching blit prog

For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore.  But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agomesa/es3.1: Allow Multisampled FrameBufferTextures
Marta Lofstedt [Mon, 10 Aug 2015 10:48:11 +0000 (13:48 +0300)]
mesa/es3.1: Allow Multisampled FrameBufferTextures

GLES 3.1 must be allowed to use multisampled framebuffer textures.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agomesa/es3.1: Pass sample count check for multisampled textures
Marta Lofstedt [Mon, 15 Jun 2015 11:50:21 +0000 (13:50 +0200)]
mesa/es3.1: Pass sample count check for multisampled textures

v3 : Removed space in comment.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agomesa: clear existing swizzle info before bitwise-OR
Oded Gabbay [Tue, 4 Aug 2015 18:39:32 +0000 (21:39 +0300)]
mesa: clear existing swizzle info before bitwise-OR

This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.

v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoutil: Use LONG_MAX instead of LONG_BIT.
Jose Fonseca [Sun, 9 Aug 2015 21:36:37 +0000 (22:36 +0100)]
util: Use LONG_MAX instead of LONG_BIT.

More portable.  Based on Roland Scheidegger's idea.

Tested with roundevent_test on Linux, MinGW, and MSVC.

https://bugs.freedesktop.org/show_bug.cgi?id=91591

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoscons: Build roundevent_test.
Jose Fonseca [Sun, 9 Aug 2015 10:55:28 +0000 (11:55 +0100)]
scons: Build roundevent_test.

Reviewed-by: Roland Scheidegger <sroland@vmware.co>
9 years agoutil: Cope with LONG_BIT not being defined on Windows.
Jose Fonseca [Sun, 9 Aug 2015 10:25:41 +0000 (11:25 +0100)]
util: Cope with LONG_BIT not being defined on Windows.

Neither MSVC nor MinGW defines LONG_BIT.  For MSVC this was not a problem as
it doesn't define __x86_64__ macro (it's GCC specific.)

However on Windows long type is guaranteed to be 32bits.

Also add an #error, as GCC will just warn, not throw any error, when no
value is returned.

Trivial.

9 years agogallium: GCC 4.9 allows to include tmmintrin.h without -msse3.
Jose Fonseca [Sun, 9 Aug 2015 10:21:03 +0000 (11:21 +0100)]
gallium: GCC 4.9 allows to include tmmintrin.h without -msse3.

Fixes build with MinGW x86_64 build with GCC 4.9, due to conflicting
definition _mm_shuffle_epi8 of u_sse.h and system headers.

Trivial.

9 years agoutil: Rename PURE to ATTRIBUTE_PURE.
Jose Fonseca [Fri, 7 Aug 2015 12:07:40 +0000 (13:07 +0100)]
util: Rename PURE to ATTRIBUTE_PURE.

To avoid collission with windows.h's PURE macro.

We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoegl/x11: Fix driver_name acquisition
Boyan Ding [Sat, 8 Aug 2015 09:23:28 +0000 (17:23 +0800)]
egl/x11: Fix driver_name acquisition

We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.

Fixes: 45e110bad9d (egl/x11: trust our loader over the xserver for the
drivername)

Reported-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoi965/skl: (trivial) Remove invalid comment about thread counts
Ben Widawsky [Fri, 7 Aug 2015 20:46:30 +0000 (13:46 -0700)]
i965/skl: (trivial) Remove invalid comment about thread counts

This should have been a part of:
commit 7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Wed Jul 29 12:35:24 2015 -0700

    i965/skl: Add production thread counts and URB size

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965: Fix HW binding tables editing
Chris Wilson [Wed, 5 Aug 2015 12:58:46 +0000 (13:58 +0100)]
i965: Fix HW binding tables editing

Since the introduction of new gl_shader_stages in

commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date:   Fri Mar 7 10:19:09 2014 +0100

    mesa: add tessellation shader enums

the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoegl/dri2: Fix include path of u_atomic.h introduced e7e29189
Alexander von Gluck IV [Fri, 7 Aug 2015 17:55:40 +0000 (12:55 -0500)]
egl/dri2: Fix include path of u_atomic.h introduced e7e29189

This was causing a failure to build on SCons due to a missing
-Isrc/egl. Instead of adding in that path, lets just -Isrc/
and include "utils/u_atomic.h".

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoegl/x11: don't crash if dri2_dpy->conn is NULL
Emil Velikov [Fri, 7 Aug 2015 18:20:48 +0000 (19:20 +0100)]
egl/x11: don't crash if dri2_dpy->conn is NULL

Identical to commit 60e9c35b3a0(egl/x11: bail out if we cannot fetch
the xcb connection) but for the swrast codepath.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoegl/x11: auth with xserver before attempting to open the dri module
Emil Velikov [Wed, 29 Jul 2015 16:19:07 +0000 (17:19 +0100)]
egl/x11: auth with xserver before attempting to open the dri module

No real change, apart from keeping the calls to the underlying winsys
(x11) next to each other. Just like platform_wayland.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoegl/x11: trust our loader over the xserver for the drivername
Emil Velikov [Wed, 29 Jul 2015 16:19:06 +0000 (17:19 +0100)]
egl/x11: trust our loader over the xserver for the drivername

This is a port of commit 7bd95ec437a(dri2: Trust our own driver name
lookup over the server's.) from glx/dri2.

v2: Add newline between code and multiline comment. (Matt)

Cc: Julien Isorce <julien.isorce@gmail.com>
Reported-by: Julien Isorce <julien.isorce@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoegl/x11: open the device from within dri2_x11_connect()
Emil Velikov [Wed, 29 Jul 2015 16:19:05 +0000 (17:19 +0100)]
egl/x11: open the device from within dri2_x11_connect()

Allows us, with the next commit, to use alternative driver_name rather
than the one from xserver.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoegl/x11: fetch the device_name prior to driver_name
Emil Velikov [Wed, 29 Jul 2015 16:19:04 +0000 (17:19 +0100)]
egl/x11: fetch the device_name prior to driver_name

With the follow up commits we're about to further reshuffle things. Thus
we'll honour our our driver_name lookup (src/loader), and use the one
provided by xserver as a fall-back.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoegl/x11: remove dri2_dpy->conn checks
Emil Velikov [Wed, 29 Jul 2015 16:19:03 +0000 (17:19 +0100)]
egl/x11: remove dri2_dpy->conn checks

If the connection is NULL we won't be able to get here.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoegl/x11: bail out if we cannot fetch the xcb connection
Emil Velikov [Wed, 29 Jul 2015 16:19:02 +0000 (17:19 +0100)]
egl/x11: bail out if we cannot fetch the xcb connection

The documentation of xcb_connection_has_error() does not mention
what will happen, if NULL is fed to the function.

Upon closer look (props to Matt), it seems that we'll crash as the
implementation dereferences conn.

This will also allow us to remove the dri2_dpy->conn checking with the
next commit.

v2: Reword commit message as per Matt's findings.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agovc4: add missing nir include, to fix the build
Emil Velikov [Fri, 17 Jul 2015 11:52:27 +0000 (12:52 +0100)]
vc4: add missing nir include, to fix the build

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agovc4: automake: remove unused include
Emil Velikov [Fri, 17 Jul 2015 11:41:24 +0000 (12:41 +0100)]
vc4: automake: remove unused include

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoclover: Stub missing CL 1.2 functions.
Serge Martin (EdB) [Fri, 7 Aug 2015 08:40:31 +0000 (10:40 +0200)]
clover: Stub missing CL 1.2 functions.

As sugested by Tom a long time ago
and in order to be able to create Piglit tests

v2:
replace NOT_SUPPORTED_BY_CL_1_1 macro with an inline function
remove extra space in clLinkProgram arg

v3:
use __func__

v4:
back to a macro, it make more sense to use it with __func__

[ Francisco Jerez: Rename to CLOVER_NOT_SUPPORTED_UNTIL and pass the
  minimum API version required by the entry point so the error
  messages don't become stale when support for additional CL versions
  is introduced. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agomesa: NULL check InfoLog
Marta Lofstedt [Tue, 23 Jun 2015 11:03:13 +0000 (13:03 +0200)]
mesa: NULL check InfoLog

When a program is compiled, but linking failed the sh->InfoLog
could be NULL. This is expoloited by OpenGL ES 3.1 conformance tests.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costs
Iago Toral Quiroga [Tue, 4 Aug 2015 08:06:41 +0000 (10:06 +0200)]
i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costs

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agoi965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructions
Iago Toral Quiroga [Fri, 31 Jul 2015 12:36:30 +0000 (14:36 +0200)]
i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructions

The dst is always written, in this case the predicate is only used to select
the value to write, so if we are spilling the dst we always want to write
whatever value we selected to scratch.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agoglsl: remove stage ref generation for transform feedback
Timothy Arceri [Wed, 5 Aug 2015 11:05:52 +0000 (21:05 +1000)]
glsl: remove stage ref generation for transform feedback

Stage ref cannot be queried for transform feedback.

Also simplify the build_stageref function by passing the
correct mode for uniforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agowinsys/radeon: add a specific error message for cs_submit -> -ENOMEM
Marek Olšák [Wed, 15 Jul 2015 19:14:24 +0000 (21:14 +0200)]
winsys/radeon: add a specific error message for cs_submit -> -ENOMEM

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
9 years agowinsys/radeon: add an interface for contexts
Marek Olšák [Thu, 30 Apr 2015 14:07:12 +0000 (16:07 +0200)]
winsys/radeon: add an interface for contexts

Same idea as in libdrm_amdgpu.

A command stream can only be created for a specific context and it's always
submitted to that context.

This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)

Reviewed-by: Christian König <christian.koenig@amd.com>
9 years agogallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
Marek Olšák [Thu, 6 Aug 2015 21:41:38 +0000 (23:41 +0200)]
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface

The timeout parameter covers both cases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
9 years agoradeonsi: rename enable_s3tc -> enable_compressed_formats
Marek Olšák [Mon, 3 Aug 2015 19:43:36 +0000 (21:43 +0200)]
radeonsi: rename enable_s3tc -> enable_compressed_formats

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
9 years agogallium/radeon: add DRM and LLVM version to the renderer string
Marek Olšák [Sun, 19 Jul 2015 22:15:59 +0000 (00:15 +0200)]
gallium/radeon: add DRM and LLVM version to the renderer string

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi: always flush framebuffer caches at the beginning of IBs
Marek Olšák [Thu, 16 Jul 2015 12:40:00 +0000 (14:40 +0200)]
radeonsi: always flush framebuffer caches at the beginning of IBs

better safe than sorry

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
9 years agoradeonsi: don't count the exact needed CS space if the CS is large enough
Marek Olšák [Sat, 27 Jun 2015 12:49:34 +0000 (14:49 +0200)]
radeonsi: don't count the exact needed CS space if the CS is large enough

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
9 years agoradeonsi: don't crash when cleaning up after an incomplete context
Marek Olšák [Wed, 6 May 2015 17:34:09 +0000 (19:34 +0200)]
radeonsi: don't crash when cleaning up after an incomplete context

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
9 years agoi965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.
Matt Turner [Thu, 6 Aug 2015 17:59:15 +0000 (10:59 -0700)]
i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.

Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965: Correct a mistake that always forced texture tiling.
Matt Turner [Wed, 5 Aug 2015 05:58:08 +0000 (22:58 -0700)]
i965: Correct a mistake that always forced texture tiling.

Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

The relevant enum values are

   MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5
   MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6
   MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
                                    MIPTREE_LAYOUT_ALLOC_XTILED
   MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7

so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can
never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR.

The enum this replaced was

   enum intel_miptree_tiling_mode {
      INTEL_MIPTREE_TILING_ANY,
      INTEL_MIPTREE_TILING_Y,
      INTEL_MIPTREE_TILING_NONE,
   };

where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the
unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine
MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965: Request a miptree with no tiling intel_miptree_map_blit().
Matt Turner [Thu, 6 Aug 2015 01:51:24 +0000 (18:51 -0700)]
i965: Request a miptree with no tiling intel_miptree_map_blit().

Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoradeonsi: add a HUD query showing the number of shaders created
Marek Olšák [Sun, 2 Aug 2015 19:12:18 +0000 (21:12 +0200)]
radeonsi: add a HUD query showing the number of shaders created

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi: add a HUD query showing the number of compiler invocations
Marek Olšák [Sun, 2 Aug 2015 14:57:39 +0000 (16:57 +0200)]
radeonsi: add a HUD query showing the number of compiler invocations

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: display cumulative results for some driver queries
Marek Olšák [Sun, 2 Aug 2015 15:28:20 +0000 (17:28 +0200)]
gallium/radeon: display cumulative results for some driver queries

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: switch the buffer-wait-time query to microseconds
Marek Olšák [Sun, 2 Aug 2015 15:47:38 +0000 (17:47 +0200)]
gallium/radeon: switch the buffer-wait-time query to microseconds

This display the units in the HUD.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: change some driver query types to Hz
Marek Olšák [Sun, 2 Aug 2015 15:09:01 +0000 (17:09 +0200)]
gallium/radeon: change some driver query types to Hz

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/hud: automatically print % if max_value == 100
Marek Olšák [Sun, 2 Aug 2015 16:11:55 +0000 (18:11 +0200)]
gallium/hud: automatically print % if max_value == 100

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/hud: fix printing % next to panes
Marek Olšák [Sun, 2 Aug 2015 16:11:09 +0000 (18:11 +0200)]
gallium/hud: fix printing % next to panes

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/hud: replace assertions with clamping the unit index
Marek Olšák [Sun, 2 Aug 2015 16:00:57 +0000 (18:00 +0200)]
gallium/hud: replace assertions with clamping the unit index

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium,hud: allow displaying cumulative values instead of average
Marek Olšák [Sun, 2 Aug 2015 15:24:30 +0000 (17:24 +0200)]
gallium,hud: allow displaying cumulative values instead of average

The cumulative value is useful for queries like the number of shader
compilations.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/hud: fix printing byte units
Marek Olšák [Sun, 2 Aug 2015 15:08:29 +0000 (17:08 +0200)]
gallium/hud: fix printing byte units

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium,hud: add support for Hz units in driver queries
Marek Olšák [Sun, 2 Aug 2015 15:06:17 +0000 (17:06 +0200)]
gallium,hud: add support for Hz units in driver queries

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi: before storing tess levels, load them from LDS instead of temporary
Marek Olšák [Sun, 2 Aug 2015 23:34:32 +0000 (01:34 +0200)]
radeonsi: before storing tess levels, load them from LDS instead of temporary

Also use only one store if stride <= 4.
All the fetches from and stores to temporaries can be removed now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91461

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agowinsys/radeon: loosen up the requirements for how much memory IBs can use
Marek Olšák [Sun, 2 Aug 2015 20:01:25 +0000 (22:01 +0200)]
winsys/radeon: loosen up the requirements for how much memory IBs can use

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: always use the llvm. prefix in intrinsic names
Marek Olšák [Fri, 31 Jul 2015 15:26:08 +0000 (17:26 +0200)]
gallium/radeon: always use the llvm. prefix in intrinsic names

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
9 years agoradeon/winsys: increase the IB size for VM
Marek Olšák [Fri, 31 Jul 2015 09:45:13 +0000 (11:45 +0200)]
radeon/winsys: increase the IB size for VM

Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: allow the winsys to choose the IB size
Marek Olšák [Sat, 27 Jun 2015 12:19:41 +0000 (14:19 +0200)]
gallium/radeon: allow the winsys to choose the IB size

Picked from the amdgpu branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agogallium/radeon: suspend timer queries between IBs
Marek Olšák [Fri, 31 Jul 2015 00:39:02 +0000 (02:39 +0200)]
gallium/radeon: suspend timer queries between IBs

When we are measuring the time spent in a draw call, an unexpected flush
can distort the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agost/mesa: implement DrawTransformFeedbackStream
Marek Olšák [Thu, 30 Jul 2015 14:14:03 +0000 (16:14 +0200)]
st/mesa: implement DrawTransformFeedbackStream

Reviewed-by: Dave Airlie <airlied@redhat.com>
9 years agomesa: save which transform feedback buffer is associated with which stream
Marek Olšák [Thu, 30 Jul 2015 14:11:50 +0000 (16:11 +0200)]
mesa: save which transform feedback buffer is associated with which stream

Reviewed-by: Dave Airlie <airlied@redhat.com>
9 years agovbo: pass the stream from DrawTransformFeedbackStream to drivers
Marek Olšák [Thu, 30 Jul 2015 13:43:09 +0000 (15:43 +0200)]
vbo: pass the stream from DrawTransformFeedbackStream to drivers

Reviewed-by: Dave Airlie <airlied@redhat.com>
9 years agomesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()
Brian Paul [Mon, 3 Aug 2015 21:06:42 +0000 (15:06 -0600)]
mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()

If the new texture unit is the current texture unit, we can return
before error checking.

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoi965/fs: Lower arithmetic instructions with register regions of unsupported width.
Francisco Jerez [Tue, 4 Aug 2015 16:07:19 +0000 (19:07 +0300)]
i965/fs: Lower arithmetic instructions with register regions of unsupported width.

This extends the SIMD lowering pass to enforce the hardware limitation
that no directly-addressed source may read more than 2 physical GRFs.
One can easily go over this limit when doing 64-bit arithmetic
(e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice
to be able to just emit an instruction of the intended execution size
from the visitor and let the lowering pass deal with this restriction
transparently.

Some hardware arithmetic instructions are not handled here, including
all instructions that use the accumulator implicitly (which the SIMD
lowering pass deliberately doesn't handle), instructions with
non-per-channel sources (e.g. LINE or PLANE) and SEND-like
instructions, which need special handling most likely as virtual
opcodes.

Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.
Francisco Jerez [Wed, 5 Aug 2015 13:29:30 +0000 (16:29 +0300)]
i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.

Otherwise it would crash on Gen8 with scalar VS.  The issue can easily
be reproduced with the following patch, but I don't see any reason why
it wouldn't be possible to end up with an ATTR argument here even
without it.

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
9 years agoi965/fs: Implement nir_op_imul/umul_high in terms of MULH.
Francisco Jerez [Tue, 4 Aug 2015 16:08:45 +0000 (19:08 +0300)]
i965/fs: Implement nir_op_imul/umul_high in terms of MULH.

And get rid of another no16() call.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Lower the MULH virtual instruction.
Francisco Jerez [Thu, 6 Aug 2015 11:04:00 +0000 (14:04 +0300)]
i965/fs: Lower the MULH virtual instruction.

Translate MULH into the MUL/MACH sequence.  This does roughly the same
thing that nir_emit_alu() used to do but we can now handle 16-wide by
taking advantage of the SIMD lowering pass.  The force_sechalf
workaround near the bottom is required because the SIMD lowering pass
will emit instructions with non-zero quarter control and we need to
make sure we avoid that on integer arithmetic instructions with
implicit accumulator access due to a known hardware bug on IVB.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.
Francisco Jerez [Wed, 5 Aug 2015 13:47:18 +0000 (16:47 +0300)]
i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.

In order to make room for the code that will lower the MULH virtual
instruction.  Also move the hardware generation and execution type
checks into the same branch, they are going to have to be different
for MULH.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Lower 32x32 bit multiplication on BXT.
Francisco Jerez [Wed, 5 Aug 2015 13:43:37 +0000 (16:43 +0300)]
i965/fs: Lower 32x32 bit multiplication on BXT.

AFAIK BXT has the same annoying alignment limitation as CHV on the
source register regions of 32x32 bit MULs, give it the same treatment.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Define virtual instruction to calculate the high 32 bits of a multiply.
Francisco Jerez [Tue, 4 Aug 2015 16:04:55 +0000 (19:04 +0300)]
i965: Define virtual instruction to calculate the high 32 bits of a multiply.

This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply.  Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoglsl: Initialize patch member of glsl_struct_field
Michel Dänzer [Wed, 5 Aug 2015 09:17:14 +0000 (18:17 +0900)]
glsl: Initialize patch member of glsl_struct_field

There is apparently a subtle difference in C++ between

    F f;

and

    F f();

The former will use the default constructor.  If there is no default
constructor specified, the compiler provides one that simply invokes the
default constructor for each field.  For built-in basic types, the
default constructor does nothing.  The later will, according to
http://stackoverflow.com/questions/2417065/does-the-default-constructor-initialize-built-in-types)
perform value-initialization of the type.  For built-in types this means
initializing to zero.

The per_vertex_accumulator constructor is:

    per_vertex_accumulator::per_vertex_accumulator()
       : fields(),
         num_fields(0)
    {
    }

This is the second form of constructor, so the glsl_struct_field
objects were previously zero initialized.  With the addition of an empty
default constructor in commit 7ac946e5, per_vertex_accumulator::fields
receive no initialization.

Fixes a bunch of random (mostly tessellation related) piglit failures
since commit 7ac946e5 ("glsl: Add constuctors for the common cases of
glsl_struct_field").

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agonir: add missing type to type_size_vec4()
Timothy Arceri [Wed, 5 Aug 2015 10:27:24 +0000 (20:27 +1000)]
nir: add missing type to type_size_vec4()

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>