Jacob Lifshay [Mon, 13 Jul 2020 02:10:01 +0000 (19:10 -0700)]
sim.pysim: write the next, not curr signal value to the VCD file
This is a temporary fix for #429.
whitequark [Sat, 11 Jul 2020 12:25:31 +0000 (12:25 +0000)]
sim.pysim: use VCD aliases to reduce space and time overhead.
On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:51:56 +0000 (14:51 +0000)]
add dummy extras_require to setup.py
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:51:02 +0000 (14:51 +0000)]
whitespace
whitequark [Wed, 8 Jul 2020 17:30:06 +0000 (17:30 +0000)]
sim: simplify. NFC.
whitequark [Wed, 8 Jul 2020 12:49:38 +0000 (12:49 +0000)]
back.pysim→sim.pysim; split into more manageable parts.
This is necessary to add cxxrtl as an alternate simulation engine.
whitequark [Wed, 8 Jul 2020 09:08:00 +0000 (09:08 +0000)]
vendor.xilinx_{7series,ultrascale}: remove `grade` property.
This was added in commit
bfd4538d based on a misunderstanding of how
Xilinx part numbers work.
* non-ultrascale 7-series parts don't have temperature grades;
* ultrascale parts have temperature grade as a part of speed grade.
whitequark [Wed, 8 Jul 2020 08:29:20 +0000 (08:29 +0000)]
back.pysim: only extract signal names if VCD is requested.
This commit also fixes an issue introduced in
2606ee33 that regressed
simulator startup time and bloated VCD files. (It's actually about
10% faster now than *before* the regression was introduced.)
whitequark [Wed, 8 Jul 2020 07:12:00 +0000 (07:12 +0000)]
back.pysim: reset timeline as well.
This is a bug that was introduced in
94faf497b.
whitequark [Wed, 8 Jul 2020 06:29:34 +0000 (06:29 +0000)]
back.pysim: simplify. NFC.
whitequark [Wed, 8 Jul 2020 06:04:50 +0000 (06:04 +0000)]
back.pysim: extract timeline handling to class _Timeline. NFC.
whitequark [Wed, 8 Jul 2020 05:42:33 +0000 (05:42 +0000)]
back.pysim: extract simulator commands to sim._cmds. NFC.
whitequark [Wed, 8 Jul 2020 03:55:09 +0000 (03:55 +0000)]
back.pysim: simplify. NFC.
awygle [Tue, 7 Jul 2020 05:17:03 +0000 (22:17 -0700)]
hdl.ast: don't inherit Shape from NamedTuple.
Fixes #421.
whitequark [Tue, 7 Jul 2020 04:29:13 +0000 (04:29 +0000)]
back.pysim: simplify.
Compiled process names were never particularly useful (comments in
the source would make more sense for debugging), and coroutine
process names were actually source locations.
whitequark [Tue, 7 Jul 2020 04:19:05 +0000 (04:19 +0000)]
back.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 04:09:10 +0000 (04:09 +0000)]
back.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 04:06:06 +0000 (04:06 +0000)]
back.pysim: synchronize waveform writing with cxxrtl.
whitequark [Tue, 7 Jul 2020 02:35:04 +0000 (02:35 +0000)]
back.pysim: synchronize terms with cxxrtl. NFC.
whitequark [Tue, 7 Jul 2020 02:14:06 +0000 (02:14 +0000)]
back.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 01:59:25 +0000 (01:59 +0000)]
back.pysim: simplify. NFC.
whitequark [Mon, 6 Jul 2020 16:01:49 +0000 (16:01 +0000)]
Remove everything deprecated in nmigen 0.2.
Alan Green [Wed, 1 Jul 2020 21:29:30 +0000 (17:29 -0400)]
Update license and copyright info
Remove non-license explanatory text from LICENSE.txt.
Create CONTRIBUTING file with instructions and notes for contributors.
This change relates to issue #412
Konrad Beckmann [Mon, 6 Jul 2020 14:04:24 +0000 (16:04 +0200)]
vendor.lattice_ecp5: Add support for io with xdr=7
This adds support for IOs with xdr=7 using the
IODDR71B and ODDR71B primitives.
Konrad Beckmann [Mon, 6 Jul 2020 14:01:19 +0000 (16:01 +0200)]
vendor.lattice_ecp5: Add support for io with xdr=4
This adds support for IOs with xdr=4 using the
IDDRX2F and ODDRX2F primitives.
whitequark [Sun, 5 Jul 2020 23:51:14 +0000 (23:51 +0000)]
docs: use working sphinxcontrib-platformpicker.
whitequark [Sun, 5 Jul 2020 23:39:47 +0000 (23:39 +0000)]
docs: use sphinxcontrib-platformpicker.
Fixes #416.
whitequark [Sat, 4 Jul 2020 02:09:35 +0000 (02:09 +0000)]
docs: link to community tutorials until we have an official one.
whitequark [Thu, 2 Jul 2020 23:11:35 +0000 (23:11 +0000)]
docs/lang: document constshifts.
whitequark [Thu, 2 Jul 2020 23:08:10 +0000 (23:08 +0000)]
docs/index: rename to "Language & toolchain".
whitequark [Thu, 2 Jul 2020 22:49:04 +0000 (22:49 +0000)]
test: remove FHDLTestCase.assertRaisesRegex.
This method is only there because I misunderstood the documentation
of unittest.
whitequark [Thu, 2 Jul 2020 22:22:44 +0000 (22:22 +0000)]
compat.fhdl.specials: fix handling of tristate (i=None) pins.
Fixes #406.
whitequark [Thu, 2 Jul 2020 18:26:08 +0000 (18:26 +0000)]
_yosys→_toolchain.yosys
whitequark [Thu, 2 Jul 2020 18:13:54 +0000 (18:13 +0000)]
vendor: `yosys` is not a required tool for proprietary toolchains.
Since commit
b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.
Fixes #419.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:40:50 +0000 (14:40 +0000)]
add wheel as setup dependency
whitequark [Wed, 1 Jul 2020 08:58:36 +0000 (08:58 +0000)]
docs/install: use pip/pip3 more consistently.
whitequark [Wed, 1 Jul 2020 08:53:52 +0000 (08:53 +0000)]
docs: clarify naming.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:34:49 +0000 (14:34 +0000)]
re-add setutools and setuptools_scm
whitequark [Wed, 1 Jul 2020 08:16:28 +0000 (08:16 +0000)]
Revert "Add PEP 518 `pyproject.toml`."
This reverts commit
7fca037f9c14974f499195171bb84c38ebddc1e1.
This broke editable installs and has to be reverted due to a number
of pip issues:
* pypa/pip#6375
* pypa/pip#6434
* pypa/pip#6438
We can put this back once PEP 517/518 support editable installs.
Until then the legacy behavior will suffice, and we should just teach
people to install the dependencies in virtualenvs or something...
whitequark [Wed, 1 Jul 2020 08:03:57 +0000 (08:03 +0000)]
docs: add a crude approximation of intersphinx toctrees.
This is a pretty awful hack. We could do this properly after one of
the following issues is fixed:
* sphinx-doc/sphinx#701
* sphinx-doc/sphinx#1836
whitequark [Wed, 1 Jul 2020 07:00:02 +0000 (07:00 +0000)]
Gracefully handle missing dependencies.
Some people's workflows involve not using `pip`. This is not
a recommended way to use nMigen, but is prevalent enough for good
enough reason that we try to keep them working anyway.
whitequark [Wed, 1 Jul 2020 06:33:03 +0000 (06:33 +0000)]
docs/install: fix dead link.
whitequark [Wed, 1 Jul 2020 06:32:15 +0000 (06:32 +0000)]
docs/install: quote special chars to avoid issues with extended glob.
whitequark [Wed, 1 Jul 2020 06:15:16 +0000 (06:15 +0000)]
docs/install: explain how to install non-editable snapshot from git.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:31:28 +0000 (14:31 +0000)]
manually remove setuptools and setuptools_scm, moved
to pyproject.toml
whitequark [Wed, 1 Jul 2020 05:58:05 +0000 (05:58 +0000)]
Add PEP 518 `pyproject.toml`.
This is necessary to be able to install nMigen into a virtualenv that
does not have `wheel` installed in certain cases.
See #349.
whitequark [Wed, 1 Jul 2020 05:06:20 +0000 (05:06 +0000)]
docs/install: use `pip install --user` on *nix.
whitequark [Wed, 1 Jul 2020 04:11:51 +0000 (04:11 +0000)]
docs/install: reduce repetition.
whitequark [Wed, 1 Jul 2020 03:59:16 +0000 (03:59 +0000)]
docs: reword slightly.
whitequark [Wed, 1 Jul 2020 03:46:59 +0000 (03:46 +0000)]
docs: explain how to install GTKWave on Windows.
whitequark [Wed, 1 Jul 2020 03:37:29 +0000 (03:37 +0000)]
CI: build docs on all pushes, update only on
whitequark [Wed, 1 Jul 2020 03:32:17 +0000 (03:32 +0000)]
docs: rewrite install instructions to be easier to understand.
whitequark [Tue, 30 Jun 2020 22:29:43 +0000 (22:29 +0000)]
docs: fix syntax.
whitequark [Tue, 30 Jun 2020 22:28:12 +0000 (22:28 +0000)]
docs: fix CI workflow.
whitequark [Tue, 30 Jun 2020 22:26:54 +0000 (22:26 +0000)]
docs: explain that `pip3 install -e` should be run after pulling.
whitequark [Mon, 27 Apr 2020 07:21:31 +0000 (07:21 +0000)]
Add (heavily work in progress) documentation.
To render correctly, the docs require:
* pygments/pygments#1441
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:16:18 +0000 (14:16 +0000)]
manually add import_metadata, import_resources
whitequark [Tue, 30 Jun 2020 22:08:59 +0000 (22:08 +0000)]
Don't use pkg_resources.
This package is deprecated and introduces a massive amount of startup
latency. On my machine with 264 installed Python packages, it reduces
the time required to `import nmigen` from ~100ms to ~200ms.
whitequark [Sun, 28 Jun 2020 05:17:33 +0000 (05:17 +0000)]
lib.cdc: update PulseSynchronizer to follow conventions.
Fixes #370.
whitequark [Sun, 28 Jun 2020 05:04:16 +0000 (05:04 +0000)]
back.pysim: simplify.
Remove _EvalContext, which was a level of indirection serving almost
no purpose. (The only case where it would be useful is repeatedly
resetting a simulation that, each time it is reset, would create new
signals to communicate with between coroutine processes. In that case
the signal states would not be persisted in _SimulatorState, but
would be removed with the _EvalContext that is recreated each time
the simulation is reset. But this could be solved with a weak map
instead.)
This regresses simulator startup time by 10-15% for unknown reasons
but is necessary to align pysim and future cxxsim.
Alan Green [Tue, 23 Jun 2020 12:12:02 +0000 (22:12 +1000)]
_yosys: handle unparseable versions
Do not use yosys binaries with unparseable version numbers. This ensures
that nmigen always knows what version of yosys it is generating RTLIL
for.
The effect of this change is that if the version number of the system
yosys is unparsable, nmigen will attempt to fallback to the builtin
Yosys.
Fixes #409.
whitequark [Sun, 21 Jun 2020 17:28:01 +0000 (17:28 +0000)]
vendor.lattice_machxo2: add back as a compatibility shim.
Gwenhael Goavec-Merou [Sun, 21 Jun 2020 17:24:47 +0000 (19:24 +0200)]
vendor.lattice_machxo*: add MachXO3L support.
whitequark [Sun, 14 Jun 2020 09:38:32 +0000 (09:38 +0000)]
back.verilog: refactor Yosys script generation. NFCI.
In commit
5f30bcbb, back.cxxsim gained a nicer way to generate
a script; this commit brings it to back.verilog too.
whitequark [Sun, 14 Jun 2020 09:25:54 +0000 (09:25 +0000)]
back.cxxrtl: allow injecting black boxes.
whitequark [Sun, 14 Jun 2020 00:04:18 +0000 (00:04 +0000)]
_yosys: add a way to retrieve Yosys data directory.
This is important for CXXRTL, since that's where its include files
are located.
whitequark [Sun, 14 Jun 2020 00:03:36 +0000 (00:03 +0000)]
_yosys: fix typo in error message.
whitequark [Thu, 11 Jun 2020 16:29:12 +0000 (16:29 +0000)]
test: fix example test after commit
a7b8ced9.
whitequark [Thu, 11 Jun 2020 16:19:40 +0000 (16:19 +0000)]
back.cxxrtl: new backend.
whitequark [Thu, 11 Jun 2020 16:12:52 +0000 (16:12 +0000)]
_yosys: translate Yosys warnings to Python warnings.
This isn't used yet (the only Yosys warning we can get is useless),
but will be handy for CXXRTL.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:07:39 +0000 (14:07 +0000)]
fix yosys version import
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:02:09 +0000 (14:02 +0000)]
manually patch in nmigen-yosys
whitequark [Fri, 22 May 2020 16:50:45 +0000 (16:50 +0000)]
back.verilog: fall back to nmigen_yosys package.
The nmigen-yosys PyPI package provides a custom, minimal build of
Yosys that uses (at the moment) wasmtime-py to deliver a single
WASM binary that can run on many platforms, and eliminates the need
to build Yosys from source.
Not only does this lower barrier to entry for new nMigen developers,
but also decouples nMigen from Yosys' yearly release cycle, which
lets us use new features and drop workarounds for Yosys bugs earlier.
The source for the nmigen-yosys package is provided at:
https://github.com/nmigen/nmigen-yosys
The package is built from upstream source and released automatically
with no manual steps.
Fixes #371.
whitequark [Thu, 11 Jun 2020 15:36:43 +0000 (15:36 +0000)]
nmigen.cli: fix file type autodetection code.
whitequark [Thu, 11 Jun 2020 15:17:49 +0000 (15:17 +0000)]
back.verilog: remove unused imports. NFC.
Adam Greig [Sat, 6 Jun 2020 11:43:25 +0000 (12:43 +0100)]
hdl.xfrm: preserve allow_reset_less when transforming ResetSignal.
Fixes #400.
Shawn Anastasio [Fri, 5 Jun 2020 03:19:46 +0000 (22:19 -0500)]
hdl.rec: preserve shapes when constructing a layout.
Preserve the original user-provided shape, while still checking
its validity. This allows Enum decoders to work when specifying
record fields with Enums.
Fixes #393.
whitequark [Fri, 29 May 2020 17:45:09 +0000 (17:45 +0000)]
setup: exclude tests.
The inclusion of tests in the package was completely unintentional
and a result of my lack of knowledge of setuptools. If you are using
nmigen.test.utils, please copy the parts you need to your own code
because the nmigen.test code can and will change without notice.
whitequark [Fri, 29 May 2020 17:45:09 +0000 (17:45 +0000)]
vendor.lattice_ice40: reword confusing comment. NFC.
Robin Ole Heinemann [Sun, 24 May 2020 15:54:17 +0000 (17:54 +0200)]
hdl.ast: fix typo
whitequark [Thu, 21 May 2020 10:41:23 +0000 (10:41 +0000)]
Update .gitignore.
whitequark [Thu, 21 May 2020 09:49:42 +0000 (09:49 +0000)]
vendor.intel: don't use `write_verilog -decimal`.
See commit
702e41ba for details.
whitequark [Thu, 21 May 2020 09:48:42 +0000 (09:48 +0000)]
vendor.intel: double-quote Tcl values rather than brace-quoting.
For unknown reasons, Quartus treats {foo} and "foo" in completely
different ways, which is not true for normal Tcl code; specifically,
it preserves the braces if they are used. Because of this, since
commit
6cee2804, the vendor.intel package was completely broken.
whitequark [Thu, 21 May 2020 08:57:30 +0000 (08:57 +0000)]
vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
In commit
892cff05, `-decimal` was used when writing Verilog for
Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *)
differently in violation of Verilog LRM. However, it is possible
to avoid that workaround by using (* keep="TRUE" *). Do that,
and remove `-decimal` to avoid special-casing 32-bit constants.
Refs #373.
whitequark [Wed, 20 May 2020 05:35:47 +0000 (05:35 +0000)]
build.plat: skip clock constraints on unused signals.
It's not very nice to add more internal mutable state to Platform
related classes, but our whole approach for Platform is inherently
stateful, and other solutions (like changing every individual vendor
platform to check for unused signals) are even worse.
Fixes #374.
whitequark [Wed, 20 May 2020 04:58:03 +0000 (04:58 +0000)]
vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.
If the clock signal is not a top-level port and has aliases, it can
be optimized out, and then the constraint will no longer apply.
To prevent this, make sure the constrained signal is preferred over
any aliases by using the `keep` attribute.
Vivado does not parse attributes like (* keep = 32'd1 *) as valid
even though, AFAICT, they are equivalent to (* keep = 1 *) or simply
(* keep *) per IEEE 1364. To work around this, use the solution we
currently use for Quartus, which is `write_verilog -decimal`.
Fixes #373.
whitequark [Wed, 20 May 2020 03:18:33 +0000 (03:18 +0000)]
hdl.ast: add const-shift operations.
Also, clean up the rotate code a bit.
Fixes #378.
whitequark [Tue, 19 May 2020 23:43:25 +0000 (23:43 +0000)]
hdl.ast: clarify docs for Value.rotate_{left,right}.
"Rotate modulo 2**len(self)" is redundant because that's just how
rotates work.
whitequark [Tue, 19 May 2020 23:40:49 +0000 (23:40 +0000)]
hdl.dsl: check for unique domain name.
Fixes #385.
whitequark [Tue, 19 May 2020 23:33:14 +0000 (23:33 +0000)]
back.rtlil: handle signed and large Instance parameters correctly.
Fixes #388.
whitequark [Mon, 4 May 2020 05:51:08 +0000 (05:51 +0000)]
tracer: fix get_var_name() to work on toplevel attributes.
E.g. this now works:
>>> class dummy: pass
>>> self = dummy()
>>> self.foo = Signal()
>>> self.foo.name
'foo'
Gwenhael Goavec-Merou [Fri, 8 May 2020 04:42:21 +0000 (06:42 +0200)]
vendor.lattice_machxo2: generate binary bitstreams.
whitequark [Sat, 2 May 2020 10:41:18 +0000 (10:41 +0000)]
plat, vendor: systematically escape net and file names in Tcl.
Before this commit, there was only occasional quoting of some names
used in any Tcl files. (I'm not sure what I was thinking.)
After this commit, any substs that may include Tcl special characters
are escaped. This does not include build names (which are explicitly
restricted to ASCII to avoid this problem), or attribute names (which
are chosen from a predefined set). Ideally we'd use a more principled
approach but Jinja2 does not support custom escaping mechanisms.
Note that Vivado restricts clock names to a more restrictive set that
forbids using Tcl special characters even when escaped.
Fixes #375.
whitequark [Tue, 28 Apr 2020 02:16:12 +0000 (02:16 +0000)]
back.rtlil: fix incorrect escaping of signed parameters.
Also, improve escaping code in general.
whitequark [Mon, 27 Apr 2020 18:06:12 +0000 (18:06 +0000)]
hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signals().
The implementation of these functions likely predates support for
{Clock,Reset}Signal() in SignalKey.
awygle [Fri, 24 Apr 2020 22:27:04 +0000 (15:27 -0700)]
lib.fifo: add r_rst output for AsyncFIFO{,Buffered}.
Fixes #181.
awygle [Fri, 24 Apr 2020 21:15:00 +0000 (14:15 -0700)]
hdl.ir: typecheck `convert(ports=)` more carefully.
The `ports` argument to the `convert` functions is a frequent hotspot of
beginner issues. Check to make sure it is either a list or a tuple, and
give an appropriately helpful error message if not.
Fixes #362.
whitequark [Fri, 24 Apr 2020 21:09:58 +0000 (21:09 +0000)]
README: link directly to Yosys build instructions.
Teguh Hofstee [Thu, 23 Apr 2020 21:46:10 +0000 (14:46 -0700)]
back.verilog: add workaround for evaluation Verific behavior.
The evaluation version of Verific prints its license information to stdout,
and since it is against the EULA to change that in any way, this behavior
is not possible to fix in Yosys. Add a workaround in nMigen instead.
Teguh Hofstee [Wed, 22 Apr 2020 12:23:14 +0000 (05:23 -0700)]
back.verilog: make Yosys version check compatible with Verific.