Eddie Hung [Fri, 7 Jun 2019 22:44:57 +0000 (15:44 -0700)]
Fix spacing from spaces to tabs
Eddie Hung [Fri, 7 Jun 2019 22:39:12 +0000 (15:39 -0700)]
Comment O(N) -> O(N^2)
Eddie Hung [Fri, 7 Jun 2019 22:35:15 +0000 (15:35 -0700)]
Add nonexcl case test, comment out two others
Eddie Hung [Fri, 7 Jun 2019 22:34:16 +0000 (15:34 -0700)]
Extend ExclusiveDatabase to query SigSpec-s (for $pmux)
Eddie Hung [Fri, 7 Jun 2019 21:18:17 +0000 (14:18 -0700)]
Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results
Clifford Wolf [Fri, 7 Jun 2019 21:13:34 +0000 (23:13 +0200)]
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
Eddie Hung [Fri, 7 Jun 2019 20:12:48 +0000 (13:12 -0700)]
Add read_aiger to CHANGELOG
Eddie Hung [Fri, 7 Jun 2019 19:12:11 +0000 (12:12 -0700)]
Add @cliffordwolf freduce testcase
Eddie Hung [Fri, 7 Jun 2019 18:54:29 +0000 (11:54 -0700)]
Add nonexclusive test from @cliffordwolf
Eddie Hung [Fri, 7 Jun 2019 18:37:52 +0000 (11:37 -0700)]
Resolve @cliffordwolf comment on redundant check
Eddie Hung [Fri, 7 Jun 2019 18:36:19 +0000 (11:36 -0700)]
Resolve @cliffordwolf comment on sigmap
Eddie Hung [Fri, 7 Jun 2019 18:30:36 +0000 (11:30 -0700)]
Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung [Fri, 7 Jun 2019 18:28:25 +0000 (11:28 -0700)]
Remove unnecessary std::getline() for ASCII
Eddie Hung [Fri, 7 Jun 2019 18:28:05 +0000 (11:28 -0700)]
Test *.aag too, by using *.aig as reference
Eddie Hung [Fri, 7 Jun 2019 18:07:15 +0000 (11:07 -0700)]
Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung [Fri, 7 Jun 2019 18:06:57 +0000 (11:06 -0700)]
Use ABC to convert from AIGER to Verilog
Eddie Hung [Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)]
Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung [Fri, 7 Jun 2019 18:05:25 +0000 (11:05 -0700)]
Add symbols to AIGER test inputs for ABC
Eddie Hung [Fri, 7 Jun 2019 15:34:58 +0000 (08:34 -0700)]
Another muxpack test
Eddie Hung [Fri, 7 Jun 2019 15:30:39 +0000 (08:30 -0700)]
Allow muxcover costs to be changed
Clifford Wolf [Fri, 7 Jun 2019 11:39:46 +0000 (13:39 +0200)]
Merge pull request #1077 from YosysHQ/clifford/pr983
elaboration system tasks
Clifford Wolf [Fri, 7 Jun 2019 11:12:25 +0000 (13:12 +0200)]
Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 10:41:09 +0000 (12:41 +0200)]
Fixes and cleanups in AST_TECALL handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 10:08:42 +0000 (12:08 +0200)]
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
Clifford Wolf [Fri, 7 Jun 2019 09:53:46 +0000 (11:53 +0200)]
Merge branch 'tux3-implicit_named_connection'
Clifford Wolf [Fri, 7 Jun 2019 09:48:33 +0000 (11:48 +0200)]
Merge pull request #1076 from thasti/centos7-build-fix
Fix pyosys-build on CentOS7
Clifford Wolf [Fri, 7 Jun 2019 09:46:16 +0000 (11:46 +0200)]
Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 09:41:54 +0000 (11:41 +0200)]
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
Stefan Biereigel [Fri, 7 Jun 2019 07:47:33 +0000 (09:47 +0200)]
remove boost/log/exceptions.hpp from wrapper generator
Eddie Hung [Thu, 6 Jun 2019 21:21:34 +0000 (14:21 -0700)]
Fix and test for balanced case
Eddie Hung [Thu, 6 Jun 2019 21:01:42 +0000 (14:01 -0700)]
Fix warnings
Eddie Hung [Thu, 6 Jun 2019 20:51:22 +0000 (13:51 -0700)]
Support cascading $pmux.A with $mux.A and $mux.B
Eddie Hung [Thu, 6 Jun 2019 19:56:34 +0000 (12:56 -0700)]
More cleanup
Eddie Hung [Thu, 6 Jun 2019 19:46:42 +0000 (12:46 -0700)]
Fix spacing
Eddie Hung [Thu, 6 Jun 2019 19:44:50 +0000 (12:44 -0700)]
Non chain user check using next_sig
Eddie Hung [Thu, 6 Jun 2019 19:44:06 +0000 (12:44 -0700)]
Add non exclusive test
Eddie Hung [Thu, 6 Jun 2019 19:15:13 +0000 (12:15 -0700)]
Move muxpack from passes/techmap to passes/opt
Eddie Hung [Thu, 6 Jun 2019 19:11:59 +0000 (12:11 -0700)]
Update doc
Eddie Hung [Thu, 6 Jun 2019 19:04:42 +0000 (12:04 -0700)]
Add to CHANGELOG
Eddie Hung [Thu, 6 Jun 2019 19:03:44 +0000 (12:03 -0700)]
One more and tidy up
Eddie Hung [Thu, 6 Jun 2019 18:59:41 +0000 (11:59 -0700)]
Add a few more special case tests
Eddie Hung [Thu, 6 Jun 2019 18:54:38 +0000 (11:54 -0700)]
Add tests, fix for !=
Eddie Hung [Thu, 6 Jun 2019 18:03:45 +0000 (11:03 -0700)]
Missing file
Eddie Hung [Thu, 6 Jun 2019 17:51:02 +0000 (10:51 -0700)]
Initial adaptation of muxpack from shregmap
tux3 [Tue, 4 Jun 2019 22:47:54 +0000 (00:47 +0200)]
SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
Clifford Wolf [Thu, 6 Jun 2019 10:34:05 +0000 (12:34 +0200)]
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Added support for parsing attributes on port connections.
David Shah [Thu, 6 Jun 2019 10:22:49 +0000 (11:22 +0100)]
Merge pull request #1073 from whitequark/ecp5-diamond-iob
ECP5: implement most Diamond I/O buffer primitives
whitequark [Thu, 6 Jun 2019 10:03:03 +0000 (10:03 +0000)]
ECP5: implement all Diamond I/O buffer primitives.
Clifford Wolf [Thu, 6 Jun 2019 04:50:12 +0000 (06:50 +0200)]
Merge pull request #1071 from YosysHQ/eddie/fix_1070
Fix typo in opt_rmdff causing register to be incorrectly removed
Clifford Wolf [Thu, 6 Jun 2019 04:49:07 +0000 (06:49 +0200)]
Merge pull request #1072 from YosysHQ/eddie/fix_1069
Error out if no top module given before 'sim'
Eddie Hung [Wed, 5 Jun 2019 21:21:44 +0000 (14:21 -0700)]
Missing doc for -tech xilinx in shregmap
Eddie Hung [Wed, 5 Jun 2019 21:16:24 +0000 (14:16 -0700)]
Error out if no top module given before 'sim'
Eddie Hung [Wed, 5 Jun 2019 21:08:14 +0000 (14:08 -0700)]
Fix typo in opt_rmdff
Eddie Hung [Wed, 5 Jun 2019 16:59:05 +0000 (09:59 -0700)]
Merge pull request #1067 from YosysHQ/clifford/fix1065
Suppress driver-driver conflict warning for unknown cell types
Maciej Kurc [Wed, 5 Jun 2019 08:42:43 +0000 (10:42 +0200)]
Fixed memory leak.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Clifford Wolf [Wed, 5 Jun 2019 08:37:39 +0000 (10:37 +0200)]
Merge pull request #1066 from YosysHQ/clifford/fix1056
Remove yosys_banner() from python wrapper init
Clifford Wolf [Wed, 5 Jun 2019 08:26:48 +0000 (10:26 +0200)]
Major rewrite of wire selection in setundef -init
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 5 Jun 2019 07:53:06 +0000 (09:53 +0200)]
Indent fix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 5 Jun 2019 07:50:15 +0000 (09:50 +0200)]
Merge pull request #999 from jakobwenzel/setundefInitFix
initialize more registers in setundef -init
Clifford Wolf [Wed, 5 Jun 2019 07:26:44 +0000 (09:26 +0200)]
Fix typo in fmcombine log message, fixes #1063
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 5 Jun 2019 07:14:12 +0000 (09:14 +0200)]
Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 5 Jun 2019 06:57:33 +0000 (08:57 +0200)]
Remove yosys_banner() from python wrapper init, fixes #1056
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 4 Jun 2019 12:37:10 +0000 (14:37 +0200)]
Merge pull request #1062 from tux3/patch-1
README.md: Missing formatting for <tag>
Tux3 [Tue, 4 Jun 2019 08:45:41 +0000 (10:45 +0200)]
README.md: Missing formatting for <tag>
Maciej Kurc [Tue, 4 Jun 2019 08:42:42 +0000 (10:42 +0200)]
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Eddie Hung [Tue, 4 Jun 2019 03:23:37 +0000 (20:23 -0700)]
Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Execute techmap and arith_map simultaneously
Eddie Hung [Tue, 4 Jun 2019 03:04:47 +0000 (20:04 -0700)]
Remove extra newline
Eddie Hung [Tue, 4 Jun 2019 02:36:09 +0000 (19:36 -0700)]
Execute techmap and arith_map simultaneously
Maciej Kurc [Mon, 3 Jun 2019 07:12:51 +0000 (09:12 +0200)]
Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Clifford Wolf [Sun, 2 Jun 2019 08:14:50 +0000 (10:14 +0200)]
Only support Symbiotic EDA flavored Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Maciej Kurc [Fri, 31 May 2019 10:24:12 +0000 (12:24 +0200)]
Added support for parsing attributes on port connections.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Clifford Wolf [Fri, 31 May 2019 07:28:51 +0000 (09:28 +0200)]
Fix "tee" handling of log_streams
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 30 May 2019 08:03:54 +0000 (10:03 +0200)]
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 30 May 2019 07:58:51 +0000 (09:58 +0200)]
Merge pull request #1057 from mmicko/fix_478
Aded one more load of .conf to support change of prefix
Miodrag Milanovic [Wed, 29 May 2019 16:57:03 +0000 (18:57 +0200)]
Aded one more load of .conf to support change of prefix
Clifford Wolf [Tue, 28 May 2019 17:02:26 +0000 (19:02 +0200)]
Merge pull request #1049 from YosysHQ/clifford/fix1047
Do not use shiftmul peepopt pattern when mul result is truncated
Clifford Wolf [Tue, 28 May 2019 15:42:16 +0000 (17:42 +0200)]
Merge pull request #1050 from YosysHQ/clifford/wandwor
Refactored wand/wor support
Clifford Wolf [Tue, 28 May 2019 13:33:47 +0000 (15:33 +0200)]
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 28 May 2019 14:52:40 +0000 (16:52 +0200)]
Merge pull request #1048 from mmicko/fix_enable_pyosys
Moved pyosys block in Makefile
Clifford Wolf [Tue, 28 May 2019 14:43:25 +0000 (16:43 +0200)]
Refactor hierarchy wand/wor handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 28 May 2019 14:42:50 +0000 (16:42 +0200)]
Add actual wandwor test that is part of "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 28 May 2019 13:45:15 +0000 (15:45 +0200)]
Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor
Miodrag Milanovic [Tue, 28 May 2019 13:43:27 +0000 (15:43 +0200)]
Remove info line in 2nd load of conf file
Miodrag Milanovic [Tue, 28 May 2019 12:53:07 +0000 (14:53 +0200)]
Moved pyosys block in Makefile
Clifford Wolf [Tue, 28 May 2019 12:00:28 +0000 (14:00 +0200)]
Merge pull request #1045 from mmicko/afl-gcc-target
afl-fuzzer compile config
Miodrag Milanovic [Mon, 27 May 2019 18:43:10 +0000 (20:43 +0200)]
make config-afl-gcc to help creating conf file
Miodrag Milanovic [Mon, 27 May 2019 18:38:44 +0000 (20:38 +0200)]
Added afl-gcc as target for fuzzer
Stefan Biereigel [Mon, 27 May 2019 17:07:46 +0000 (19:07 +0200)]
Merge branch 'master' into wandwor
Stefan Biereigel [Mon, 27 May 2019 16:45:54 +0000 (18:45 +0200)]
reformat wand/wor test
Stefan Biereigel [Mon, 27 May 2019 16:10:39 +0000 (18:10 +0200)]
remove port direction workaround from test case
Stefan Biereigel [Mon, 27 May 2019 16:07:12 +0000 (18:07 +0200)]
update README.md with wand/wor information
Stefan Biereigel [Mon, 27 May 2019 16:01:44 +0000 (18:01 +0200)]
remove leftovers from ast data structures
Stefan Biereigel [Mon, 27 May 2019 16:00:22 +0000 (18:00 +0200)]
move wand/wor resolution into hierarchy pass
Clifford Wolf [Mon, 27 May 2019 11:26:12 +0000 (13:26 +0200)]
Merge pull request #1044 from mmicko/invalid_width_range
Give error instead of asserting for invalid range, fixes #947
Clifford Wolf [Mon, 27 May 2019 11:25:52 +0000 (13:25 +0200)]
Merge pull request #1043 from mmicko/unsized_constant
Added support for unsized constants, fixes #1022
Clifford Wolf [Mon, 27 May 2019 11:24:19 +0000 (13:24 +0200)]
Merge pull request #1026 from YosysHQ/clifford/fix1023
Keep zero-width wires in opt_clean if and only if they are ports
Clifford Wolf [Mon, 27 May 2019 11:22:51 +0000 (13:22 +0200)]
Merge pull request #1030 from Kmanfi/makefile_osx
OS X related Makefile fixes.
Miodrag Milanovic [Mon, 27 May 2019 10:25:18 +0000 (12:25 +0200)]
Give error instead of asserting for invalid range, fixes #947
Miodrag Milanovic [Mon, 27 May 2019 09:42:10 +0000 (11:42 +0200)]
Added support for unsized constants, fixes #1022
Includes work from @sumit0190 and @AaronKel
Kaj Tuomi [Mon, 27 May 2019 08:31:50 +0000 (11:31 +0300)]
Guard all Python-api related items.