Anton Blanchard [Wed, 11 Sep 2019 11:58:01 +0000 (21:58 +1000)]
Merge pull request #44 from antonblanchard/nia-remove
Remove nia from loadstore and multiply
Anton Blanchard [Wed, 11 Sep 2019 11:42:37 +0000 (21:42 +1000)]
Remove nia from loadstore and multiply
Neither unit needs the NIA, so remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 11:42:00 +0000 (21:42 +1000)]
Merge pull request #43 from mikey/trivial
Remove FIXME comment
Michael Neuling [Wed, 11 Sep 2019 06:50:57 +0000 (16:50 +1000)]
Remove FIXME comment
This was mistakenly left behind in
4d5abfb430d1 ("Remove dynamic
ranges from code")
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Wed, 11 Sep 2019 06:05:05 +0000 (16:05 +1000)]
Merge pull request #41 from mikey/travis
Allow a full make check on Travis
Anton Blanchard [Wed, 11 Sep 2019 06:04:10 +0000 (16:04 +1000)]
Merge pull request #42 from antonblanchard/fetch-rework-v2
Fetch rework
Anton Blanchard [Tue, 10 Sep 2019 21:55:35 +0000 (07:55 +1000)]
Reformat core.vhdl
Anton Blanchard [Tue, 10 Sep 2019 21:16:56 +0000 (07:16 +1000)]
Remove sim console
We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:22:58 +0000 (16:22 +1000)]
Reduce multiply to 2 cycles
We want all non load/store ops to take 2 cycles to make
tracking write back easier.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:04:39 +0000 (16:04 +1000)]
Register outputs on writeback
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:40:20 +0000 (15:40 +1000)]
Register outputs on execute2
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:39:50 +0000 (15:39 +1000)]
Register outputs on loadstore1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:02:18 +0000 (15:02 +1000)]
Move debug execute output into decode2
This covers all units, and we avoid double printing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 3 Sep 2019 23:36:30 +0000 (09:36 +1000)]
Rework pipeline, add stall and flush signals
This adds stall and flush signals to the pipeline.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Wed, 11 Sep 2019 00:18:19 +0000 (10:18 +1000)]
Allow a full make check on Travis
Some Travis instances allow more CPU time. On these we can perform the
full 'make check'.
This patch allows this longer `make check`. To enable it you need to
go into your Travis configuration and add a TRAVIS_FULL_CHECK
environment variable.
If you don't add this environment, the shorter make check_light is
still run.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Tue, 10 Sep 2019 21:48:19 +0000 (07:48 +1000)]
Merge pull request #40 from antonblanchard/makefile-dependencies
Update Makefile dependencies
Anton Blanchard [Tue, 10 Sep 2019 21:32:00 +0000 (07:32 +1000)]
Update Makefile dependencies
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:59:10 +0000 (16:59 +0100)]
Switch soc to use std_ulogic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:40:11 +0000 (16:40 +0100)]
Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:39:52 +0000 (16:39 +0100)]
Pass wishbone record to bram memory module
(And rename it to mw_soc_memory).
This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 13:52:23 +0000 (14:52 +0100)]
Rework wishbone slave address decoding
Don't make it synchronous, no latches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 31 Aug 2019 08:54:58 +0000 (18:54 +1000)]
Move wishbone arbiter out of the core
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 12:01:17 +0000 (13:01 +0100)]
Re-indent and reformat soc.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 11:45:33 +0000 (12:45 +0100)]
Split FPGA toplevel from soc
This will be useful when we start needing different toplevels for
different boards.
We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Tue, 10 Sep 2019 07:07:09 +0000 (17:07 +1000)]
Merge pull request #39 from antonblanchard/no-x-state
Don't send out X state from the memory behavioural
Anton Blanchard [Tue, 10 Sep 2019 06:46:41 +0000 (16:46 +1000)]
Don't send out X state from the memory behavioural
Just send out all 1s.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:31:37 +0000 (16:31 +1000)]
Merge pull request #36 from mikey/gitignore
Add new files to git ignore
Anton Blanchard [Tue, 10 Sep 2019 06:31:08 +0000 (16:31 +1000)]
Merge pull request #38 from antonblanchard/multiply-warn
Quieten multiply warning
Anton Blanchard [Tue, 10 Sep 2019 05:31:54 +0000 (15:31 +1000)]
Quieten multiply warning
We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 10 Sep 2019 05:00:35 +0000 (15:00 +1000)]
Add new files to git ignore
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Mon, 9 Sep 2019 23:14:31 +0000 (09:14 +1000)]
Merge pull request #35 from antonblanchard/multiply-opt
Simplify multiply
Anton Blanchard [Sun, 8 Sep 2019 01:11:15 +0000 (11:11 +1000)]
Simplify multiply
No need to gate everything with the valid bit.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 22:09:48 +0000 (08:09 +1000)]
Merge pull request #34 from antonblanchard/decode-table
Decode table
Anton Blanchard [Mon, 2 Sep 2019 06:11:31 +0000 (16:11 +1000)]
Add a decode bit to mark an instruction as single through the pipeline
This is used by the pipelining patches. Mark everyone as single through
the pipeline to start.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Benjamin Herrenschmidt [Mon, 2 Sep 2019 22:44:01 +0000 (08:44 +1000)]
decode1 array fix header
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Mon, 9 Sep 2019 12:44:34 +0000 (22:44 +1000)]
Merge pull request #33 from antonblanchard/cr-fix
Fix CR forwarding
Anton Blanchard [Mon, 9 Sep 2019 12:21:30 +0000 (22:21 +1000)]
Merge pull request #32 from antonblanchard/register-file-forwarding
Add forwarding in the register file
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:09:45 +0000 (00:09 +1000)]
Use simulated UART in core test bench
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:09:24 +0000 (00:09 +1000)]
Make sim poll non-blocking
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:08:54 +0000 (00:08 +1000)]
Add simulated UART design
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Mon, 9 Sep 2019 12:16:11 +0000 (22:16 +1000)]
Fix CR forwarding
We weren't actually forwarding writes in the same cycle. Not a
problem right now, but noticed when testing the pipelining series.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 06:36:47 +0000 (16:36 +1000)]
Add forwarding in the register file
We need this for the upcoming pipelining patches.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 06:12:59 +0000 (16:12 +1000)]
Merge pull request #31 from antonblanchard/no-second-write-port-2
More second write port removal
Anton Blanchard [Mon, 9 Sep 2019 06:12:39 +0000 (16:12 +1000)]
Merge pull request #30 from antonblanchard/writeback-assert
Add some assertions to writeback
Anton Blanchard [Mon, 9 Sep 2019 06:00:49 +0000 (16:00 +1000)]
More second write port removal
I missed the register file updates for the second write port
removal.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:54:09 +0000 (15:54 +1000)]
Add some assertions to writeback
We want to make sure we never complete more than one
instruction per cycle, or write back more than one GPR
or CR per cycle.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:51:34 +0000 (15:51 +1000)]
Merge pull request #29 from antonblanchard/no-second-write-port
Remove second write port
Anton Blanchard [Mon, 9 Sep 2019 05:50:46 +0000 (15:50 +1000)]
Merge pull request #28 from antonblanchard/loadstore-cleanup
Remove some more loadstore debug
Anton Blanchard [Mon, 9 Sep 2019 05:18:09 +0000 (15:18 +1000)]
Remove second write port
We only need two write ports for load with update instructions.
Having two write ports just for this instruction is expensive.
For now we will force them to be the only instruction in the
pipeline, and take two cycles of writeback.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:03:06 +0000 (15:03 +1000)]
Remove some more loadstore debug
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 03:35:12 +0000 (13:35 +1000)]
Merge pull request #27 from antonblanchard/fix-cr
Fix issues with CR rework
Anton Blanchard [Mon, 9 Sep 2019 03:03:27 +0000 (13:03 +1000)]
Fix issues with CR rework
It simulated fine, but didn't synthesize. Fix some obvious issues
to get us going again.
Fixes: 9fbaea6f0819 ("Rework CR file and add forwarding")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 01:42:55 +0000 (11:42 +1000)]
Merge pull request #26 from antonblanchard/silence-loadstore-debug
Silence some loadstore related debug
Anton Blanchard [Mon, 9 Sep 2019 01:42:41 +0000 (11:42 +1000)]
Merge pull request #25 from antonblanchard/register_file_printing
Clean up register read debug output
Anton Blanchard [Mon, 9 Sep 2019 01:41:44 +0000 (11:41 +1000)]
Merge pull request #24 from antonblanchard/cr_file_cleanup
Rework CR file and add forwarding
Anton Blanchard [Mon, 9 Sep 2019 01:23:29 +0000 (11:23 +1000)]
Silence some loadstore related debug
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 01:18:26 +0000 (11:18 +1000)]
Clean up register read debug output
Right now we continually print all 3 possible GPRs an instruction
may be using. Add signals so we only print GPRs when they are
actually read. This should hopefully optimise away when synthesized.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 8 Sep 2019 23:32:08 +0000 (09:32 +1000)]
Rework CR file and add forwarding
Handle the CR as a single field with per nibble enables. Forward any
writes in the same cycle.
If this proves to be an issue for timing, we may want to revisit
this in the future. For now, it keeps things simple.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 8 Sep 2019 08:04:38 +0000 (18:04 +1000)]
Merge pull request #19 from antonblanchard/cmod-a7
Cmod A7-35 support
Anton Blanchard [Fri, 6 Sep 2019 06:24:16 +0000 (16:24 +1000)]
Cmod A7-35 support
This adds support for the Digilane Cmod A7-35.
I had to use the MMCM because the clock (12 MHz) is below the PLL
minimum of 19 MHz.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 8 Sep 2019 06:34:10 +0000 (16:34 +1000)]
Merge pull request #20 from antonblanchard/reset-rework2
Rework reset code
Anton Blanchard [Sun, 8 Sep 2019 06:23:54 +0000 (16:23 +1000)]
Merge pull request #22 from antonblanchard/store-fix
Stores need to wait for wishbone write ack
Anton Blanchard [Sun, 8 Sep 2019 06:00:36 +0000 (16:00 +1000)]
Stores need to wait for wishbone write ack
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 8 Sep 2019 00:19:29 +0000 (10:19 +1000)]
Merge pull request #21 from antonblanchard/xdc-update
Add CONFIG_VOLTAGE and CFGBVS entries
Anton Blanchard [Sat, 7 Sep 2019 23:49:39 +0000 (09:49 +1000)]
Add CONFIG_VOLTAGE and CFGBVS entries
Remove a couple of warnings from Vivado.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 7 Sep 2019 11:28:21 +0000 (21:28 +1000)]
Rework SOC reset
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:
- Wait a number of external clock cycles before removing reset from
the PLL.
- After the PLL locks and the external reset button isn't pressed,
wait a number of PLL clock cycles before removing reset from the SOC.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 7 Sep 2019 11:08:02 +0000 (21:08 +1000)]
Rename a few reset signals
clk -> ext_clk
reset_n -> ext_rst
reset -> rst
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 6 Sep 2019 10:54:50 +0000 (20:54 +1000)]
Merge pull request #18 from mikey/verific
Fix verific script with new VHDL files
Michael Neuling [Fri, 6 Sep 2019 05:05:01 +0000 (15:05 +1000)]
Fix verific script with new VHDL files
This really needs to be auto generated, but here we are.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Fri, 6 Sep 2019 00:09:26 +0000 (10:09 +1000)]
Merge pull request #17 from antonblanchard/writeback-signal
Use a better input signal in writeback
Anton Blanchard [Thu, 5 Sep 2019 23:46:55 +0000 (09:46 +1000)]
Use a better input signal in writeback
w_in comes from the execution unit, it makes more sense to call
it e_in.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 3 Sep 2019 20:33:40 +0000 (06:33 +1000)]
Merge pull request #16 from antonblanchard/decode2_rework2
Rework decode2
Anton Blanchard [Tue, 3 Sep 2019 02:44:03 +0000 (12:44 +1000)]
Rework decode2
The decode2 stage was spaghetti code and needed cleaning up.
Create a series of functions to pull fields from a ppc instruction
and also a series of helpers to extract values for the execution
units.
As suggested by Paul, we should pass all signals to the execution
units and only set the valid signal conditionally, which should
use less resources.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 31 Aug 2019 03:34:38 +0000 (13:34 +1000)]
Merge pull request #13 from mikey/dynamic-ranges
Remove dynamic ranges from code
Michael Neuling [Wed, 28 Aug 2019 23:47:45 +0000 (09:47 +1000)]
Remove dynamic ranges from code
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.
Also add basic script to run verific and generate verilog.
1. https://www.verific.com/
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Thu, 29 Aug 2019 23:06:48 +0000 (09:06 +1000)]
Merge pull request #10 from antonblanchard/arty-fix
Arty A7 reset pin is C2
Anton Blanchard [Thu, 29 Aug 2019 22:39:44 +0000 (08:39 +1000)]
Arty A7 reset pin is C2
Use C2 for reset, and fix up a few whitespace issues.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 29 Aug 2019 22:38:13 +0000 (08:38 +1000)]
Merge pull request #7 from riktw/fusesoc_arty_a7
Fusesoc arty a7
Anton Blanchard [Thu, 29 Aug 2019 22:26:35 +0000 (08:26 +1000)]
Merge pull request #9 from antonblanchard/travis-fix
A few Travis CI fixes
Anton Blanchard [Thu, 29 Aug 2019 22:12:54 +0000 (08:12 +1000)]
A few Travis CI fixes
- Switch to using ghdl/vunit:llvm, it's a smaller container
- We need to "apt update" before installing packages
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
riktw [Tue, 27 Aug 2019 20:20:02 +0000 (22:20 +0200)]
Added support for building for Arty A7 boards
Anton Blanchard [Wed, 28 Aug 2019 21:46:51 +0000 (07:46 +1000)]
Merge pull request #5 from antonblanchard/travis-test
Add an initial travis.yml
Anton Blanchard [Tue, 27 Aug 2019 00:40:43 +0000 (10:40 +1000)]
Add an initial travis.yml
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 28 Aug 2019 04:50:11 +0000 (14:50 +1000)]
Add srd and srw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 28 Aug 2019 04:07:29 +0000 (14:07 +1000)]
Add sim only divw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 12:12:33 +0000 (22:12 +1000)]
Fix ghdl build error with pp_soc_memory
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 02:02:00 +0000 (12:02 +1000)]
micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 27 Aug 2019 01:50:25 +0000 (11:50 +1000)]
Merge pull request #6 from mikey/gif
Add pretty gif demo of MicroPython on Microwatt to README.md
Anton Blanchard [Tue, 27 Aug 2019 01:44:34 +0000 (11:44 +1000)]
Add -Wall to CFLAGS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 27 Aug 2019 01:19:15 +0000 (11:19 +1000)]
Add pretty gif demo of MicroPython on Microwatt to README.md
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Mon, 26 Aug 2019 13:11:51 +0000 (23:11 +1000)]
Add missing argument to fprintf warning
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 12:32:15 +0000 (22:32 +1000)]
Add some initial FPGA synthesis instructions
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 02:33:15 +0000 (12:33 +1000)]
Rebuild hello world assuming a 50MHz clock
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 26 Aug 2019 12:02:17 +0000 (22:02 +1000)]
Merge pull request #3 from olofk/plle2
Add and use plle2 primitive for nexys boards
Olof Kindgren [Sat, 24 Aug 2019 09:25:21 +0000 (11:25 +0200)]
Add and use plle2 primitive for nexys boards
Anton Blanchard [Mon, 26 Aug 2019 01:33:38 +0000 (11:33 +1000)]
Merge pull request #4 from sharkcz/build
don't cross compile when on Power
Dan Horák [Sat, 24 Aug 2019 12:02:35 +0000 (14:02 +0200)]
don't cross compile when on Power
Anton Blanchard [Fri, 23 Aug 2019 22:59:17 +0000 (08:59 +1000)]
Add a simple hello_world example that also echos input
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 23 Aug 2019 19:25:48 +0000 (05:25 +1000)]
Merge pull request #2 from olofk/fusesoc_nexys_a7
Fusesoc nexys a7
Olof Kindgren [Fri, 23 Aug 2019 12:20:20 +0000 (14:20 +0200)]
Added synthesis target
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.
To run synthesis only for a part, run
fusesoc run --target=synth --tool=vivado microwatt --part=<part>
where part is a valid Xilinx part such as xc7a100tcsg324-1
projects / microwatt.git / log