Ron Dreslinski [Fri, 30 Jun 2006 20:25:35 +0000 (16:25 -0400)]
First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality.
src/mem/cache/base_cache.cc:
Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects.
Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
Update for newmem
--HG--
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2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
Ron Dreslinski [Fri, 30 Jun 2006 15:34:27 +0000 (11:34 -0400)]
Fix the packet data allocation methods. Small fixes from changesets after my initial work.
This now compiles.
src/mem/cache/base_cache.cc:
Fix getPort function that changed
src/mem/cache/base_cache.hh:
Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
Fix virtual function declerations
src/mem/cache/cache_builder.cc:
Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
Properly allocate data in packet
--HG--
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dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
Ron Dreslinski [Fri, 30 Jun 2006 14:25:50 +0000 (10:25 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem
--HG--
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6eefb4a3ee472f2f2c86ed823c70fc9e5625818f
Ron Dreslinski [Fri, 30 Jun 2006 14:25:25 +0000 (10:25 -0400)]
All files compile in the mem directory except cache_builder
Missing some functionality (like split caches and copy support)
src/SConscript:
Typo
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.hh:
src/mem/request.hh:
Fix so it compiles
--HG--
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0d87d84f6e9445bab655c0cb0f8541bbf6eab904
Kevin Lim [Fri, 30 Jun 2006 01:38:16 +0000 (21:38 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
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0756f7f1f63fae472e0ef1d20e9eb38e56de78c8
Kevin Lim [Fri, 30 Jun 2006 01:34:01 +0000 (21:34 -0400)]
Remove function that no longer can be used. We should figure out if we want to allow the m5checkpoint pseudoinstruction or not.
src/sim/pseudo_inst.cc:
Remove the setup function from Checkpoint. I'm not sure what we want to do with this pseudoinst.
src/sim/serialize.hh:
Remove setup function.
--HG--
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5ff494d816e2d8a7fe65a3d13037608003388d8f
Kevin Lim [Thu, 29 Jun 2006 23:45:24 +0000 (19:45 -0400)]
Various fixes for the CPU models to support the features that have been moved to python.
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/simple/atomic.hh:
Switching out no longer takes a sampler.
src/cpu/simple/atomic.cc:
Fix up switching out. Also fix up serialization; the nameOut() was messing up the ordering.
src/cpu/simple/timing.cc:
Add in quiesce, fix up serialization.
src/cpu/simple/timing.hh:
Add in queisce, fix up serialization.
--HG--
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9d59d53bdf269d4d82fb119e5ae7c8a5d475880b
Kevin Lim [Thu, 29 Jun 2006 23:40:12 +0000 (19:40 -0400)]
Add in support for quiescing the system, taking checkpoints, restoring from checkpoints, changing memory modes, and switching CPUs.
Key new functions that can be called on the m5 object at the python interpreter:
doQuiesce(root) - A helper function that quiesces the object passed in and all of its children.
resume(root) - Another helper function that tells the object and all of its children that the quiesce is over.
checkpoint(root) - Takes a checkpoint of the system. Checkpoint directory must be set before hand.
setCheckpointDir(name) - Sets the checkpoint directory.
restoreCheckpoint(root) - Restores the values from the checkpoint located in the checkpoint directory.
changeToAtomic(system) - Changes the system and all of its children to atomic memory mode.
changeToTiming(system) - Changes the system and all of its children to timing memory mode.
switchCpus(list) - Takes in a list of tuples, where each tuple is a pair of (old CPU, new CPU). Quiesces the old CPUs, and then switches over to the new CPUs.
src/SConscript:
Remove serializer, replaced by python code.
src/python/m5/__init__.py:
Updates to support quiescing, checkpointing, changing memory modes, and switching CPUs.
src/python/m5/config.py:
Several functions defined on the SimObject for quiescing, changing timing modes, and switching CPUs
src/sim/main.cc:
Add some extra functions that are exported to python through SWIG.
src/sim/serialize.cc:
Change serialization around a bit. Now it is controlled through Python, so there's no need for SerializeEvents or SerializeParams.
Also add in a new unserializeAll() function that loads a checkpoint and handles unserializing all objects.
src/sim/serialize.hh:
Add unserializeAll function and a setCheckpointName function.
src/sim/sim_events.cc:
Add process() function for CountedQuiesceEvent, which calls exitSimLoop() once its counter reaches 0.
src/sim/sim_events.hh:
Add in a CountedQuiesceEvent, which is used when the system is preparing to quiesce. Any objects that can't be quiesced immediately are given a pointer to a CountedQuiesceEvent. The event has its counter set via Python, and as objects finish quiescing they call process() on the event. Eventually the event causes the simulation to stop once all objects have quiesced.
src/sim/sim_object.cc:
Add a few functions for quiescing, checkpointing, and changing memory modes.
src/sim/sim_object.hh:
Add a state variable to all SimObjects that tracks both the timing mode of the object and the quiesce state of the object. Currently this isn't serialized, and I'm not sure it needs to be so long as the timing mode starts up the same after a checkpoint.
--HG--
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a8c738d3911c68d5a7caf7de24d732dcc62cfb61
Ali Saidi [Thu, 29 Jun 2006 20:52:47 +0000 (16:52 -0400)]
Update the readme to point people to m5.eecs.umich.edu
start a new release section in RELEASE_NOTES
add AUTHORS file that still needs work
README:
Update the readme to point people to m5.eecs.umich.edu
RELEASE_NOTES:
start a new release section
--HG--
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4c51e4255aecb67b10f18337428e5af114759d2e
Ron Dreslinski [Thu, 29 Jun 2006 20:07:19 +0000 (16:07 -0400)]
Still missing prefetch and tags directories as well as cache builder.
Some implementation details were left blank still, need to fill them in.
src/SConscript:
Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
Add some more support, need to clean some of it out once everything is working
--HG--
extra : convert_revision :
ba73676165810edf2c2effaf5fbad8397d6bd800
Ron Dreslinski [Wed, 28 Jun 2006 21:28:33 +0000 (17:28 -0400)]
More Changes, working towards cache.cc compiling. Headers cleaned up.
src/mem/cache/cache_blk.hh:
Remove XC
--HG--
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aa2c43e4412ebb93165e12f693d5126983cfd0dc
Ron Dreslinski [Wed, 28 Jun 2006 18:35:00 +0000 (14:35 -0400)]
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on
src/SConscript:
Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
Backing in more changsets, getting closer to compile
--HG--
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ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
Ron Dreslinski [Wed, 28 Jun 2006 15:02:14 +0000 (11:02 -0400)]
Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
Trying to merge
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/prefetch/ghb_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.cc:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher.hh:
src/mem/cache/tags/base_tags.cc:
src/mem/cache/tags/base_tags.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/repl/gen.cc:
src/mem/cache/tags/repl/gen.hh:
src/mem/cache/tags/repl/repl.cc:
src/mem/cache/tags/repl/repl.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_blk.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Pulling an early version of the cache into the tree due to merging issues. Will apply patches and push.
--HG--
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3276e5fb9a6272681a1690babf2b586dd0e1f380
Ali Saidi [Tue, 27 Jun 2006 19:04:11 +0000 (15:04 -0400)]
change the page table from map to hash_map and create small cache to to speed up lookups
--HG--
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4c73ed33c2a22ae3254b459b0fd189e6ac9d438e
Ali Saidi [Tue, 27 Jun 2006 18:59:38 +0000 (14:59 -0400)]
Make full CPU handle SE faults
--HG--
extra : convert_revision :
e336623ac3329ec0ee2430548c6a9650e2a69d6a
Ali Saidi [Tue, 27 Jun 2006 18:58:46 +0000 (14:58 -0400)]
Add help strings for options
--HG--
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ebbafaf00c56a4d2ee65eea08a12d276f279135d
Kevin Lim [Tue, 27 Jun 2006 17:57:44 +0000 (13:57 -0400)]
Fix import command.
--HG--
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8a87b23dba77b7661583029920b8fc5ea89fe8f6
Ali Saidi [Mon, 26 Jun 2006 21:50:58 +0000 (17:50 -0400)]
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
39c99c8acadd43f3ec42ae7550289a5075d910e4
Ali Saidi [Mon, 26 Jun 2006 21:50:48 +0000 (17:50 -0400)]
don't depend on the memory system to return the atomic cpu a multiple of cpu cycles.
--HG--
extra : convert_revision :
e5eb36f14c8394381a0269fefd34a178833c8346
Ali Saidi [Mon, 26 Jun 2006 21:49:49 +0000 (17:49 -0400)]
remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern
name should be mangled, but it isn't
--HG--
extra : convert_revision :
62e2a1989e8fd3d73958d3a3e2d00e378488e642
Ali Saidi [Mon, 26 Jun 2006 20:50:19 +0000 (16:50 -0400)]
add python options for input file and command line options for live process
--HG--
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3db1e6d29846812378aa5174179a0686f0141580
Ali Saidi [Mon, 26 Jun 2006 20:49:05 +0000 (16:49 -0400)]
add syscall emulation page table fault so we can allocate more stack pages
src/cpu/simple/base.cc:
add syscall emulation page table fault so we can allocate more stack pages
FaultBase::invoke will do this, we don't need to do it here
src/sim/faults.hh:
I have no idea why this #if was there... gone
src/sim/process.cc:
make stack_min actually be the current minimum
--HG--
extra : convert_revision :
9786b39f2747b94654a5d77c74243cd20503add4
Kevin Lim [Sun, 25 Jun 2006 04:24:50 +0000 (00:24 -0400)]
Allow ports to be created without a name.
--HG--
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26dad6853feaf4f68907aab902c54259281cac1c
Kevin Lim [Sun, 25 Jun 2006 04:22:41 +0000 (00:22 -0400)]
Make OzoneCPU work again in SE/FS.
src/cpu/ozone/cpu.hh:
Fixes to get OzoneCPU working in SE/FS again.
src/cpu/ozone/cpu_impl.hh:
Be sure to set up ports properly.
src/cpu/ozone/front_end.hh:
Allow port to be created without specifying its name at the beginning.
src/cpu/ozone/front_end_impl.hh:
Setup port properly, also only use checker if it's enabled.
src/cpu/ozone/lw_back_end_impl.hh:
Be sure to initialize variables.
src/cpu/ozone/lw_lsq.hh:
Handle locked flag for UP systems.
src/cpu/ozone/lw_lsq_impl.hh:
Initialize all variables.
src/python/m5/objects/OzoneCPU.py:
Fix up config.
--HG--
extra : convert_revision :
c99e7bf82fc0dd1099c7a82eaebd58ab6017764d
Kevin Lim [Fri, 23 Jun 2006 03:43:45 +0000 (23:43 -0400)]
Checker related updates.
src/cpu/o3/cpu.cc:
Updates to make sure the checker is compiled in if enabled and also to include it only when it's used.
--HG--
extra : convert_revision :
c48ead5b2665dc858acd87c2ee99d39d80594a69
Kevin Lim [Fri, 23 Jun 2006 03:34:37 +0000 (23:34 -0400)]
Delete old unused files in the Ozone directory.
--HG--
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8f417b566e772d7a26d91fb66ff3d4484bd35c42
Kevin Lim [Fri, 23 Jun 2006 03:33:26 +0000 (23:33 -0400)]
Changes to get OzoneCPU to compile once more.
The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened.
OzoneCPU is untested for now but at least compiles. Fixes will be coming shortly.
SConstruct:
Remove OzoneSimpleCPU from list of CPUs.
src/cpu/SConscript:
Leave out OzoneSimpleCPU.
src/cpu/ozone/bpred_unit.cc:
Fixes to get OzoneCPU to compile.
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/dyn_inst_impl.hh:
src/cpu/ozone/front_end.cc:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/rename_table.cc:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
Fixes to get OzoneCPU back to compiling.
--HG--
extra : convert_revision :
90ffb397263bcf9fea3987317272c64f2b20f7e6
Kevin Lim [Thu, 22 Jun 2006 22:10:17 +0000 (18:10 -0400)]
Change ThreadState constructor ordering to match the rest of the ThreadStates.
--HG--
extra : convert_revision :
63d98aa8b6a694c285d95a2a57e1b3aaef4cee3b
Kevin Lim [Thu, 22 Jun 2006 22:09:31 +0000 (18:09 -0400)]
Misc fixes.
src/cpu/o3/alpha_dyn_inst_impl.hh:
Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
Only include checker if it's being used.
--HG--
extra : convert_revision :
aae0bf1e19baae90f1e61d41191548612bbb3be6
Kevin Lim [Thu, 22 Jun 2006 22:05:12 +0000 (18:05 -0400)]
Split Checker up properly into templated and non-templated definitions.
--HG--
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3ead18e42f4a536f2f868da07cb81a8940a7fa2f
Kevin Lim [Thu, 22 Jun 2006 22:03:08 +0000 (18:03 -0400)]
Fix to have the static inst exec sigs also dependent on the CPU models used.
--HG--
extra : convert_revision :
65d978d638dd9a57a641ca52adcf2c0ef48edf1c
Korey Sewell [Sun, 18 Jun 2006 19:58:14 +0000 (15:58 -0400)]
use 'tick' instead of 'cycle'
--HG--
extra : convert_revision :
e7119d20ef95deab16081743c885979b0fa85548
Steve Reinhardt [Sun, 18 Jun 2006 16:31:24 +0000 (12:31 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into tpx31.:C:/cygwin/home/stever/bk/newmem
--HG--
extra : convert_revision :
c13feaea77fe650a3d11112804a88bc5c729c32e
Steve Reinhardt [Sun, 18 Jun 2006 16:30:24 +0000 (12:30 -0400)]
Put sconsign in bulid dir.
--HG--
extra : convert_revision :
e1be318e99037842501306e7c35cf4d6690ebdce
Ali Saidi [Sun, 18 Jun 2006 15:10:19 +0000 (11:10 -0400)]
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
1b2352532b6e1d1e180f3debd66588a450a46923
Ali Saidi [Sun, 18 Jun 2006 15:10:08 +0000 (11:10 -0400)]
minor device fixups
configs/test/SysPaths.py:
remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
move DmaReqState into DmaDevie
--HG--
extra : convert_revision :
2b5300d85ab33b3753afc54bc6a04a47b6e00d20
Kevin Lim [Sun, 18 Jun 2006 02:55:00 +0000 (22:55 -0400)]
Minor updates.
src/cpu/o3/alpha_cpu.hh:
Fix #define in header.
util/rundiff:
Fix file comments to be more correct.
util/tracediff:
Update comments to be more correct.
--HG--
extra : convert_revision :
a28030ce8979de3d9361191c6af23743460dc53e
Kevin Lim [Sun, 18 Jun 2006 02:33:40 +0000 (22:33 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
a11200523e2cf7f69547b1a4f5622396caa511be
Steve Reinhardt [Sun, 18 Jun 2006 02:28:40 +0000 (22:28 -0400)]
Delete old doxygen docs... now on wiki.
Update release scripts for new tree structure.
--HG--
extra : convert_revision :
35603f5476abd296625f777718c1245593a5dfc4
Kevin Lim [Sun, 18 Jun 2006 02:05:02 +0000 (22:05 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
037fe9ee54da7e11c2bd07388b9f79cda9abef4c
Kevin Lim [Sun, 18 Jun 2006 02:04:48 +0000 (22:04 -0400)]
Change options back to just being flags instead of taking in a True/False value.
src/python/m5/__init__.py:
Change up options. Now setting the flag enables/disables, each of which is the opposite of the default values found in the Python class.
--HG--
extra : convert_revision :
23889b89e6105a437a74906587d90ab6ba885c97
Kevin Lim [Sun, 18 Jun 2006 02:01:30 +0000 (22:01 -0400)]
Fix up code to be able to use the Checker.
SConstruct:
Remove check for Checker from this SConstruct
src/arch/SConscript:
Specific check if CheckerCPU is being used. Not the cleanest, but works for now.
src/cpu/SConscript:
Code to handle using the CheckerCPU a little better. Allows -c to be used normally.
--HG--
extra : convert_revision :
0a82f16db0f38e5ce114d08368477bd211331fa3
Kevin Lim [Sun, 18 Jun 2006 01:39:25 +0000 (21:39 -0400)]
Split off instantiation into separate CC files for each of the models. This makes it easier to be able to specify only certain CPU models.
src/cpu/SConscript:
Split off instantiations into separate CC files. This makes it easier to split them per CPU model.
src/cpu/base_dyn_inst_impl.hh:
Move instantations out of impl.hh file and into a cc file.
src/cpu/checker/cpu_impl.hh:
Move instantiations over to .cc files inside each CPU's directory. Makes it easier to only use what's actually included.
src/cpu/o3/bpred_unit.cc:
Pull Ozone instantiations out of this .cc file; put them into the ozone's CC file.
src/cpu/o3/checker_builder.cc:
Instantiate Checker for O3 CPU.
src/cpu/ozone/checker_builder.cc:
Instantiate Checker for Ozone CPU.
--HG--
rename : src/cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst_impl.hh
rename : src/cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : src/cpu/checker/o3_builder.cc => src/cpu/o3/checker_builder.cc
rename : src/cpu/checker/ozone_builder.cc => src/cpu/ozone/checker_builder.cc
extra : convert_revision :
4e5f928b165379c06d31071c544ea46cf0b8fa71
Nathan Binkert [Sat, 17 Jun 2006 23:18:53 +0000 (19:18 -0400)]
include misc.hh for panic
--HG--
extra : convert_revision :
05e59f45b98e862f9d61bec223871b314eb2195e
Ali Saidi [Sat, 17 Jun 2006 23:06:28 +0000 (19:06 -0400)]
add mac os x fast byte swap code
--HG--
extra : convert_revision :
591e5adbf86feb894fceea982b9303da70a41955
Ali Saidi [Sat, 17 Jun 2006 22:44:42 +0000 (18:44 -0400)]
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
9b628a0ee157657ac76c3a9455108d033c125822
Ali Saidi [Sat, 17 Jun 2006 22:40:40 +0000 (18:40 -0400)]
minor header cleanups
src/dev/alpha_console.cc:
Remove my name twice from header
src/dev/ide_disk.cc:
Spell my full name correctly
src/mem/bus.hh:
I think I edited much of this
src/sim/byteswap.hh:
I believe most of this code is mine or nate's
--HG--
extra : convert_revision :
b672b5de5492e04d2880fb51e7d63bc5587f2954
Steve Reinhardt [Sat, 17 Jun 2006 22:28:21 +0000 (18:28 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into tpx31.:C:/cygwin/home/stever/bk/newmem
--HG--
extra : convert_revision :
81affa14d8d900ccd3d1c44cb160eaecfb8599d1
Steve Reinhardt [Sat, 17 Jun 2006 22:27:28 +0000 (18:27 -0400)]
Fixes to compile under Cygwin.
src/kern/linux/linux.hh:
src/kern/solaris/solaris.hh:
Rename BSD_HOST to the more specific NO_STAT64.
src/sim/byteswap.hh:
Replace set of swap_byte functions with a single
templated version. Hope this fixes compiler issues
with e.g. int32_t vs int disambiguation.
src/sim/syscall_emul.hh:
Rename BSD_HOST to the more specific NO_STAT64.
Set this for __CYGWIN__.
--HG--
extra : convert_revision :
86a63b4b60d2445a566321333381d79ba8ab63c4
Nathan Binkert [Sat, 17 Jun 2006 22:14:16 +0000 (18:14 -0400)]
Make the system paths more configurable
configs/test/SysPaths.py:
Make the paths more configurable
--HG--
extra : convert_revision :
c426b102dfe55e4b601a23e980e1b01140e0ee93
Nathan Binkert [Sat, 17 Jun 2006 22:12:44 +0000 (18:12 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/research/m5/newmem
--HG--
extra : convert_revision :
915088112b7b8c3e2182b188ae832b587dd79386
Ali Saidi [Sat, 17 Jun 2006 21:56:33 +0000 (17:56 -0400)]
remove byte_swap.hh since it's not used
--HG--
extra : convert_revision :
20120d34ad2ab28d9dd5ac2907b974c40e511e9e
Ali Saidi [Sat, 17 Jun 2006 21:50:11 +0000 (17:50 -0400)]
remove profile.cc
--HG--
extra : convert_revision :
ac400789ee0cbd1cd01c28ffd149789dbd954613
Nathan Binkert [Sat, 17 Jun 2006 21:49:38 +0000 (17:49 -0400)]
Add myself to list of authors
--HG--
extra : convert_revision :
0c9a892127476d586fb8bff1b0eb7342c6b1f166
Ali Saidi [Sat, 17 Jun 2006 21:17:43 +0000 (17:17 -0400)]
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c8670f1a39d6826870ca0934587f4cc71c94b0ab
Steve Reinhardt [Sat, 17 Jun 2006 16:08:19 +0000 (12:08 -0400)]
Rename SWIG "main" module to "cc_main" so it's
clear from the Python side that this is the
interface to C++.
src/SConscript:
main_wrap.cc -> cc_main_wrap.cc
src/python/SConscript:
src/python/m5/__init__.py:
src/sim/main.cc:
s/main/cc_main/
src/python/m5/config.py:
s/main/cc_main/
Also directly import cc_main so we don't need
to put the "m5." in front all the time.
--HG--
extra : convert_revision :
755552f70cf671881ff31e476c677b95ef12950d
Steve Reinhardt [Sat, 17 Jun 2006 13:58:10 +0000 (09:58 -0400)]
Add --outdir option. Didn't call it "-d" since
that's already being used for "detailed cpu".
Needed to add extra function for user script
to pass parsed options back to m5 module.
configs/test/fs.py:
configs/test/test.py:
Call setStandardOptions().
src/python/m5/__init__.py:
Add --outdir option.
Add setStandardOptions() so user script can
pass parsed options back to m5 module.
src/sim/main.cc:
Add SWIG-wrappable function to set output dir.
--HG--
extra : convert_revision :
1323bee69ca920c699a1cd1218e15b7b0875c1e5
Steve Reinhardt [Sat, 17 Jun 2006 13:26:08 +0000 (09:26 -0400)]
Minor fixes in comments.
SConstruct:
Fix paths in comments and other minor comment edits.
src/cpu/SConscript:
Fix path in comment.
--HG--
extra : convert_revision :
c02aa9cefd8c5ad791ad2f1653c1554a4aa8ffbd
Kevin Lim [Sat, 17 Jun 2006 01:18:19 +0000 (21:18 -0400)]
Add in some of the commonly used Trace/ExeTrace/Debug options.
src/python/m5/__init__.py:
Add in some of the commonly used Trace/ExeTrace/Debug options. Not terribly clean but it works.
--HG--
extra : convert_revision :
abb3cb4892512483a5031606baabf6540019233c
Kevin Lim [Fri, 16 Jun 2006 22:04:34 +0000 (18:04 -0400)]
Update this with the same option as single_fs.py
--HG--
extra : convert_revision :
778d654f515b6af7c45165b0a9bc5ef0d60f0d19
Kevin Lim [Fri, 16 Jun 2006 21:53:33 +0000 (17:53 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
488b9a9965dd86ca73dc9e510e5b3122cbd357f9
Kevin Lim [Fri, 16 Jun 2006 21:52:15 +0000 (17:52 -0400)]
Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
src/SConscript:
Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
Include the func unit file that's not in the encumbered directory.
--HG--
extra : convert_revision :
9801c606961dd2d62dba190d13a76069992bf241
Kevin Lim [Fri, 16 Jun 2006 21:19:36 +0000 (17:19 -0400)]
Add in exec_context.hh, which is a file for documentation purposes only. It describes the ExecContext interface that the ISA uses to access CPU state. Also #ifdef Erik's old copy code from the decoder so ExecContext doesn't need his two specific copy functions.
src/arch/alpha/isa/decoder.isa:
Surround Erik's old copy code with #ifdefs. This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in).
--HG--
extra : convert_revision :
508ca387757a32bb616e5b4b07af17787a76970e
Kevin Lim [Fri, 16 Jun 2006 21:15:18 +0000 (17:15 -0400)]
Miscellaneous minor fixes.
src/cpu/checker/cpu.cc:
Add in comment.
src/cpu/cpuevent.hh:
Fix up comment.
src/cpu/o3/bpred_unit.cc:
Comment out Ozone instantiations.
src/cpu/o3/dep_graph.hh:
Include destructor.
--HG--
extra : convert_revision :
549454ed11bc2fa49a0627f7fb8f96d00a9be303
Kevin Lim [Fri, 16 Jun 2006 21:08:47 +0000 (17:08 -0400)]
Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.
--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision :
86619baf257b8b7c8955efd447eba56e0d7acd6a
Kevin Lim [Fri, 16 Jun 2006 17:10:47 +0000 (13:10 -0400)]
Checker updates.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
Updates for checker. Output more informative messages on error. Rename some functions. Add in option to warn (and not exit) on load results being incorrect.
src/cpu/checker/cpu_builder.cc:
src/cpu/checker/o3_cpu_builder.cc:
Add in parameter to warn (and not exit) on load result errors.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Renamed checker functin.
--HG--
extra : convert_revision :
d7aa28b8462691d20600f97a7213e2acd91c5665
Korey Sewell [Fri, 16 Jun 2006 02:01:28 +0000 (22:01 -0400)]
Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)
Still need to add some code to fetch & commit stages
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Add nextNPC
--HG--
extra : convert_revision :
120677547d54091411399156bd066ce5baf785f7
Ali Saidi [Thu, 15 Jun 2006 19:05:26 +0000 (15:05 -0400)]
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
45677638b0bb5753f3277c212094cfb9313d4706
Steve Reinhardt [Thu, 15 Jun 2006 15:46:13 +0000 (11:46 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
8a1cd7ff43aa4ebbfce0ff174d2f4ba3f095dd47
Steve Reinhardt [Thu, 15 Jun 2006 15:45:51 +0000 (11:45 -0400)]
Get Port stuff working with full-system scripts.
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.
configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.
--HG--
extra : convert_revision :
4816d05ead0de520748aace06dbd1911a33f0af8
Korey Sewell [Thu, 15 Jun 2006 05:00:15 +0000 (01:00 -0400)]
Mips Code Cleanup:
Fix some author stuff and copyright dates
Take out full system code
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
copyright info
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/control.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/process.cc:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/stacktrace.hh:
copyright 2006
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
copyright 2006
take out full system
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/regfile.hh:
copyright 2006
use FloatRegVal
src/arch/mips/regfile/int_regfile.hh:
copyright 2006
move HI/LO to types.hh
src/arch/mips/types.hh:
copyright 2006
typedef FloatRegVal
--HG--
extra : convert_revision :
1d0d72cd655a4e28622745a6c6b06349da533a1d
Korey Sewell [Thu, 15 Jun 2006 02:01:36 +0000 (22:01 -0400)]
tried to undo change and it didnt work so might as well put it back
--HG--
extra : convert_revision :
9793917e8a3e4d30f59ff469e4f08da96ce001f9
Korey Sewell [Wed, 14 Jun 2006 23:53:36 +0000 (19:53 -0400)]
change back, BK is acting up
--HG--
extra : convert_revision :
11fd5ebbca0408b357e9186d1b3722eb571e874e
Korey Sewell [Wed, 14 Jun 2006 23:45:15 +0000 (19:45 -0400)]
add cycle to exit message
src/arch/mips/isa/formats/trap.isa:
Take out fix that tried to fix trap
instruction disassembly. It forces bad
compile ..
configs/test/test.py:
add 'cycle' to exit message
--HG--
extra : convert_revision :
568877797fd2806416b4cbb388cc3f7eb2492627
Korey Sewell [Wed, 14 Jun 2006 23:31:21 +0000 (19:31 -0400)]
-luxc1 fix
-noop templates
-trap disassembly
src/arch/mips/isa/decoder.isa:
luxc1 uses doubleword, not single
src/arch/mips/isa/formats/int.isa:
use new nop decode template
src/arch/mips/isa/formats/mem.isa:
Noop templates
src/arch/mips/isa/formats/noop.isa:
redo noop templates
src/arch/mips/isa/formats/trap.isa:
fix for trap disassembly
--HG--
extra : convert_revision :
56f13e88abdcbd03ab828cff5d775c993157ae96
Ali Saidi [Wed, 14 Jun 2006 20:12:56 +0000 (16:12 -0400)]
add a comment that should be able to pass --help after config file
--HG--
extra : convert_revision :
0229d0c2f4f2615fa744561f32773b4c8160e81a
Korey Sewell [Wed, 14 Jun 2006 18:43:45 +0000 (14:43 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision :
9b5b1419e8e22bce16ed97fc02c2008ca0181afc
Kevin Lim [Wed, 14 Jun 2006 17:12:41 +0000 (13:12 -0400)]
Minor code cleanup of BaseDynInst.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Minor code cleanup by putting several bools into a bitset instead.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Changed around some things in BaseDynInst.
--HG--
extra : convert_revision :
1db363d69a863cc8744cc9f9ec542ade8472eb42
Steve Reinhardt [Wed, 14 Jun 2006 03:19:42 +0000 (23:19 -0400)]
Merge zizzer:/bk/newmem
into vm1.(none):/home/stever/bk/newmem
--HG--
extra : convert_revision :
6ebb12890c516a11733a04041f29c9964267a5ca
Steve Reinhardt [Wed, 14 Jun 2006 03:19:28 +0000 (23:19 -0400)]
Move SimObject creation and Port connection loops
into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.
configs/test/fs.py:
configs/test/test.py:
Rewrite for new port connector syntax.
src/SConscript:
Remove unneeded files:
- mem/connector.*
- sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
Allow getPort() to take an optional index to
support vector ports (eventually).
src/python/m5/__init__.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
src/python/m5/config.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Add support for declaring and connecting MemObject
ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
ConfigNodes are gone; builder just gets the
name of a .ini file section now.
src/sim/main.cc:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Split remaining initialization operations into two parts,
loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
SimObject resolution done globally in Python now
(not via ConfigNode hierarchy).
src/sim/sim_object.cc:
Remove unneeded #include.
--HG--
extra : convert_revision :
2fa4001eaaec0c9a4231ef6e854f8e156d930dfe
Kevin Lim [Wed, 14 Jun 2006 02:40:02 +0000 (22:40 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
5c0e56572c5ca14e0c9a7ac52b0453026e48b336
Kevin Lim [Wed, 14 Jun 2006 02:39:31 +0000 (22:39 -0400)]
Add in a few global options. Feel free to rename them, they're just the first thing that came to mind.
src/python/m5/__init__.py:
Add in a few global options.
--HG--
extra : convert_revision :
e0dba78dd60f565a2e5cbda2cd6cf221bb3f4688
Kevin Lim [Wed, 14 Jun 2006 02:35:05 +0000 (22:35 -0400)]
Minor updates for stats.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch.hh:
Update stats comments.
src/cpu/o3/fetch_impl.hh:
Differentiate stats.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
Update for stats.
src/cpu/o3/lsq.hh:
LSQ now has stats.
src/cpu/o3/lsq_impl.hh:
Register stats of all LSQ units.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Add in stats.
--HG--
extra : convert_revision :
7672ecf3c02515b268c28d5a986af1432197654a
Ali Saidi [Tue, 13 Jun 2006 20:53:26 +0000 (16:53 -0400)]
allow long opts to m5 and add a help flag back.
--HG--
extra : convert_revision :
279cf97fe2e3098e2fe9c568c0336f97e41a14e4
Kevin Lim [Tue, 13 Jun 2006 18:39:05 +0000 (14:39 -0400)]
Make syscalls serialize after instructions so they work properly on the new CPU model.
--HG--
extra : convert_revision :
c2cea5771e41d3c97d0e44559316363718d89abd
Kevin Lim [Tue, 13 Jun 2006 18:37:50 +0000 (14:37 -0400)]
Add itb and dtb to checker when in full system mode.
--HG--
extra : convert_revision :
6e272d484d04b018e7d48e2878ae3e21e8dc571e
Kevin Lim [Tue, 13 Jun 2006 18:15:24 +0000 (14:15 -0400)]
Add in DetailedCPU to test.
--HG--
extra : convert_revision :
98c67b45af239e1cf5bad6888da6577a4c3bb45d
Korey Sewell [Tue, 13 Jun 2006 16:07:48 +0000 (12:07 -0400)]
Merge zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision :
78ef94172884c2db0f591c54657b28be5be7f61c
Kevin Lim [Tue, 13 Jun 2006 15:58:05 +0000 (11:58 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
1a00a3970c6064cb59cd2f788094569fc431bf70
Kevin Lim [Tue, 13 Jun 2006 15:38:16 +0000 (11:38 -0400)]
Compile fix.
--HG--
extra : convert_revision :
20649b0b9b9c496aae22c19926c1166c8c0cc821
Kevin Lim [Mon, 12 Jun 2006 23:15:14 +0000 (19:15 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
349dbc2a39eba7fa5019c811123a643a41fdc6ff
Kevin Lim [Mon, 12 Jun 2006 23:11:38 +0000 (19:11 -0400)]
Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
Fixes for checker.
--HG--
extra : convert_revision :
b0ec8f3c4a10453a567cd6691283fc498403795e
Kevin Lim [Mon, 12 Jun 2006 23:05:48 +0000 (19:05 -0400)]
Fix output messages.
src/cpu/o3/decode_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix output message.
--HG--
extra : convert_revision :
f226b84d0e15f275286b1ed078d341831370322b
Kevin Lim [Mon, 12 Jun 2006 23:04:42 +0000 (19:04 -0400)]
Clean up/shift some code around.
src/cpu/base_dyn_inst.cc:
Clean up some code and update.
src/cpu/base_dyn_inst.hh:
Clean up some code and update with more descriptive function names.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
Remove unused parameters.
src/cpu/o3/commit_impl.hh:
Remove unused parameters, also set squashCounter directly to the counted number of squashes.
src/cpu/o3/fetch_impl.hh:
Update for function name changes.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
Remove unused parameter, move some code into a function.
--HG--
extra : convert_revision :
45abd77ad43dde2e93c2e53c4738c90ba8352a1d
Kevin Lim [Mon, 12 Jun 2006 22:59:24 +0000 (18:59 -0400)]
Fix compile error.
--HG--
extra : convert_revision :
334f5033f5a3a303bfaec3a3acfbd36f205efe86
Kevin Lim [Mon, 12 Jun 2006 22:58:29 +0000 (18:58 -0400)]
Fix memory leak.
src/arch/alpha/ev5.cc:
Fix memory leak. The faults are refcounted, but that only works if you're actually assigning them to a RefCountingPtr.
--HG--
extra : convert_revision :
9a57963eb5d5d86c16023bfedb0fb5ccdbe7efaa
Korey Sewell [Mon, 12 Jun 2006 22:16:05 +0000 (18:16 -0400)]
Merge zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision :
7ac7b9c9288e4940899766cd2dd55ef793d48d4d
Kevin Lim [Mon, 12 Jun 2006 21:53:57 +0000 (17:53 -0400)]
Merge fixes to make full system compile and run.
src/arch/alpha/linux/system.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/sim/system.cc:
Merge fixes.
--HG--
extra : convert_revision :
aa3326c0ebf54da9ab1dbd2d9877da41ca487082
Kevin Lim [Mon, 12 Jun 2006 20:42:56 +0000 (16:42 -0400)]
Removed syscall function from thread_context.hh. ThreadContext is the interface for external, non-CPU objects to access the thread, so they probably shouldn't be able to call syscall(). The case it was being used for was already handled by the ISA code.
src/arch/sparc/faults.cc:
src/cpu/thread_context.hh:
Fix for merge problems.
--HG--
extra : convert_revision :
05a7a2d6e45099fcf36d113da2e52450d892a72c
Korey Sewell [Mon, 12 Jun 2006 20:19:18 +0000 (16:19 -0400)]
Merge zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision :
18a381fa230f2ef6d027359ffd619e3ae75cd446