Immanuel, Yehowshua U [Tue, 5 May 2020 18:20:35 +0000 (18:20 +0000)]
Re: [libre-riscv-dev] Finished Scoreboard
Yehowshua [Tue, 5 May 2020 18:18:51 +0000 (14:18 -0400)]
Re: [libre-riscv-dev] Finished Scoreboard
Michael Nolan [Tue, 5 May 2020 17:33:27 +0000 (13:33 -0400)]
[libre-riscv-dev] CORDIC importance
bugzilla-daemon [Tue, 5 May 2020 17:30:44 +0000 (17:30 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 17:02:11 +0000 (17:02 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 16:28:32 +0000 (16:28 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
Luke Kenneth Casson Leighton [Tue, 5 May 2020 16:26:14 +0000 (17:26 +0100)]
Re: [libre-riscv-dev] Finished Scoreboard
bugzilla-daemon [Tue, 5 May 2020 16:16:00 +0000 (16:16 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 16:14:13 +0000 (16:14 +0000)]
[libre-riscv-dev] [Bug 301] New: design a micro-op subsystem that works with scoreboards
bugzilla-daemon [Tue, 5 May 2020 16:12:25 +0000 (16:12 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 16:03:05 +0000 (16:03 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 15:13:16 +0000 (15:13 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 15:10:57 +0000 (15:10 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 15:10:21 +0000 (15:10 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 15:00:48 +0000 (15:00 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 15:00:32 +0000 (15:00 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:58:40 +0000 (14:58 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:55:26 +0000 (14:55 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:53:32 +0000 (14:53 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:52:35 +0000 (14:52 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:42:02 +0000 (14:42 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:29:33 +0000 (14:29 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
Luke Kenneth Casson Leighton [Tue, 5 May 2020 14:26:11 +0000 (15:26 +0100)]
Re: [libre-riscv-dev] global network of developers
Luke Kenneth Casson Leighton [Tue, 5 May 2020 14:24:44 +0000 (15:24 +0100)]
Re: [libre-riscv-dev] daily status update 05may2020
Luke Kenneth Casson Leighton [Tue, 5 May 2020 14:23:39 +0000 (15:23 +0100)]
Re: [libre-riscv-dev] daily status update 05may2020
bugzilla-daemon [Tue, 5 May 2020 14:06:42 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 14:04:06 +0000 (14:04 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon [Tue, 5 May 2020 13:17:18 +0000 (13:17 +0000)]
[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
Yehowshua [Tue, 5 May 2020 13:10:49 +0000 (09:10 -0400)]
Re: [libre-riscv-dev] global network of developers
Yehowshua [Tue, 5 May 2020 13:10:19 +0000 (09:10 -0400)]
Re: [libre-riscv-dev] global network of developers
Yehowshua [Tue, 5 May 2020 13:07:50 +0000 (09:07 -0400)]
Re: [libre-riscv-dev] daily status update 05may2020
Yehowshua [Tue, 5 May 2020 13:02:45 +0000 (09:02 -0400)]
Re: [libre-riscv-dev] daily status update 05may2020
Luke Kenneth Casson Leighton [Tue, 5 May 2020 12:51:23 +0000 (13:51 +0100)]
Re: [libre-riscv-dev] global network of developers
Luke Kenneth Casson Leighton [Tue, 5 May 2020 11:09:59 +0000 (12:09 +0100)]
Re: [libre-riscv-dev] global network of developers
Luke Kenneth Casson Leighton [Tue, 5 May 2020 10:47:32 +0000 (11:47 +0100)]
[libre-riscv-dev] daily status update 05may2020
bugzilla-daemon [Mon, 4 May 2020 20:11:22 +0000 (20:11 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Mon, 4 May 2020 13:14:26 +0000 (14:14 +0100)]
Re: [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
bugzilla-daemon [Mon, 4 May 2020 13:12:38 +0000 (13:12 +0000)]
[libre-riscv-dev] [Bug 300] Documentation for the SOC
Yehowshua [Mon, 4 May 2020 13:10:44 +0000 (09:10 -0400)]
Re: [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
bugzilla-daemon [Mon, 4 May 2020 13:09:55 +0000 (13:09 +0000)]
[libre-riscv-dev] [Bug 300] New: Documentation for the SOC
Luke Kenneth Casson Leighton [Mon, 4 May 2020 12:59:48 +0000 (13:59 +0100)]
Re: [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
bugzilla-daemon [Mon, 4 May 2020 10:21:30 +0000 (10:21 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Mon, 4 May 2020 09:29:09 +0000 (10:29 +0100)]
[libre-riscv-dev] global network of developers
Luke Kenneth Casson Leighton [Mon, 4 May 2020 09:23:30 +0000 (10:23 +0100)]
Re: [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:33:30 +0000 (09:33 +0100)]
Re: [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
Yehowshua [Mon, 4 May 2020 02:13:30 +0000 (22:13 -0400)]
[libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation
bugzilla-daemon [Sun, 3 May 2020 14:07:06 +0000 (14:07 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sun, 3 May 2020 13:23:01 +0000 (13:23 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sun, 3 May 2020 11:58:32 +0000 (11:58 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Luke Kenneth Casson Leighton [Sun, 3 May 2020 11:02:11 +0000 (12:02 +0100)]
Re: [libre-riscv-dev] experimental code & monorepo
Jacob Lifshay [Sun, 3 May 2020 04:49:15 +0000 (21:49 -0700)]
[libre-riscv-dev] experimental code & monorepo
Luke Kenneth Casson Leighton [Sun, 3 May 2020 00:21:45 +0000 (01:21 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sun, 3 May 2020 00:09:46 +0000 (20:09 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sun, 3 May 2020 00:08:53 +0000 (20:08 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 23:34:52 +0000 (00:34 +0100)]
Re: [libre-riscv-dev] Needed Subset of POWER
Luke Kenneth Casson Leighton [Sat, 2 May 2020 23:24:38 +0000 (00:24 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sat, 2 May 2020 22:07:02 +0000 (18:07 -0400)]
[libre-riscv-dev] Needed Subset of POWER
Yehowshua [Sat, 2 May 2020 20:59:03 +0000 (16:59 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 19:30:22 +0000 (20:30 +0100)]
Re: [libre-riscv-dev] GItlab For SOC repo
Yehowshua [Sat, 2 May 2020 18:47:32 +0000 (14:47 -0400)]
Re: [libre-riscv-dev] GItlab For SOC repo
Yehowshua [Sat, 2 May 2020 18:45:20 +0000 (14:45 -0400)]
[libre-riscv-dev] GItlab For SOC repo
bugzilla-daemon [Sat, 2 May 2020 15:02:55 +0000 (15:02 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sat, 2 May 2020 13:15:16 +0000 (13:15 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sat, 2 May 2020 05:28:25 +0000 (05:28 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Yehowshua [Sat, 2 May 2020 04:42:44 +0000 (00:42 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 04:40:39 +0000 (05:40 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
bugzilla-daemon [Sat, 2 May 2020 04:00:41 +0000 (04:00 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Yehowshua [Sat, 2 May 2020 03:09:13 +0000 (23:09 -0400)]
[libre-riscv-dev] Documenting the SOC tree Repository
bugzilla-daemon [Sat, 2 May 2020 02:01:39 +0000 (02:01 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 23:39:59 +0000 (23:39 +0000)]
[libre-riscv-dev] [Bug 299] New: improve memory clash detection
bugzilla-daemon [Fri, 1 May 2020 23:21:10 +0000 (23:21 +0000)]
[libre-riscv-dev] [Bug 298] consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
bugzilla-daemon [Fri, 1 May 2020 23:04:36 +0000 (23:04 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 22:00:08 +0000 (22:00 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 21:55:15 +0000 (21:55 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
Hendrik Boom [Fri, 1 May 2020 21:43:22 +0000 (17:43 -0400)]
Re: [libre-riscv-dev] Verilog book
bugzilla-daemon [Fri, 1 May 2020 21:28:24 +0000 (21:28 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 20:51:33 +0000 (20:51 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 20:23:37 +0000 (20:23 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Hendrik Boom [Fri, 1 May 2020 20:08:57 +0000 (16:08 -0400)]
[libre-riscv-dev] Verilog book
bugzilla-daemon [Fri, 1 May 2020 19:17:25 +0000 (19:17 +0000)]
[libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
bugzilla-daemon [Fri, 1 May 2020 19:12:35 +0000 (19:12 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Luke Kenneth Casson Leighton [Fri, 1 May 2020 19:09:19 +0000 (20:09 +0100)]
Re: [libre-riscv-dev] sum-addressed decoder
bugzilla-daemon [Fri, 1 May 2020 18:54:22 +0000 (18:54 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 18:33:05 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 18:19:03 +0000 (18:19 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 14:35:42 +0000 (14:35 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
Jacob Lifshay [Fri, 1 May 2020 14:32:10 +0000 (07:32 -0700)]
[libre-riscv-dev] sum-addressed decoder
bugzilla-daemon [Fri, 1 May 2020 13:33:18 +0000 (13:33 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 1 May 2020 13:31:54 +0000 (13:31 +0000)]
[libre-riscv-dev] [Bug 297] New: nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 13:27:55 +0000 (13:27 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Fri, 1 May 2020 13:22:33 +0000 (14:22 +0100)]
Re: [libre-riscv-dev] sun opensparc t2
Luke Kenneth Casson Leighton [Fri, 1 May 2020 11:24:24 +0000 (12:24 +0100)]
Re: [libre-riscv-dev] load/store execution queue idea
bugzilla-daemon [Fri, 1 May 2020 05:03:14 +0000 (05:03 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 03:02:55 +0000 (03:02 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Jacob Lifshay [Fri, 1 May 2020 02:53:59 +0000 (19:53 -0700)]
[libre-riscv-dev] load/store execution queue idea
bugzilla-daemon [Fri, 1 May 2020 02:10:10 +0000 (02:10 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 02:10:01 +0000 (02:10 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 02:09:45 +0000 (02:09 +0000)]
[libre-riscv-dev] [Bug 296] New: idea: cyclic buffer between FUs and register file
Jacob Lifshay [Thu, 30 Apr 2020 22:50:10 +0000 (15:50 -0700)]
[libre-riscv-dev] sun opensparc t2
bugzilla-daemon [Thu, 30 Apr 2020 22:44:32 +0000 (22:44 +0000)]
[libre-riscv-dev] [Bug 295] pay attention to these insights
projects / libre-riscv-dev.git / log