Geoffrey Blake [Sun, 22 Nov 2015 10:10:19 +0000 (05:10 -0500)]
arm, dev: Fix flash model serialization code typos
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint. This patch fixes these typos.
Nathanael Premillieu [Sun, 22 Nov 2015 10:10:19 +0000 (05:10 -0500)]
cpu: Fix base FP and CC register index in o3 insertThread()
Note that the method is not used, and could possibly be deleted.
Nathanael Premillieu [Sun, 22 Nov 2015 10:10:18 +0000 (05:10 -0500)]
arm: Fix fplib 128-bit shift operators
Appease clang.
Andreas Hansson [Sun, 22 Nov 2015 10:10:17 +0000 (05:10 -0500)]
config: Minor fixes to the DRAM utilisation sweep
Andreas Hansson [Sun, 22 Nov 2015 10:10:16 +0000 (05:10 -0500)]
cpu: Fix memory leak in traffic generator
In cases where we discard the packet, make sure to also delete it and
the associated request.
Andreas Sandberg [Fri, 20 Nov 2015 20:50:17 +0000 (14:50 -0600)]
cpu: Enforce 1 interrupt controller per thread
Consider it a fatal configuration error if the number of interrupt
controllers doesn't match the number of threads in an SMT
configuration.
Nilay Vaish [Mon, 16 Nov 2015 11:10:45 +0000 (05:10 -0600)]
Nilay Vaish [Mon, 16 Nov 2015 11:08:57 +0000 (05:08 -0600)]
stats: updates due to recent chagnesets
Swapnil Haria [Mon, 16 Nov 2015 11:08:54 +0000 (05:08 -0600)]
x86: Invalidating TLB entry on page fault
As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel. This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit
e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.
Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11
Bjoern A. Zeeb [Mon, 16 Nov 2015 10:58:39 +0000 (04:58 -0600)]
x86: cpuid: add family to warn() message
doCpuid() has to identical warn messages about unimplemented functions. Add
the family to the log message to make them distinguishable.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Bjoern A. Zeeb [Mon, 16 Nov 2015 10:58:39 +0000 (04:58 -0600)]
x86: pagetable walker: fix typo in comment
Palle Lyckegaard [Mon, 16 Nov 2015 10:58:39 +0000 (04:58 -0600)]
sparc: Make remote debugging with gdb work
Remove sparc V8 TBR register from list of registers since it is not part of
sparc V9. This brings the number of registers in sync with what gdb expects
Without this patch gdb complains about receoved packet too long.
with this patch gdb is able to work properly with gem5 for remote debugging.
Note: gdb is version 7.8
Note: gdb is configured with --target=sparc64-sun-solaris2.8
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Mon, 16 Nov 2015 10:58:29 +0000 (04:58 -0600)]
stats: remove wb_penalized and wb_penalized_rate
Nilay Vaish [Mon, 16 Nov 2015 10:57:52 +0000 (04:57 -0600)]
o3: drop unused statistic wbPenalized and wbPenalizedRate
Joe Gross [Sun, 15 Nov 2015 22:56:43 +0000 (17:56 -0500)]
sim: support for distcc pump server settings
Andreas Sandberg [Sun, 15 Nov 2015 21:28:00 +0000 (21:28 +0000)]
arm: Add missing explicit overrides for classic caches
Make clang when compiling on OSX.
Brad Beckmann [Mon, 20 Jul 2015 14:15:20 +0000 (09:15 -0500)]
ruby: added stl vector of ints to be used by SLICC
Tony Gutierrez [Fri, 13 Nov 2015 22:30:58 +0000 (17:30 -0500)]
slicc: fixes for the Address to Addr changeset (11025)
misc changes now that Address has become Addr including int to address util
function
Joe Gross [Fri, 13 Nov 2015 22:30:56 +0000 (17:30 -0500)]
ruby: add BoolVec
The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: add boolean to disable PacketQueue's size sanity check
the sanity check, while generally useful for exposing memory system bugs,
may be spurious with respect to GPU workloads, which may generate many more
requests than typical CPU workloads. the large number of requests generated
by the GPU may cause the req/resp queues to back up, thus queueing more than
100 packets.
Anthony Gutierrez [Fri, 13 Nov 2015 22:03:48 +0000 (17:03 -0500)]
misc: ignore object files and static libs in util/m5
Andreas Sandberg [Wed, 11 Nov 2015 10:18:38 +0000 (10:18 +0000)]
dev, arm: Initialized the iccrpr register in the GIC
The IICRPR register in the GIC is currently not being initialized when
the GIC is instantiated. Initialize to the value mandated by the
architecture specification.
Sascha Bischoff [Thu, 5 Nov 2015 09:40:12 +0000 (09:40 +0000)]
dev: Add basic checkpoint support to VirtIO9PProxy device
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
Andreas Sandberg [Mon, 9 Nov 2015 13:44:15 +0000 (13:44 +0000)]
dev: Remove unused header includes
Devices should never need to include dev/pciconfall.hh.
--HG--
extra : amend_source :
3a6e56485d432b49e2af22407982fa785c0ccb68
Andreas Sandberg [Mon, 9 Nov 2015 13:44:04 +0000 (13:44 +0000)]
dev: Don't access the platform directly in PCI devices
Cleanup PCI devices to avoid using the PciDevice::platform pointer
directly. The PCI-specific functionality provided by the Platform
should be accessed through the wrappers in PciDevice.
Andreas Hansson [Fri, 6 Nov 2015 08:26:50 +0000 (03:26 -0500)]
stats: Update stats to match cache changes
Andreas Hansson [Fri, 6 Nov 2015 08:26:44 +0000 (03:26 -0500)]
config: Update memtest to stress test clean writebacks
This patch adds yet another twist to the memtest cache hierarchy, in that
the writeback_clean option is toggled at every level to match the
clusivity of the downstream cache.
Andreas Hansson [Fri, 6 Nov 2015 08:26:43 +0000 (03:26 -0500)]
mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.
The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.
The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py
Andreas Hansson [Fri, 6 Nov 2015 08:26:42 +0000 (03:26 -0500)]
config: Update memtest to stress test cache clusivity
This patch adds an new twist to the memtest cache hierarchy, in that
it switches from mostly inclusive to mostly exclusive at every level
in the tree. This has helped weed out plenty issues, and serves as a
good stress tests.
Andreas Hansson [Fri, 6 Nov 2015 08:26:41 +0000 (03:26 -0500)]
mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.
The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.
This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.
Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.
The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
Ali Jafri [Fri, 6 Nov 2015 08:26:40 +0000 (03:26 -0500)]
mem: Avoid unnecessary snoops on writebacks and clean evictions
This patch optimises the handling of writebacks and clean evictions
when using a snoop filter. Instead of snooping into the caches to
determine if the block is cached or not, simply set the status based
on the snoop-filter result.
Andreas Hansson [Fri, 6 Nov 2015 08:26:38 +0000 (03:26 -0500)]
mem: Order packet queue only on matching addresses
Instead of conservatively enforcing order for all packets, which may
negatively impact the simulated-system performance, this patch updates
the packet queue such that it only applies the restriction if there
are already packets with the same address in the queue.
The basic need for the order enforcement is due to coherency
interactions where requests/responses to the same cache line must not
over-take each other. We rely on the fact that any packet that needs
order enforcement will have a block-aligned address. Thus, there is no
need for the queue to know about the cacheline size.
Ali Jafri [Fri, 6 Nov 2015 08:26:37 +0000 (03:26 -0500)]
mem: Enforce insertion order on the cache response path
This patch enforces insertion order transmission of packets on the
response path in the cache. Note that the logic to enforce order is
already present in the packet queue, this patch simply turns it on for
queues in the response path.
Without this patch, there are corner cases where a request-response is
faster than a response-response forwarded through the cache. This
violation of queuing order causes problems in the snoop filter leaving
it with inaccurate information. This causes assert failures in the
snoop filter later on.
A follow on patch relaxes the order enforcement in the packet queue to
limit the performance impact.
Andreas Hansson [Fri, 6 Nov 2015 08:26:36 +0000 (03:26 -0500)]
mem: Use the packet delays and do not just zero them out
This patch updates the I/O devices, bridge and simple memory to take
the packet header and payload delay into account in their latency
calculations. In all cases we add the header delay, i.e. the
accumulated pipeline delay of any crossbars, and the payload delay
needed for deserialisation of any payload.
Due to the additional unknown latency contribution, the packet queue
of the simple memory is changed to use insertion sorting based on the
time stamp. Moreover, since the memory hands out exclusive (non
shared) responses, we also need to ensure ordering for reads to the
same address.
Andreas Hansson [Fri, 6 Nov 2015 08:26:35 +0000 (03:26 -0500)]
mem: Align rules for sinking inhibited packets at the slave
This patch aligns how the memory-system slaves, i.e. the various
memory controllers and the bridge, identify and deal with sinking of
inhibited packets that are only useful within the coherent part of the
memory system.
In the future we could shift the onus to the crossbar, and add a
parameter "is_point_of_coherence" that would allow it to sink the
aforementioned packets.
Andreas Hansson [Fri, 6 Nov 2015 08:26:33 +0000 (03:26 -0500)]
mem: Do not treat CleanEvict as a write operation
This patch changes the CleanEvict command type to not be considered a
write. Initially it was made a zero-sized write to match the writeback
command, but as things developed it became clear that it causes more
problems than it solves. For example, the memory modules (and bridge)
should not consider the CleanEvict as a write, but instead discard
it. With this patch it will be neither a read, nor write, and as it
does not need a response the slave will simply sink it.
Andreas Hansson [Fri, 6 Nov 2015 08:26:21 +0000 (03:26 -0500)]
mem: Unify delayed packet deletion
This patch unifies how we deal with delayed packet deletion, where the
receiving slave is responsible for deleting the packet, but the
sending agent (e.g. a cache) is still relying on the pointer until the
call to sendTimingReq completes. Previously we used a mix of a
deletion vector and a construct using unique_ptr. With this patch we
ensure all slaves use the latter approach.
Andreas Hansson [Fri, 6 Nov 2015 08:26:16 +0000 (03:26 -0500)]
misc: Appease clang static analyzer
A few minor fixes to issues identified by the clang static analyzer.
Andreas Sandberg [Fri, 6 Nov 2015 08:26:09 +0000 (03:26 -0500)]
mem: Check the XBar's port queues on functional snoops
The CoherentXBar currently doesn't check its queued slave ports when
receiving a functional snoop. This caused data corruption in cases
when a modified cache lines is forwarded between two caches.
Add the required functional calls into the queued slave ports.
Nilay Vaish [Wed, 4 Nov 2015 18:36:28 +0000 (12:36 -0600)]
configs: fix bug introduced due to
276ad9121192
I had made a typo in changeset
276ad9121192. This changeset fixes it
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:58 +0000 (12:17 -0600)]
mem: hmc: minor fixes
This patch performs two minor fixes to DRAMCtrl.py and xbar.hh in favor of the
HMC patch series.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:57 +0000 (12:17 -0600)]
mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube (HMC).
SerialLink is a simple variation of the Bridge class, with the ability to
account for the latency of packet serialization. Also trySendTiming has been
modified to correctly model bandwidth.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:56 +0000 (12:17 -0600)]
mem: hmc: adds controller
This patch models a simple HMC Controller. It simply schedules the incoming
packets to HMC Serial Links using a round robin mechanism. This patch should
be applied in series with other patches modeling a complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Erfan Azarkhish [Tue, 3 Nov 2015 18:17:56 +0000 (12:17 -0600)]
mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It
highly reuses the existing components in gem5's general memory system with some
small modifications. This changeset requires additional patches to model a
complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Palle Lyckegaard [Tue, 3 Nov 2015 18:17:55 +0000 (12:17 -0600)]
sparc: add missing parameter to makeSparcSystem()
makeSparcSystem() in configs/common/FSConfig.py is missing the cmdLine
parameter Without the parameter the simulation fails to start. With the
parameter the simulation starts properly.
Nathanael Premillieu [Thu, 29 Oct 2015 12:48:26 +0000 (08:48 -0400)]
arm: Add secure flag to TableWalker request when needed
Sascha Bischoff [Thu, 29 Oct 2015 12:48:25 +0000 (08:48 -0400)]
dev: Fix segfault in flash device
Fix a bug in which the flash device would write out of bounds and
could either trigger a segfault and corrupt the memory of other
objects. This was caused by using pageSize in the place of
pagesPerBlock when running the garbage collector.
Also, added an assert to flag this condition in the future.
Sascha Bischoff [Thu, 29 Oct 2015 12:48:24 +0000 (08:48 -0400)]
dev: Fix draining for UFSHostDevice and FlashDevice
This patch fixes the drain logic for the UFSHostDevice and the
FlashDevice. In the case of the FlashDevice, the logic for CheckDrain
needed to be reversed, whilst in the case of the UFSHostDevice check
drain was never being called. In both cases the system would never
complete draining if the initial attampt to drain failed.
Victor Garcia [Thu, 29 Oct 2015 12:48:23 +0000 (08:48 -0400)]
kvm, arm: Fix compilation errors due to API changes
The checkpoint changes, along with the SMT patches have changed a
number of APIs. Adapt the ArmKvmCPU accordingly.
Andreas Hansson [Thu, 29 Oct 2015 12:48:20 +0000 (08:48 -0400)]
mem: Clarify cache MSHR handling on fill
This patch addresses the upgrading of deferred targets in the MSHR,
and makes it clearer by explicitly calling out what is happening
(deferred targets are promoted if we get exclusivity without asking
for it).
Boris Shingarov [Sun, 25 Oct 2015 23:01:52 +0000 (16:01 -0700)]
power: Implement Remote GDB
Andreas Hansson [Fri, 23 Oct 2015 13:51:12 +0000 (09:51 -0400)]
x86: Add missing explicit overrides for X86 devices
Make clang >= 3.5 happy when compiling build/X86/gem5.opt on OSX.
Andreas Hansson [Fri, 23 Oct 2015 13:51:11 +0000 (09:51 -0400)]
arm: Add missing explicit overrides for ARM devices
Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX.
Andreas Hansson [Wed, 14 Oct 2015 17:32:28 +0000 (13:32 -0400)]
mem: Pass snoop retries through the CommMonitor
Allow the monitor to be placed after a snooping port, and do not fail
on snoop retries, but instead pass them on to the slave port.
Nilay Vaish [Wed, 14 Oct 2015 05:29:43 +0000 (00:29 -0500)]
ruby: profiler: provide the number of vnets through ruby system
The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().
Nilay Vaish [Wed, 14 Oct 2015 05:29:39 +0000 (00:29 -0500)]
ruby: remove unused functionalRead() function.
Not required since functional reads cannot rely on messages that are inflight.
Nilay Vaish [Wed, 14 Oct 2015 05:29:38 +0000 (00:29 -0500)]
ruby: garnet: flexible: refactor flit
Andreas Hansson [Mon, 12 Oct 2015 08:08:01 +0000 (04:08 -0400)]
misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.
As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
Andreas Hansson [Mon, 12 Oct 2015 08:07:59 +0000 (04:07 -0400)]
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
Joel Hestness [Sat, 10 Oct 2015 21:45:41 +0000 (16:45 -0500)]
stats: Update for UDelayEvent quiesce change
Joel Hestness [Sat, 10 Oct 2015 21:45:38 +0000 (16:45 -0500)]
sim: Don't quiesce UDelayEvents with 0 latency
ARM uses UDelayEvents to emulate kernel __*udelay functions and speed up
simulation. UDelayEvents call Pseudoinst::quiesceNs to quiesce the system for
a specified delay. Changeset 10341:
0b4d10f53c2d introduced the requirement
that any quiesce process that is started must also be completed by scheduling
an EndQuiesceEvent. This change causes the CPU to hang if an IsQuiesce
instruction is executed, but the corresponding EndQuiesceEvent is not
scheduled.
Changeset 11058:
d0934b57735a introduces a fix for uses of PseudoInst::quiesce*
that would conditionally execute the EndQuiesceEvent. ARM UDelayEvents specify
quiesce period of 0 ns (src/arch/arm/linux/system.cc), so changeset 11058
causes these events to now execute full quiesce processes, greatly increasing
the total instructions executed in kernel delay loops and slowing simulation.
This patch updates the UDelayEvent to conditionally execute
PseudoInst::quiesceNs (**a quiesce operation**) only if the specified
delay is >0 ns. The result is ARM delay loops no longer execute instructions
for quiesce handling, and regression time returns to normal.
Rekai Gonzalez Alberquilla [Fri, 9 Oct 2015 19:50:54 +0000 (14:50 -0500)]
isa: Add parameter to pick different decoder inside ISA
The decoder is responsible for splitting instructions in micro
operations (uops). Given that different micro architectures may split
operations differently, this patch allows to specify which micro
architecture each isa implements, so different cores in the system can
split instructions differently, also decoupling uop splitting
(microArch) from ISA (Arch). This is done making the decodification
calls templates that receive a type 'DecoderFlavour' that maps the
name of the operation to the class that implements it. This way there
is only one selection point (converting the command line enum to the
appropriate DecodeFeatures object). In addition, there is no explicit
code replication: template instantiation hides that, and the compiler
should be able to resolve a number of things at compile-time.
Dylan Johnson [Fri, 9 Oct 2015 19:27:09 +0000 (14:27 -0500)]
sim: Add relative break scheduling
Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
arch: clean up isa_parser error handling
Although some decent error messages were getting generated inside
isa_parser.py, they weren't always getting printed because of the
screwy way we were handling exceptions. (Basically an inner
exception would get hidden by an outer exception, and the more
informative inner error message would not get printed.)
Also line numbers were messed up, since they were taken from the
lexer, which is typically a token (or more) ahead of the grammar
rule that's being matched. Using the 'lineno' attribute that
PLY associates with the grammar production is more accurate.
The new LineTracker class extends lineno to track filenames as
well as line numbers.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
sim: add ExecMacro to Exec* compound debug flags
Really should have been there in the first place, IMO.
Makes debugging x86 execution a lot easier.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
sim: print pid in output header
This information is useful if you have a bunch of simulations running
and want to know which one to kill, but you've neglected to take
advantage of the previous patch and embed the pid in your output path.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
x86: implement rcpps and rcpss SSE insts
These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.
This code was basically developed by copying the code for
sqrtps and sqrtss. The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.
Steve Reinhardt [Wed, 7 Oct 2015 00:26:50 +0000 (17:26 -0700)]
x86: implement fild, fucomi, and fucomip x87 insts
fild loads an integer value into the x87 top of stack register.
fucomi/fucomip compare two x87 register values (the latter
also doing a stack pop).
These instructions are used by some versions of GNU libstdc++.
Curtis Dunham [Tue, 6 Oct 2015 23:08:28 +0000 (18:08 -0500)]
ext: fix SST connector
The renamings in changesets
8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and
fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector. This commit repeats those renamings in ext/sst.
Dylan Johnson [Wed, 2 Sep 2015 18:34:19 +0000 (13:34 -0500)]
sim: Add ability to break at specific kernel function
Adds a GDB callable function that sets a breakpoint at
the beginning of a kernel function.
Andreas Sandberg [Mon, 5 Oct 2015 18:13:23 +0000 (13:13 -0500)]
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
Steve Reinhardt [Fri, 2 Oct 2015 05:04:12 +0000 (01:04 -0400)]
stats: update EIO stats for snoop filter changes
Andreas Hansson [Thu, 1 Oct 2015 08:07:15 +0000 (04:07 -0400)]
config: Fix 'learning gem5' configs after SMT push
This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.
Curtis Dunham [Wed, 30 Sep 2015 20:21:55 +0000 (15:21 -0500)]
base: remove Trace::enabled flag
The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is
detected. Having 2 SMT threads share a TLB resulted in these not being
updated as required. This patch adds a thread context identifer to
assist in the invalidation of these variables.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
arm: SMT MPIDR Setting
Changes assignment of the MPIDR for multi-threaded systems only.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu: Add per-thread monitors
Adds per-thread address monitors to support FullSystem SMT.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
Mitch Hayenga [Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)]
cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
cores) caused failures due to the CPU id assignment logic. The comment
about thread assignment (worrying about core 0 not having tid 0) seems
not to be valid given that our configuration scripts initialize them in
order.
This removes that constraint so a heterogenously threaded sytem can work.
Joel Hestness [Tue, 29 Sep 2015 14:28:26 +0000 (09:28 -0500)]
ruby: Fix CacheMemory allocate leak
If a cache entry permission was previously set to NotPresent, but the entry was
not deleted, a following cache allocation can cause the entry to be leaked by
setting the entry pointer to a newly allocated entry. To eliminate this
possibility, check if the new entry is different from the old one, and if so,
delete the old one.
Joel Hestness [Tue, 29 Sep 2015 14:28:26 +0000 (09:28 -0500)]
arch, x86: Delete packet in IntDevice::recvResponse
IntDevice::recvResponse is called from two places in current mainline: (1) the
short circuit path of X86ISA::IntDevice::IntMasterPort::sendMessage for atomic
mode, and (2) the full request->response path to and from the x86 interrupts
device (finally called from MessageMasterPort::recvTimingResp). In the former
case, the packet was deleted correctly, but in the latter case, the packet and
request leak. To fix the leak, move request and packet deletion into IntDevice
inherited class implementations of recvResponse.
Joel Hestness [Tue, 29 Sep 2015 14:28:25 +0000 (09:28 -0500)]
ruby: RubyPort delete snoop requests
In RubyPort::ruby_eviction_callback, prior changes fixed a memory leak caused
by instantiating separate packets for each port that the eviction was forwarded
to. That change, however, left the instantiated request to also leak. Allocate
it on the stack to avoid the leak.
Joel Hestness [Tue, 29 Sep 2015 14:28:25 +0000 (09:28 -0500)]
ruby: Fix memory leak in AbstractController
Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.
Joel Hestness [Tue, 29 Sep 2015 14:25:29 +0000 (09:25 -0500)]
ruby: RubyMemoryControl delete requests
Changes to the RubyMemoryControl removed the dequeue function, which deleted
MemoryNode instances. This results in leaked MemoryNode instances. Correctly
delete these instances.
Joel Hestness [Tue, 29 Sep 2015 14:25:20 +0000 (09:25 -0500)]
syscall_emul: Bandage readlink /proc/self/exe
The recent changeset to readlink() to handle reading the /proc/self/exe link
introduces a number of problems. This patch fixes two:
1) Because readlink() called on /proc/self/exe now uses LiveProcess::progName()
to find the binary path, it will only get the zeroth parameter of the simulated
system command line. However, if a config script also specifies the process'
executable, the executable parameter is used to create the LiveProcess rather
than the zeroth command line parameter. Thus, the zeroth command line parameter
is not necessarily the correct path to the binary executing in the simulated
system. To fix this, add a LiveProcess data member, 'executable', which is
correctly set during instantiation and returned from progName().
2) If a config script allows a user to pass a relative path as the zeroth
simulated system command line parameter or process executable, readlink() will
incorrecly return a relative path when called on '/proc/self/exe'.
/proc/self/exe is always set to a full path, so running benchmarks can fail if
a relative path is returned. To fix this, clean up the handling of
LiveProcess::progName() within readlink() to get the full binary path.
NOTE: This patch still leaves the potential problem that host full path to the
binary bleeds into the simulated system, potentially causing the appearance of
non-deterministic simulated system execution.
Andreas Hansson [Fri, 25 Sep 2015 17:25:34 +0000 (13:25 -0400)]
mem: Add PacketInfo to be used for packet probe points
This patch fixes a use-after-delete issue in the packet probe points
by adding a PacketInfo struct to retain the key fields before passing
the packet onwards. We want to probe the packet after it is
successfully sent, but by that time the fields may be modified, and
the packet may even be deleted.
Amazingly enough the issue has gone undetected for months, and only
recently popped up in our regressions.
Andreas Hansson [Fri, 25 Sep 2015 11:27:03 +0000 (07:27 -0400)]
stats: Update stats to reflect snoop-filter changes
Andreas Hansson [Fri, 25 Sep 2015 11:26:58 +0000 (07:26 -0400)]
mem: Add check for block status on WriteLineReq fill
More checks to help with understanding of functionality.
Andreas Hansson [Fri, 25 Sep 2015 11:26:58 +0000 (07:26 -0400)]
mem: Fix WriteLineReq fill behaviour
This patch fixes issues in the interactions between deferred snoops
and WriteLineReq. More specifically, the patch addresses an issue
where deferred snoops caused assertion failures when being serviced on
the arrival of an InvalidateResp. The response packet was perceived to
be invalidating, when actually it is not for the cache that sent out
the original invalidation request.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Comment clean-up for the snoop filter
Merely fixing up some style issues and adding more comments.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Avoid adding and then removing empty snoop-filter items
This patch tidies up how we access the snoop filter for snoops, and
avoids adding items only to later remove them.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Only track snooping ports in the snoop filter
This patch changes the tracking of ports in the snoop filter to use
local dense port IDs so that we can have 64 snooping ports (rather
than crossbar slave ports). This is achieved by adding a simple
remapping vector that translates the actal port IDs into the local
slave IDs used in the SnoopMask.
Ultimately this patch allows us to scale to much larger systems
without introducing a hierarchy of crossbars.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add snoop filters to L2 crossbars, and check size
This patch adds a snoop filter to the L2XBar. For now we refrain from
globally adding a snoop filter to the SystemXBar, since the latter is
also used in systems without caches. In scenarios without caches the
snoop filter will not see any writeback/clean evicts from the CPU
ports, despite the fact that they are snooping. To avoid inadvertent
use of the snoop filter in these cases we leave it out for now.
A size check is added to the snoop filter, merely to ensure it does
not grow beyond the total capacity of the caches above it. The size
has to be set manually, and a value of 8 MByte is choosen as suitably
high default.
Andreas Hansson [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Store snoop filter lookup result to avoid second lookup
This patch introduces a private member storing the iterator from the
lookupRequest call, such that it can be re-used when the request
eventually finishes. The method previously called updateRequest is
renamed finishRequest to make it more clear that the two functions
must be called together.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add snoops for CleanEvicts and Writebacks in atomic mode
This patch mirrors the logic in timing mode which sends up snoops to
check for cached copies before sending CleanEvicts and Writebacks down
the memory hierarchy. In case there is a copy in a cache above,
discard CleanEvicts and set the BLOCK_CACHED flag in Writebacks so
that writebacks do not reset the cache residency bit in the snoop
filter below.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add CleanEvict and Writeback support to snoop filters
This patch adds the functionality to properly track CleanEvicts and
Writebacks in the snoop filter. Previously there were no CleanEvicts, and
Writebacks did not send up snoops to ensure there were no copies in
caches above. Hence a writeback could never erase an entry from the
snoop filter.
When a CleanEvict message reaches a snoop filter, it confirms that the
BLOCK_CACHED flag is not set and resets the bits corresponding to the
CleanEvict address and port it arrived on. If none of the other peer
caches have (or have requested) the block, the snoop filter forwards
the CleanEvict to lower levels of memory. In case of a Writeback
message, the snoop filter checks if the BLOCK_CACHED flag is not set
and only then resets the bits corresponding to the Writeback
address. If any of the other peer caches have (or has requested) the
same block, the snoop filter sets the BLOCK_CACHED flag in the
Writeback before forwarding it to lower levels of memory heirarachy.
Ali Jafri [Fri, 25 Sep 2015 11:26:57 +0000 (07:26 -0400)]
mem: Add check for snooping ports in the snoop filter
This patch prevents the snoop filter from creating items for requests
originating from non-snooping ports. The allocation decision is thus
based both on the cacheability of the line, and the snooping status of
the source port. Ultimately we should check if the source of the
packet is caching, since also the CPU ports are snooping (but not
allocating). Thus, at the moment we rely on the snoop filter being
used together with caches.
The patch also transitions to use the Packet::getBlockAddr in
determining the line address.
Andreas Hansson [Fri, 25 Sep 2015 11:13:54 +0000 (07:13 -0400)]
mem: Make the coherent crossbar account for timing snoops
This patch introduces the concept of a snoop latency. Given the
requirement to snoop and forward packets in zero time (due to the
coherency mechanism), the latency is accounted for later.
On a snoop, we establish the latency, and later add it to the header
delay of the packet. To allow multiple caches to contribute to the
snoop latency, we use a separate variable in the packet, and then take
the maximum before adding it to the header delay.