re PR libgomp/91473 (Test case libgomp.fortran/appendix-a/a.28.5.f90 is invalid)

2019-08-17  Thomas Koenig  <tkoenig@gcc.gnu.org>

    PR fortran/91473
    * testsuite/libgomp.fortran/appendix-a/a.28.5.f90: Add
    -std=legacy so invalid code in the test case is accepted.

From-SVN: r274602

* doc/ux.texi (User Experience Guidelines): Update reference.

From-SVN: r274601

gpl_v3.texi (Copying): Adjust the link to "Why not LGPL".

* doc/include/gpl_v3.texi (Copying): Adjust the link to "Why
not LGPL".

From-SVN: r274600

PR fortran/68401 Improve allocation error message

Improve the error message that is printed when a memory allocation
fails, by including the location, and the size of the allocation that
failed.

Regtested on x86_64-pc-linux-gnu.

gcc/fortran/ChangeLog:

2019-08-17  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/68401
* trans-decl.c (gfc_build_builtin_function_decls): Replace
os_error with os_error_at decl.
* trans.c (trans_runtime_error_vararg): Modify so the error
function decl is passed directly.
(gfc_trans_runtime_error): Pass correct error function decl.
(gfc_trans_runtime_check): Likewise.
(trans_os_error_at): New function.
(gfc_call_malloc): Use trans_os_error_at.
(gfc_allocate_using_malloc): Likewise.
(gfc_call_realloc): Likewise.
* trans.h (gfor_fndecl_os_error): Replace with gfor_fndecl_os_error_at.

libgfortran/ChangeLog:

2019-08-17  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/68401
* gfortran.map: Add GFORTRAN_10 node, add _gfortran_os_error_at
symbol.
* libgfortran.h (os_error_at): New prototype.
* runtime/error.c (os_error_at): New function.

From-SVN: r274599

runtime: scan write barrier buffer conservatively

    In gccgo, we insert the write barriers in the frontend, and so we
    cannot completely prevent write barriers on stack writes. So it
    is possible for a bad pointer appearing in the write barrier
    buffer. When flushing the write barrier, treat it the same as
    sacnning the stack. In particular, don't mark a pointer if it
    does not point to an allocated object. We already have similar
    logic in greyobject. With this, hopefully, we can prevent an
    unallocated object from being marked completely.

    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/190599

From-SVN: r274598

Put the CL into the right dir.

From-SVN: r274596

Daily bump.

From-SVN: r274595

compiler: print runtime.hex in hex

    The gc compiler recognizes the type runtime.hex and prints values
    in this type as hex. Do the same here. This makes debugging
    runtime crashes slightly better.

    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/190597

From-SVN: r274591

* gcc.target/sh/pr54236-6.c: Use -fno-tree-forwprop.

From-SVN: r274590

re PR c++/85827 (false positive for -Wunused-but-set-variable because of constexpr-if)

PR c++/85827
g++.dg/cpp1z/constexpr-if29.C: New test.

From-SVN: r274587

libsanitizer, record a local patch.

2019-08-16  Iain Sandoe  <iain@sandoe.co.uk>

* LOCAL_PATCHES: Add r274585.

From-SVN: r274586

libsanitize, asan - reapply r272406

The entry in LOCAL_PATCHES was accidentally omitted.

2019-08-16  Iain Sandoe  <iain@sandoe.co.uk>

* asan/asan_interceptors.h: Reapply r272406.

From-SVN: r274585

As discussed below:

  https://gcc.gnu.org/ml/gcc-patches/2019-08/msg00517.html

gcc/testsuite/ChangeLog:
* gcc.dg/struct-ret-1.c: Enable on all targets.

From-SVN: r274579

tree-sra.c (build_reconstructed_reference): Return NULL_TREE instead of NULL.

* tree-sra.c (build_reconstructed_reference): Return NULL_TREE instead
of NULL.  Add guard for broken VIEW_CONVERT_EXPRs.

From-SVN: r274576

tree.def (TYPE_SIZE): Clarify.

gcc/ChangeLog:

* tree.def (TYPE_SIZE): Clarify.
* tree.h (TYPE_SIZE, TYPE_SIZE_UNIT, DECL_SIZE): Add comments.

From-SVN: r274575

re PR testsuite/91458 (FAIL: g++.dg/tree-ssa/pr19807.C  -std=gnu++98  scan-tree-dump-times optimized "&MEM\\\\[\\\\(void .\\\\)&a \\\\+ 8B\\\\]" 3)

PR testsuite/91458

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/pr19807.C: Use the same search pattern
unconditionally (correcting r272199, PR middle-end/90676).

From-SVN: r274574

re PR tree-optimization/91109 ([arm] gcc.c-torture/execute/20040709-1.c fails since r273135)

2019-08-16  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR tree-optimization/91109
        * lra-int.h (lra_need_for_scratch_reg_p): Declare.
        * lra.c (lra): Use lra_need_for_scratch_reg_p.
        * lra-spills.c (lra_need_for_scratch_reg_p): New function.

From-SVN: r274573

mmx.md (mmxdoublemode): New mode attribute.

* config/i386/mmx.md (mmxdoublemode): New mode attribute.
(mmx_uavg<mode>3): Macroize expaner from mmx_uavgv8qi3 and
mmx_uavgv4hi3 using MMXMODE12 mode iterator.
(uavg<mode>3_ceil): New expander.
* config/i386/sse.md (uavg<mode>3_ceil): Use ssedoublemode
mode iterator when creating CONST1_RTX.
(<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
(*<sse2_avx2>_uavg<mode>3<mask_name>): Use ssedoublemode
mode iterator for const1_operand predicate.

From-SVN: r274572

tree-scalar-evolution.c (follow_ssa_edge_expr): Declare.

2019-08-16  Richard Biener  <rguenther@suse.de>

* tree-scalar-evolution.c (follow_ssa_edge_expr): Declare.
(follow_ssa_edge_binary): Call follow_ssa_edge_expr instead of
follow_ssa_edge.
(follow_ssa_edge_in_condition_phi_branch): Likewise.
(analyze_evolution_in_loop): Likewise.
(follow_ssa_edge, follow_ssa_edge_in_rhs): Inline into ...
(follow_ssa_edge_expr): ... here.  Refactor code.

From-SVN: r274571

re PR target/91469 (ICE in extract_insn, at recog.c:2310 since r274481)

2019-08-16  Richard Biener  <rguenther@suse.de>

PR target/91469
* config/i386/i386-features.c
(general_scalar_chain::replace_with_subreg): Stop at memory operands.

* gcc.target/i386/pr91469-1.c: New testcase.
* gcc.target/i386/pr91469-2.c: Likewise.

From-SVN: r274570

baseline_symbols.txt: Update.

* config/abi/post/alpha-linux-gnu/baseline_symbols.txt: Update.

From-SVN: r274569

Allow automatics in equivalences

If a variable with an automatic attribute appears in an
equivalence statement the storage should be allocated on the
stack.

Note: most of this patch was provided by Jeff Law  <law@redhat.com>.

From-SVN: r274565

[gensupport] PR 91255: Do not error out immediately on set_attr_alternative with define_subst

I'm trying to add a define_subst use in the arm backend but am getting many build errors complaining about:
`set_attr_alternative' is unsupported by `define_subst'

Looking at the gensupport.c code it iterates over all define_insns and errors if any of them have set_attr_alternative.

The usecase I'm targetting doesn't involve patterns with set_attr_alternative, so I would like to make the define_subst handling
more robust to only error out if the define_subst is actually attempted on a set_attr_alternative.

This patch produces the error only if the set_attr_alternative attr matches the subst name.
This allows a build of the arm backend with a define_subst usage to succeed.

PR other/91255
* gensupport.c (has_subst_attribute): Error out on set_attr_alternative
only if subst_name matches curr_attr string.

From-SVN: r274564

tree-ssa-forwprop.c (simplify_builtin_call): Do not remove stmt at gsi_p, instead replace it with a NOP removed later.

2019-08-16  Richard Biener  <rguenther@suse.de>

* tree-ssa-forwprop.c (simplify_builtin_call): Do not remove
stmt at gsi_p, instead replace it with a NOP removed later.
(pass_forwprop::execute): Fully propagate lattice, DCE stmts
that became dead because of that.

fortran/
* trans-intrinsic.c (gfc_conv_intrinsic_findloc): Initialize
forward_branch to avoid bogus uninitialized warning.

* gcc.dg/tree-ssa/forwprop-31.c: Adjust.

From-SVN: r274563

Add missed to a opt-info dump.

2019-08-16  Martin Liska  <mliska@suse.cz>

PR ipa/91447
* g++.dg/ipa/ipa-icf-4.C: Add -missed for target that
don't have aliases.

From-SVN: r274562

Add type to VR_VARYING.

From-SVN: r274561

require trampolines for pr85044

Testcases that require support for trampolines should be marked as
such; gcc.target/i386/pr85044.c was missing it.  Fixed.

for  gcc/testsuite/ChangeLog

* gcc.target/i386/pr85044.c: Require support for trampolines.

From-SVN: r274560

i386/asm-4 test: use amd64's natural addressing mode on all OSs

gcc.target/i386/asm-4.c uses amd64's natural PC-relative addressing
mode on a single platform, using the 32-bit absolute addressing mode
elsewhere.  There's no point in giving up amd64's natural addressing
mode and insisting on the 32-bit one when we're targeting amd64, and
having to make explicit exceptions for systems where that's found not
to work for whatever reason.  If we just use the best-suited way to
take the address of a function behind the compiler's back on each
target variant, we're less likely to hit unexpected failures.

for  gcc/testsuite/ChangeLog

* gcc.target/i386/asm-4.c: Use amd64 natural addressing mode
on all __LP64__ targets.

From-SVN: r274559

use __builtin_alloca, drop non-standard alloca.h

Since alloca.h is not ISO C, most of our alloca-using tests seem to
rely on __builtin_alloca instead of including the header and calling
alloca.  This patch extends this practice to some of the exceptions I
found in gcc.target, marking them as requiring a functional alloca
while at that.

for  gcc/testsuite/ChangeLog

* gcc.target/arc/interrupt-6.c: Use __builtin_alloca, require
effective target support for alloca, drop include of alloca.h.
* gcc.target/i386/pr80969-3.c: Likewise.
* gcc.target/sparc/setjmp-1.c: Likewise.
* gcc.target/x86_64/abi/ms-sysv/gen.cc: Likewise.
* gcc.target/x86_64/abi/ms-sysv/ms-sysv.c: Likewise.

From-SVN: r274558

Match ld besides collect2 in gcov test

The regexp that checks that -lgcov is linked in when --coverage is
passed to the compiler driver requires the command line to match
'/collect2'.  Some of our targets don't match that, but they match /ld
or ${target_alias}-ld depending on the testing scenario, so I'd like
to tweak the test to match those as well.

for  gcc/testsuite/ChangeLog

* gcc.misc-tests/options.exp: Match /ld and -ld besides
/collect2.

From-SVN: r274557

address change

Oops, I forgot to update the MAINTAINERS file a couple of months ago,
when the address there stopped working.

Honestly, I haven't really had much involvement with the frv, mn10300
or sh ports for almost 15 years, so I wouldn't mind if someone else
stepped up and took over, but until someone does, I don't mind
reviewing the occasional patch, so it's best if it can reach me ;-)

for  ChangeLog

* MAINTAINERS: aoliva from @redhat.com to @gcc.gnu.org.

From-SVN: r274556

Daily bump.

From-SVN: r274555

re PR fortran/91443 (-Wargument-mismatch does not catch mismatch for global procedure)

2019-08-15  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/91443
* frontend-passes.c (check_externals_expr): New function.
(check_externals_code): New function.
(gfc_check_externals): New function.
* gfortran.h (debug): Add prototypes for gfc_symbol * and
gfc_expr *.
(gfc_check_externals): Add prototype.
* interface.c (compare_actual_formal): Do not complain about
alternate returns if the formal argument is optional.
(gfc_procedure_use): Handle cases when an error has been issued
previously.  Break long line.
* parse.c (gfc_parse_file): Call gfc_check_externals for all
external procedures.
* resolve.c (resolve_global_procedure): Remove checking of
argument list.

2019-08-15  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/91443
* gfortran.dg/argument_checking_19.f90: New test.
* gfortran.dg/altreturn_10.f90: Change dg-warning to dg-error.
* gfortran.dg/dec_union_11.f90: Add -std=legacy.
* gfortran.dg/hollerith8.f90: Likewise. Remove warning for
Hollerith constant.
* gfortran.dg/integer_exponentiation_2.f90: New subroutine gee_i8;
use it to avoid type mismatches.
* gfortran.dg/pr41011.f: Add -std=legacy.
* gfortran.dg/whole_file_1.f90: Change warnings to errors.
* gfortran.dg/whole_file_2.f90: Likewise.

From-SVN: r274551

PR c++/90393 - ICE with thow in ?:

My previous patch for 64372 was incomplete: it only stopped making the
non-throw argument into an rvalue, lvalue_kind still considered the ?:
expression to be an rvalue, leaving us worse than before.

PR c++/64372, DR 1560 - Gratuitous lvalue-to-rvalue conversion in ?:
* tree.c (lvalue_kind): Handle throw in one arm.
* typeck.c (rationalize_conditional_expr): Likewise.
(cp_build_modify_expr): Likewise.

From-SVN: r274550

i386: Separate costs of pseudo registers from hard registers

processor_costs has costs of RTL expressions with pseudo registers and
and costs of hard register moves:

1. Costs of RTL expressions are used to generate the most efficient RTL
operations with pseudo registers.

2. Costs of hard register moves are used by register allocator to
decide how to allocate and move hard registers.

Since relative costs of pseudo register load and store versus pseudo
register moves in RTL expressions can be different from relative costs
of hard registers, we should separate costs of RTL expressions with
pseudo registers from costs of hard registers so that register allocator
and RTL expressions can be improved independently.

This patch moves costs of hard register moves to the new hard_register
field and duplicates costs of moves which are also used for costs of RTL
expressions.

PR target/90878
* config/i386/i386.c (inline_memory_move_cost): Use hard_register
for costs of hard register moves.
(ix86_register_move_cost): Likewise.
* config/i386/i386.h (processor_costs): Move costs of hard
register moves to hard_register.  Add int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store, sse_unaligned_load and sse_unaligned_store
for costs of RTL expressions.
* config/i386/x86-tune-costs.h: Move costs of hard register
moves to hard_register.  Duplicate int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store for costs of RTL expressions.

From-SVN: r274543

PR libstdc++/91456 make INVOKE<R> work with uncopyable prvalues

In C++17 a function can return a prvalue of a type that cannot be moved
or copied. The current implementation of std::is_invocable_r uses
std::is_convertible to test the conversion to R required by INVOKE<R>.
That fails for non-copyable prvalues, because std::is_convertible is
defined in terms of std::declval which uses std::add_rvalue_reference.
In C++17 conversion from R to R involves no copies and so is not the
same as conversion from R&& to R.

This commit changes std::is_invocable_r to check the conversion without
using std::is_convertible.

std::function also contains a similar check using std::is_convertible,
which can be fixed by simply reusing std::is_invocable_r (but because
std::is_invocable_r is not defined for C++11 it uses the underlying
std::__is_invocable_impl trait directly).

PR libstdc++/91456
* include/bits/std_function.h (__check_func_return_type): Remove.
(function::_Callable): Use std::__is_invocable_impl instead of
__check_func_return_type.
* include/std/type_traits (__is_invocable_impl): Add another defaulted
template parameter. Define a separate partial specialization for
INVOKE and INVOKE<void>. For INVOKE<R> replace is_convertible check
with a check that models delayed temporary materialization.
* testsuite/20_util/function/91456.cc: New test.
* testsuite/20_util/is_invocable/91456.cc: New test.

From-SVN: r274542

Add r274540 to LOCAL_PATCHES.

2019-08-15  Martin Liska  <mliska@suse.cz>

* LOCAL_PATCHES: Add r274540

From-SVN: r274541

Reapply missing patch for libsanitizer.

2019-08-15  Martin Liska  <mliska@suse.cz>

* tsan/tsan_rtl_ppc64.S: Reapply.

From-SVN: r274540

Remove TARGET_SETUP_INCOMING_VARARG_BOUNDS

TARGET_SETUP_INCOMING_VARARG_BOUNDS seems to be an unused vestige of the
MPX support.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* target.def (setup_incoming_vararg_bounds): Remove.
* doc/tm.texi.in (TARGET_SETUP_INCOMING_VARARG_BOUNDS): Remove.
* doc/tm.texi: Regenerate.
* targhooks.c (default_setup_incoming_vararg_bounds): Delete.
* targhooks.h (default_setup_incoming_vararg_bounds): Likewise.
* config/i386/i386.c (ix86_setup_incoming_vararg_bounds): Likewise.
(TARGET_SETUP_INCOMING_VARARG_BOUNDS): Likewise.

From-SVN: r274539

[libsanitizer] Fix PR bootstrap/91455

If a target does not support libbacktrace, it might still the include
for $(top_srcdir).

Regenerate the built files using automake-1.15.1

libsanitizer/

2019-08-15  Iain Sandoe  <iain@sandoe.co.uk>

PR bootstrap/91455
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* asan/Makefile.in: Likewise.
* configure: Likewise.
* interception/Makefile.in: Likewise.
* libbacktrace/Makefile.in: Likewise.
* lsan/Makefile.in: Likewise.
* sanitizer_common/Makefile.am: Include top_srcdir unconditionally.
* sanitizer_common/Makefile.in: Regenerated.
* tsan/Makefile.in: Likewise.
* ubsan/Makefile.in: Likewise.

From-SVN: r274538

MSP430: Fix lines over 80 characters long in config/msp430/*.{c,h} files

2019-08-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

MSP430: Fix lines over 80 characters long in
config/msp430/*.{c,h} files

* config/msp430/driver-msp430.c (msp430_select_cpu): Fix format
specifier in string.
(msp430_select_hwmult_lib): Split line more than 80 characters long.
* config/msp430/msp430-devices.c (msp430_extract_mcu_data): Remove
redundant old comment.
* config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
Split line more than 80 characters long.
* config/msp430/msp430.c (msp430_option_override): Likewise.
(msp430_return_in_memory): Likewise.
(msp430_gimplify_va_arg_expr): Likewise.
(TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): Likewise.
(msp430_legitimate_constant): Likewise.
(TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS): Likewise.
(msp430_attr): Likewise.
(msp430_data_attr): Likewise.
(msp430_start_function): Likewise.
(gen_prefix): Likewise.
(msp430_init_sections): Likewise.
(msp430_select_section): Likewise.
(msp430_function_section): Likewise.
(msp430_unique_section): Likewise.
(msp430_output_aligned_decl_common): Likewise.
(msp430_do_not_relax_short_jumps): Likewise.
(msp430_init_builtins): Likewise.
(msp430_expand_delay_cycles): Likewise.
(msp430_expand_prologue): Likewise.
(msp430_expand_epilogue): Likewise.
(msp430_expand_helper): Likewise.
(msp430_split_movsi): Likewise.
(msp430_print_operand): Likewise.
(msp430_return_addr_rtx): Likewise.
(msp430x_extendhisi): Likewise.
* config/msp430/msp430.h (STARTFILE_SPEC): Likewise.
(ASM_SPEC): Likewise.
Remove very obvious comments.
(LIB_SPEC): Split line more than 80 characters long.
(EH_RETURN_HANDLER_RTX): Likewise.
(HARD_REGNO_CALLER_SAVE_MODE): Likewise.

From-SVN: r274537

MSP430: Fix whitespace errors and incorrect indentation in config/msp430/*.{c,h} files

2019-08-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

MSP430: Fix whitespace errors and incorrect indentation in
config/msp430/*.{c,h} files

* config/msp430/driver-msp430.c (msp430_select_cpu): Fix indentation.
(msp430_select_hwmult_lib): Likewise.
* config/msp430/msp430-devices.c (parse_devices_csv_1): Likewise.
(msp430_extract_mcu_data): Likewise.
(struct t_msp430_mcu_data): Likewise.
* config/msp430/msp430.c (struct machine_function): Remove whitespace
before left square bracket.
(msp430_option_override): Fix indentation.
(msp430_hard_regno_nregs_with_padding): Likewise.
(msp430_initial_elimination_offset): Likewise.
(msp430_special_register_convention_p): Remove whitespace before left
square bracket and after exclamation mark.
(msp430_evaluate_arg): Likewise.
(msp430_callee_copies): Fix indentation.
(msp430_gimplify_va_arg_expr): Likewise.
(msp430_function_arg_advance): Remove whitespace before left square
bracket.
(reg_ok_for_addr): Likewise.
(msp430_preserve_reg_p): Likewise.
(msp430_compute_frame_info): Likewise.
(msp430_asm_output_addr_const_extra): Add space between function name
and open parenthesis.
(has_section_name): Fix indentation.
(msp430_attr): Remove trailing whitespace.
(msp430_section_attr): Likewise.
(msp430_data_attr): Likewise.
(struct msp430_attribute_table): Fix comment and whitespace.
(msp430_start_function): Remove whitespace before left square bracket.
Add space between function name and open parenthesis.
(msp430_select_section): Remove trailing whitespace.
(msp430_section_type_flags): Remove trailing whitespace.
(msp430_unique_section): Remove space before closing parenthesis.
(msp430_output_aligned_decl_common): Change 8 spaces to a tab.
(msp430_builtins): Remove whitespace before left square bracket.
(msp430_init_builtins): Fix indentation.
(msp430_expand_prologue): Remove whitespace before left square bracket.
Remove space before closing parenthesis.
(msp430_expand_epilogue): Remove whitespace before left square bracket.
(msp430_split_movsi): Remove space before closing parenthesis.
(helper_function_name_mappings): Fix indentation.
(msp430_use_f5_series_hwmult): Fix whitespace.
(use_32bit_hwmult): Likewise.
(msp430_no_hwmult): Likewise.
(msp430_output_labelref): Remove whitespace before left square bracket.
(msp430_print_operand_raw): Likewise.
(msp430_print_operand_addr): Likewise.
(msp430_print_operand): Add two spaces after '.' in comment.
Fix trailing whitespace.
(msp430x_extendhisi): Fix indentation.
* config/msp430/msp430.h (TARGET_CPU_CPP_BUILTINS): Change 8 spaces to
tab.
(PC_REGNUM): Likewise.
(STACK_POINTER_REGNUM): Likewise.
(CC_REGNUM): Likewise.

From-SVN: r274536

re PR target/91454 (ICE in get_attr_avx_partial_xmm_update, at config/i386/i386.md:1804 since r274481)

2019-08-15  Richard Biener  <rguenther@suse.de>

PR target/91454
* config/i386/i386-features.c (gen_gpr_to_xmm_move_src): New
helper.
(general_scalar_chain::make_vector_copies): Use it.

From-SVN: r274535

Implement P0848R3, Conditionally Trivial Special Member Functions.

With Concepts, overloads of special member functions can differ in
constraints, and this paper clarifies how that affects class properties: if
a class has a more constrained trivial copy constructor and a less
constrained non-trivial copy constructor, it is still trivially copyable.

* tree.c (special_memfn_p): New.
* class.c (add_method): When overloading, hide ineligible special
member fns.
(check_methods): Set TYPE_HAS_COMPLEX_* here.
* decl.c (grok_special_member_properties): Not here.
* name-lookup.c (push_class_level_binding_1): Move overloaded
functions case down, accept FUNCTION_DECL as target_decl.

From-SVN: r274534

re PR tree-optimization/91445 (After memset, logical && operator produces false result, optimization level >=O1)

2019-08-15  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91445
* gcc.dg/torture/pr91445.c: New testcase.

From-SVN: r274533

function.c (assign_parm_setup_reg): Handle misaligned stack arguments.

2019-08-15  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        * function.c (assign_parm_setup_reg): Handle misaligned stack arguments.

From-SVN: r274531

Clean up dead condition for operators in DCE.

2019-08-15  Martin Liska  <mliska@suse.cz>

* tree-ssa-dce.c (propagate_necessity): We can't reach now
operators with no arguments.
(eliminate_unnecessary_stmts): Likewise here.

From-SVN: r274529

c-common.c (c_stddef_cpp_builtins): When the GIMPLE FE is enabled, define __SIZETYPE__.

2019-08-15  Richard Biener  <rguenther@suse.de>

c-family/
* c-common.c (c_stddef_cpp_builtins): When the GIMPLE FE is
enabled, define __SIZETYPE__.

* gcc.dg/pr80170.c: Adjust to use __SIZETYPE__.

From-SVN: r274528

* config/i386/i386.c (convertible_comparison_p): Fix argument declaration.

From-SVN: r274527

i386-features.c (general_scalar_chain::convert_insn): Revert 2019-08-14 change.

* config/i386/i386-features.c (general_scalar_chain::convert_insn)
<case COMPARE>: Revert 2019-08-14 change.
(convertible_comparison_p): Revert 2019-08-14 change.  Return false
for (TARGET_64BIT || mode != DImode).

From-SVN: r274526

Enforce canonicalization in value_range.

From-SVN: r274525

Add missing check for BUILT_IN_MD (PR 91444)

In this PR we were passing an ordinary non-built-in function to
targetm.vectorize.builtin_md_vectorized_function, which is only
supposed to handle BUILT_IN_MD.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
PR middle-end/91444
* tree-vect-stmts.c (vectorizable_call): Check that the function
is a BUILT_IN_MD function before passing it to
targetm.vectorize.builtin_md_vectorized_function.

From-SVN: r274524

[AArch64] Add a aarch64_sve_mode_p query

This patch adds an exported function for testing whether a mode is
an SVE mode.  The ACLE will make more use of it, but there's already
one place that can benefit.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_sve_mode_p): Declare.
* config/aarch64/aarch64.c (aarch64_sve_mode_p): New function.
(aarch64_select_early_remat_modes): Use it.

From-SVN: r274523

[AArch64] Fix predicate alignment for fixed-length SVE

aarch64_simd_vector_alignment was only giving predicates 16-bit
alignment in VLA mode, not VLS mode.  I think the problem is latent
because we can't yet create an ABI predicate type, but it seemed worth
fixing in a standalone patch rather than as part of the main ACLE series.

The ACLE patches have tests for this.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_simd_vector_alignment): Return
16 for SVE predicates even if they are fixed-length.

From-SVN: r274522

[AArch64] Tweak operand choice for SVE predicate AND

SVE defines an assembly alias:

   MOV pa.B, pb/Z, pc.B  ->  AND pa.B. pb/Z, pc.B, pc.B

Our and<mode>3 pattern was instead using the functionally-equivalent:

   AND pa.B. pb/Z, pb.B, pc.B
                   ^^^^
This patch duplicates pc.B instead so that the alias can be seen
in disassembly.

I wondered about using the alias in the pattern instead, but using AND
explicitly seems to fit better with the pattern name and surrounding code.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
operand order match the MOV /Z alias.

From-SVN: r274521

[AArch64] Pass a pattern to aarch64_output_sve_cnt_immediate

This patch makes us always pass an explicit vector pattern to
aarch64_output_sve_cnt_immediate, rather than assuming it's ALL.
The ACLE patches need to be able to pass in other values.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take
the vector pattern as an aarch64_svpattern argument.  Update the
overloaded caller accordingly.
(aarch64_output_sve_scalar_inc_dec): Update call accordingly.
(aarch64_output_sve_vector_inc_dec): Likewise.

From-SVN: r274520

[AArch64] Optimise aarch64_add_offset for SVE VL constants

aarch64_add_offset contains code to decompose all SVE VL-based constants
into native operations.  The worst-case fallback is to load the number
of SVE elements into a register and use a general multiplication.
This patch improves that fallback by reusing expand_mult if
can_create_pseudo_p, rather than emitting a MULT pattern directly.

In order to increase the chances of being able to use a simple
add-and-shift, the patch also tries to compute VG * the lowest set
bit of the multiplier, rather than always using CNTD as the basis
for the multiplication path.

This is tested by the ACLE patches but is really an independent
improvement.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_add_offset): In the fallback
multiplication case, try to compute VG * (lowest set bit) directly
rather than always basing the multiplication on VG.  Use
expand_mult for the multiplication if we can.

gcc/testsuite/
* gcc.target/aarch64/sve/loop_add_4.c: Expect 10 INCWs and
INCDs rather than 8.

From-SVN: r274519

[AArch64] Rework SVE INC/DEC handling

The scalar addition patterns allowed all the VL constants that
ADDVL and ADDPL allow, but wrote the instructions as INC or DEC
if possible (i.e. adding or subtracting a number of elements * [1, 16]
when the source and target registers the same).  That works for the
cases that the autovectoriser needs, but there are a few constants
that INC and DEC can handle but ADDPL and ADDVL can't.  E.g.:

        inch    x0, all, mul #9

is not a multiple of the number of bytes in an SVE register, and so
can't use ADDVL.  It represents 36 times the number of bytes in an
SVE predicate, putting it outside the range of ADDPL.

This patch therefore adds separate alternatives for INC and DEC,
tied to a new Uai constraint.  It also adds an explicit "scalar"
or "vector" to the function names, to avoid a clash with the
existing support for vector INC and DEC.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-protos.h
(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
(aarch64_output_sve_scalar_inc_dec): Declare.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.
* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
(aarch64_output_sve_scalar_inc_dec): New functions.
(aarch64_output_sve_addvl_addpl): Remove the base and offset
arguments.  Only handle true ADDVL and ADDPL instructions;
don't emit an INC or DEC.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.  Update call to
aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
(aarch64_sve_plus_immediate): New predicates.
(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
rather than aarch64_sve_addvl_addpl_immediate.
(aarch64_sve_inc_dec_immediate): Rename to...
(aarch64_sve_vector_inc_dec_immediate): ...this.  Update call to
aarch64_sve_vector_inc_dec_immediate_p.
(aarch64_sve_add_operand): Update accordingly.
* config/aarch64/constraints.md (Uai): New constraint.
(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
operand into a register if it satisfies aarch64_sve_plus_immediate.
(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
for Uai.  Update calls to aarch64_output_sve_addvl_addpl.
* config/aarch64/aarch64-sve.md (add<mode>3): Call
aarch64_output_sve_vector_inc_dec instead of
aarch64_output_sve_inc_dec_immediate.

From-SVN: r274518

[AArch64] Rework SVE REV[BHW] patterns

The current SVE REV patterns follow the AArch64 scheme, in which
UNSPEC_REV<NN> reverses elements within an <NN>-bit granule.
E.g. UNSPEC_REV64 on VNx8HI reverses the four 16-bit elements
within each 64-bit granule.

The native SVE scheme is the other way around: UNSPEC_REV64 is seen
as an operation on 64-bit elements, with REVB swapping bytes within
the elements, REVH swapping halfwords, and so on.  This fits SVE more
naturally because the operation can then be predicated per <NN>-bit
granule/element.

Making the patterns use the Advanced SIMD scheme was more natural
when all we cared about were permutes, since we could then use
the source and target of the permute in their original modes.
However, the ACLE does need patterns that follow the native scheme,
treating them as operations on integer elements.  This patch defines
the patterns that way instead and updates the existing uses to match.

This also brings in a couple of helper routines from the ACLE branch.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/iterators.md (UNSPEC_REVB, UNSPEC_REVH)
(UNSPEC_REVW): New constants.
(elem_bits): New mode attribute.
(SVE_INT_UNARY): New int iterator.
(optab): Handle UNSPEC_REV[BHW].
(sve_int_op): New int attribute.
(min_elem_bits): Handle VNx16QI and the predicate modes.
* config/aarch64/aarch64-sve.md (*aarch64_sve_rev64<mode>)
(*aarch64_sve_rev32<mode>, *aarch64_sve_rev16vnx16qi): Delete.
(@aarch64_pred_<SVE_INT_UNARY:optab><SVE_I:mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_sve_data_mode): New function.
(aarch64_sve_int_mode, aarch64_sve_rev_unspec): Likewise.
(aarch64_split_sve_subreg_move): Use UNSPEC_REV[BHW] instead of
unspecs based on the total width of the reversed data.
(aarch64_evpc_rev_local): Likewise (for SVE only).  Use a
reinterpret followed by a subreg on big-endian targets.

gcc/testsuite/
* gcc.target/aarch64/sve/revb_1.c: Restrict to little-endian targets.
Avoid including stdint.h.
* gcc.target/aarch64/sve/revh_1.c: Likewise.
* gcc.target/aarch64/sve/revw_1.c: Likewise.
* gcc.target/aarch64/sve/revb_2.c: New big-endian test.
* gcc.target/aarch64/sve/revh_2.c: Likewise.
* gcc.target/aarch64/sve/revw_2.c: Likewise.

From-SVN: r274517

[AArch64] Add more SVE FMLA and FMAD /z alternatives

This patch makes the floating-point conditional FMA patterns provide the
same /z alternatives as the integer patterns added by a previous patch.
We can handle cases in which individual inputs are allocated to the same
register as the output, so we don't need to force all registers to be
different.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
alternatives in which one of the inputs is in the same register
as the output.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
and FMSB as well as FMLS.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274516

[AArch64] Add MOVPRFX alternatives for SVE EXT patterns

We use EXT both to implement vec_extract for large indices and as a
permute.  In both cases we can use MOVPRFX to handle the case in which
the first input and output can't be tied.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md (*vec_extract<mode><Vel>_ext)
(*aarch64_sve_ext<mode>): Add MOVPRFX alternatives.

gcc/testsuite/
* gcc.target/aarch64/sve/ext_2.c: Expect a MOVPRFX.
* gcc.target/aarch64/sve/ext_3.c: New test.

From-SVN: r274515

[AArch64] Remove unneeded FSUB alternatives and add a new one

The floating-point subtraction patterns don't need to handle
subtraction of constants, since those go through the addition
patterns instead.  There was a missing MOVPRFX alternative for
FSUBR though.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
FADD and FSUB alternatives.  Add a MOVPRFX alternative for FSUBR.

From-SVN: r274514

[AArch64] Add more unpredicated MOVPRFX alternatives

FABD and some immediate instructions were missing MOVPRFX alternatives.
This is tested by the ACLE patches but is really an independent improvement.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md (add<SVE_I:mode>3, sub<SVE_I:mode>3)
(<LOGICAL:optab><SVE_I:mode>3, *add<SVE_F:mode>3, *mul<SVE_F:mode>3)
(*fabd<SVE_F:mode>3): Add more MOVPRFX alternatives.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274513

[AArch64] Use SVE reversed shifts in preference to MOVPRFX

This patch makes us use reversed SVE shifts when the first operand
can't be tied to the output but the second can.  This is tested
more thoroughly by the ACLE patches but is really an independent
improvement.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3):
Add an alternative that uses reversed shifts.

gcc/testsuite/
* gcc.target/aarch64/sve/shift_1.c: Accept reversed shifts.

Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
From-SVN: r274512

[aarch64] Use neoversen1 tuning struct for -mcpu=cortex-a76

The neoversen1 tuning struct gives better performance on the Cortex-A76, so use that.
The only difference from the current tuning is the function and label alignment settings.

This gives about 1.3% improvement on SPEC2006 int and 0.3% on SPEC2006 fp.

        * config/aarch64/aarch64-cores.def (cortex-a76): Use neoversen1 tuning
        struct.

From-SVN: r274511

[AArch64] Add a commutativity marker to the SVE [SU]ABD patterns

This will be tested by the ACLE patches, but it's really an
independent improvement.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md (aarch64_<su>abd<mode>_3): Add
a commutativity marker.

From-SVN: r274510

[AArch64] Use SVE MLA, MLS, MAD and MSB for conditional arithmetic

This patch uses predicated MLA, MLS, MAD and MSB to implement
conditional "FMA"s on integers.  This also requires providing
the unpredicated optabs (fma and fnma) since otherwise
tree-ssa-math-opts.c won't try to use the conditional forms.

We still want to use shifts and adds in preference to multiplications,
so the patch makes the optab expanders check for that.

The tests cover floating-point types too, which are already handled,
and which were already tested to some extent by gcc.dg/vect.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_prepare_sve_int_fma)
(aarch64_prepare_sve_cond_int_fma): Declare.
* config/aarch64/aarch64.c (aarch64_convert_mult_to_shift)
(aarch64_prepare_sve_int_fma): New functions.
(aarch64_prepare_sve_cond_int_fma): Likewise.
* config/aarch64/aarch64-sve.md
(cond_<SVE_INT_BINARY:optab><SVE_I:mode>): Add a "@" marker.
(fma<SVE_I:mode>4, cond_fma<SVE_I:mode>, *cond_fma<SVE_I:mode>_2)
(*cond_fma<SVE_I:mode>_4, *cond_fma<SVE_I:mode>_any, fnma<SVE_I:mode>4)
(cond_fnma<SVE_I:mode>, *cond_fnma<SVE_I:mode>_2)
(*cond_fnma<SVE_I:mode>_4, *cond_fnma<SVE_I:mode>_any): New patterns.
(*madd<mode>): Rename to...
(*fma<mode>4): ...this.
(*msub<mode>): Rename to...
(*fnma<mode>4): ...this.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_mla_1.c: New test.
* gcc.target/aarch64/sve/cond_mla_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_2.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_3.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_4.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_5.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_6.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_6_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_7.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_7_run.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_8.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_8_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274509

[AArch64] Use SVE binary immediate instructions for conditional arithmetic

This patch lets us use the immediate forms of FADD, FSUB, FSUBR,
FMUL, FMAXNM and FMINNM for conditional arithmetic.  (We already
use them for normal unconditional arithmetic.)

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64.c (aarch64_print_vector_float_operand):
Print 2.0 naturally.
(aarch64_sve_float_mul_immediate_p): Return true for 2.0.
* config/aarch64/predicates.md
(aarch64_sve_float_negated_arith_immediate): New predicate,
renamed from aarch64_sve_float_arith_with_sub_immediate.
(aarch64_sve_float_arith_with_sub_immediate): Test for both
positive and negative constants.
(aarch64_sve_float_arith_with_sub_operand): Redefine as a register
or an aarch64_sve_float_arith_with_sub_immediate.
* config/aarch64/constraints.md (vsN): Use
aarch64_sve_float_negated_arith_immediate.
* config/aarch64/iterators.md (SVE_COND_FP_BINARY_I1): New int
iterator.
(sve_pred_fp_rhs2_immediate): New int attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>): Use
sve_pred_fp_rhs1_operand and sve_pred_fp_rhs2_operand.
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_2_const)
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_any_const)
(*cond_add<SVE_F:mode>_2_const, *cond_add<SVE_F:mode>_any_const)
(*cond_sub<mode>_3_const, *cond_sub<mode>_any_const): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_fadd_1.c: New test.
* gcc.target/aarch64/sve/cond_fadd_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fadd_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_4_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274508

[AArch64] Use SVE FABD in conditional arithmetic

This patch extends the FABD support so that it handles conditional
arithmetic.  We're relying on combine for this, since there's no
associated IFN_COND_* (yet?).

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_abd<SVE_F:mode>_2)
(*aarch64_cond_abd<SVE_F:mode>_3)
(*aarch64_cond_abd<SVE_F:mode>_any): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_fabd_1.c: New test.
* gcc.target/aarch64/sve/cond_fabd_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_2.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_4.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_5.c: Likewise.
* gcc.target/aarch64/sve/cond_fabd_5_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274507

[AArch64] Use SVE [SU]ABD in conditional arithmetic

This patch extends the [SU]ABD support so that it handles
conditional arithmetic.  We're relying on combine for this,
since there's no associated IFN_COND_* (yet?).

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_<su>abd<mode>_2)
(*aarch64_cond_<su>abd<mode>_any): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_abd_1.c: New test.
* gcc.target/aarch64/sve/cond_abd_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_2.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_3.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_4.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_5.c: Likewise.
* gcc.target/aarch64/sve/cond_abd_5_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274506

Add support for conditional shifts

This patch adds support for IFN_COND shifts left and shifts right.
This is mostly mechanical, but since we try to handle conditional
operations in the same way as unconditional operations in match.pd,
we need to support IFN_COND shifts by scalars as well as vectors.
E.g.:

   IFN_COND_SHL (cond, a, { 1, 1, ... }, fallback)

and:

   IFN_COND_SHL (cond, a, 1, fallback)

are the same operation, with:

   (for shiftrotate (lrotate rrotate lshift rshift)
    ...
    /* Prefer vector1 << scalar to vector1 << vector2
       if vector2 is uniform.  */
    (for vec (VECTOR_CST CONSTRUCTOR)
     (simplify
      (shiftrotate @0 vec@1)
      (with { tree tem = uniform_vector_p (@1); }
       (if (tem)
(shiftrotate @0 { tem; }))))))

preferring the latter.  The patch copes with this by extending
create_convert_operand_from to handle scalar-to-vector conversions.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>
    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

gcc/
* internal-fn.def (IFN_COND_SHL, IFN_COND_SHR): New internal functions.
* internal-fn.c (FOR_EACH_CODE_MAPPING): Handle shifts.
* match.pd (UNCOND_BINARY, COND_BINARY): Likewise.
* optabs.def (cond_ashl_optab, cond_ashr_optab, cond_lshr_optab): New
optabs.
* optabs.h (create_convert_operand_from): Expand comment.
* optabs.c (maybe_legitimize_operand): Allow implicit broadcasts
when mapping scalar rtxes to vector operands.
* config/aarch64/iterators.md (SVE_INT_BINARY): Add ashift,
ashiftrt and lshiftrt.
(sve_int_op, sve_int_op_rev, sve_pred_int_rhs2_operand): Handle them.
* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_2_const)
(*cond_<optab><mode>_any_const): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_shift_1.c: New test.
* gcc.target/aarch64/sve/cond_shift_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_2.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_3.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_4.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_5.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_6.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_6_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_7.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_7_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_8.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_8_run.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_9.c: Likewise.
* gcc.target/aarch64/sve/cond_shift_9_run.c: Likewise.

Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
From-SVN: r274505

Clean next_nested properly.

2019-08-15  Martin Liska  <mliska@suse.cz>

PR ipa/91438
* cgraph.c (cgraph_node::remove): When setting
n->origin = NULL for all nested functions, reset
also next_nested.

From-SVN: r274504

Add ::verify for cgraph_node::origin/nested/next_nested.

2019-08-15  Martin Liska  <mliska@suse.cz>

* cgraph.c (cgraph_node::verify_node): Verify origin, nested
and next_nested.

From-SVN: r274503

Properly register dead cgraph_nodes in passes.c.

2019-08-15  Martin Liska  <mliska@suse.cz>

PR ipa/91404
* passes.c (order): Remove.
(uid_hash_t): Likewise).
(remove_cgraph_node_from_order): Remove from set
of pointers (cgraph_node *).
(insert_cgraph_node_to_order): New.
(duplicate_cgraph_node_to_order): New.
(do_per_function_toporder): Register all 3 cgraph hooks.
Skip removed_nodes now as we know about all of them.

From-SVN: r274502

Daily bump.

From-SVN: r274501

PR testsuite/91449 - new test case gcc.dg/strlenopt-73.c fails on powerpc64

gcc/testsuite/ChangeLog:
* gcc.dg/strlenopt-73.c: Restrict 128-bit tests to i386.

From-SVN: r274495

PR c++/91436 fix C++ dialect for std::make_unique fix-it hint

The std::make_unique function wasn't added until C++14, and neither was
the std::complex_literals namespace.

gcc/cp:

PR c++/91436
* name-lookup.c (get_std_name_hint): Fix min_dialect field for
complex_literals and make_unique entries.

gcc/testsuite:

PR c++/91436
* g++.dg/lookup/missing-std-include-5.C: Limit test to C++14 and up.
* g++.dg/lookup/missing-std-include-6.C: Don't check make_unique in
test that runs for C++11.
* g++.dg/lookup/missing-std-include-8.C: Check make_unique here.

From-SVN: r274492

Deprecate std::__is_nullptr_t type trait

This non-standard extension is redundant and unused by the library.

* include/std/type_traits (__is_nullptr_t): Add deprecated attribute.

From-SVN: r274491

i386-expand.c (ix86_expand_vector_init_one_nonzero): Use vector_set path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.

* config/i386/i386-expand.c (ix86_expand_vector_init_one_nonzero)
<case E_V8QImode>: Use vector_set path for
TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
(ix86_expand_vector_init_one_nonzero) <case E_V8QImode>:
Do not widen for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.

From-SVN: r274490

noinit-attribute.c: Fix typo.

2019-08-14  Christophe Lyon  <christophe.lyon@linaro.org>

* gcc.c-torture/execute/noinit-attribute.c: Fix typo.

From-SVN: r274489

Implement C++20 p0879 - Constexpr for swap and swap related functions.

2019-08-14  Edward Smith-Rowland  <3dw4rd@verizon.net>

Implement C++20 p0879 - Constexpr for swap and swap related functions.
* include/std/version (__cpp_lib_constexpr_swap_algorithms): New macro.
* include/bits/algorithmfwd.h (__cpp_lib_constexpr_swap_algorithms):
New macro.
(iter_swap, make_heap, next_permutation, partial_sort_copy, pop_heap)
(prev_permutation, push_heap, reverse, rotate, sort_heap, swap)
(swap_ranges, nth_element, partial_sort, sort): Add constexpr.
* include/bits/move.h (swap): Add constexpr.
* include/bits/stl_algo.h (__move_median_to_first, __reverse, reverse)
(__gcd, __rotate, rotate, __partition, __heap_select)
(__partial_sort_copy, partial_sort_copy, __unguarded_partition)
(__unguarded_partition_pivot, __partial_sort, __introsort_loop, __sort)
(__introselect, __chunk_insertion_sort, next_permutation)
(prev_permutation, partition, partial_sort, nth_element, sort)
(__iter_swap::iter_swap, iter_swap, swap_ranges): Add constexpr.
* include/bits/stl_algobase.h (__iter_swap::iter_swap, iter_swap)
(swap_ranges): Add constexpr.
* include/bits/stl_heap.h (__push_heap, push_heap, __adjust_heap,
__pop_heap, pop_heap, __make_heap, make_heap, __sort_heap, sort_heap):
Add constexpr.
* include/std/type_traits (swap): Add constexpr.
* testsuite/25_algorithms/headers/algorithm/synopsis.cc: Add constexpr.
* testsuite/25_algorithms/iter_swap/constexpr.cc: New test.
* testsuite/25_algorithms/make_heap/constexpr.cc: New test.
* testsuite/25_algorithms/next_permutation/constexpr.cc: New test.
* testsuite/25_algorithms/nth_element/constexpr.cc: New test.
* testsuite/25_algorithms/partial_sort/constexpr.cc: New test.
* testsuite/25_algorithms/partial_sort_copy/constexpr.cc: New test.
* testsuite/25_algorithms/partition/constexpr.cc: New test.
* testsuite/25_algorithms/pop_heap/constexpr.cc: New test.
* testsuite/25_algorithms/prev_permutation/constexpr.cc: New test.
* testsuite/25_algorithms/push_heap/constexpr.cc: New test.
* testsuite/25_algorithms/reverse/constexpr.cc: New test.
* testsuite/25_algorithms/rotate/constexpr.cc: New test.
* testsuite/25_algorithms/sort/constexpr.cc: New test.
* testsuite/25_algorithms/sort_heap/constexpr.cc: New test.
* testsuite/25_algorithms/swap/constexpr.cc: New test.
* testsuite/25_algorithms/swap_ranges/constexpr.cc: New test.

From-SVN: r274488

builtins.c (expand_builtin_init_descriptor): Set memory alignment.

2019-08-14  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        * builtins.c (expand_builtin_init_descriptor): Set memory alignment.

From-SVN: r274487

PR tree-optimization/91294 - [10 Regression] wrong strlen result of a conditional with an offset

gcc/testsuite/ChangeLog:

PR tree-optimization/91294
* gcc.dg/strlenopt-44.c: Adjust tested result.
* gcc.dg/strlenopt-70.c: Avoid exercising unimplemnted optimization.
* gcc.dg/strlenopt-73.c: New test.
* gcc.dg/strlenopt-74.c: New test.
* gcc.dg/strlenopt-75.c: New test.
* gcc.dg/strlenopt-76.c: New test.
* gcc.dg/strlenopt-77.c: New test.

gcc/ChangeLog:

PR tree-optimization/91294
* tree-ssa-strlen.c (handle_store): Avoid treating lower bound of
source length as exact.

From-SVN: r274486

PR c++/91391 - bogus -Wcomma-subscript warning.

* parser.c (cp_parser_postfix_open_square_expression): Don't warn about
a deprecated comma here.  Pass warn_comma_subscript down to
cp_parser_expression.
(cp_parser_expression): New bool parameter.  Warn about uses of a comma
operator within a subscripting expression.
(cp_parser_skip_to_closing_square_bracket): Revert to pre-r274121 state.
(cp_parser_skip_to_closing_square_bracket_1): Remove.

* g++.dg/cpp2a/comma5.C: New test.

Co-Authored-By: Marek Polacek <polacek@redhat.com>
From-SVN: r274483

Add generic support for noinit attribute.

    Similar to what already exists for TI msp430 or in TI compilers for
    arm, this patch adds support for the "noinit" attribute.

    It is convenient for embedded targets where the user wants to keep the
    value of some data when the program is restarted: such variables are
    not zero-initialized. It is mostly a helper/shortcut to placing
    variables in a dedicated section.

    It's probably desirable to add the following chunk to the GNU linker:
    diff --git a/ld/emulparams/armelf.sh b/ld/emulparams/armelf.sh
    index 272a8bc..9555cec 100644
    --- a/ld/emulparams/armelf.sh
    +++ b/ld/emulparams/armelf.sh
    @@ -10,7 +10,19 @@ OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7)
    *(.vfp11_veneer) *(.v4_bx)'
     OTHER_BSS_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__bss_start__ =
    .${CREATE_SHLIB+)};"
     OTHER_BSS_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}_bss_end__ =
    .${CREATE_SHLIB+)}; ${CREATE_SHLIB+PROVIDE (}__bss_end__ =
    .${CREATE_SHLIB+)};"
     OTHER_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__end__ = .${CREATE_SHLIB+)};"
     -OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
     +OTHER_SECTIONS='
     +.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
     +  /* This section contains data that is not initialised during load
     +     *or* application reset.  */
     +   .noinit (NOLOAD) :
     +   {
     +     . = ALIGN(2);
     +     PROVIDE (__noinit_start = .);
     +     *(.noinit)
     +     . = ALIGN(2);
     +     PROVIDE (__noinit_end = .);
     +   }
     +'

    so that the noinit section has the "NOLOAD" flag.

    I added a testcase if gcc.c-torture/execute, gated by the new noinit
    effective-target.

    Finally, I tested on arm-eabi, but not on msp430 for which I do not
    have the environment.

gcc/ChangeLog:

2019-08-14  Christophe Lyon  <christophe.lyon@linaro.org>

* doc/extend.texi: Add "noinit" attribute documentation.
* doc/sourcebuild.texi: Add noinit effective target documentation.
* varasm.c (default_section_type_flags): Add support for "noinit" section.
(default_elf_select_section): Add support for "noinit" attribute.
* config/msp430/msp430.c (msp430_attribute_table): Remove "noinit" entry.

gcc/c-family/ChangeLog:

2019-08-14  Christophe Lyon  <christophe.lyon@linaro.org>

* c-attribs.c (c_common_attribute_table): Add "noinit" entry. Add
exclusion with "section" attribute.
(attr_noinit_exclusions): New table.
(handle_noinit_attribute): New function.

gcc/testsuite/ChangeLog:

2019-08-14  Christophe Lyon  <christophe.lyon@linaro.org>

* lib/target-supports.exp (check_effective_target_noinit): New
proc.
* gcc.c-torture/execute/noinit-attribute.c: New test.

From-SVN: r274482

re PR rtl-optimization/91154 (456.hmmer regression on Haswell caused by r272922)

2019-08-14  Richard Biener  <rguenther@suse.de>
        Uroš Bizjak  <ubizjak@gmail.com>

PR target/91154
* config/i386/i386-features.h (scalar_chain::scalar_chain): Add
mode arguments.
(scalar_chain::smode): New member.
(scalar_chain::vmode): Likewise.
(dimode_scalar_chain): Rename to...
(general_scalar_chain): ... this.
(general_scalar_chain::general_scalar_chain): Take mode arguments.
(timode_scalar_chain::timode_scalar_chain): Initialize scalar_chain
base with TImode and V1TImode.
* config/i386/i386-features.c (scalar_chain::scalar_chain): Adjust.
(general_scalar_chain::vector_const_cost): Adjust for SImode
chains.
(general_scalar_chain::compute_convert_gain): Likewise.  Add
{S,U}{MIN,MAX} support.
(general_scalar_chain::replace_with_subreg): Use vmode/smode.
(general_scalar_chain::make_vector_copies): Likewise.  Handle
non-DImode chains appropriately.
(general_scalar_chain::convert_reg): Likewise.
(general_scalar_chain::convert_op): Likewise.
(general_scalar_chain::convert_insn): Likewise.  Add
fatal_insn_not_found if the result is not recognized.
(convertible_comparison_p): Pass in the scalar mode and use that.
(general_scalar_to_vector_candidate_p): Likewise.  Rename from
dimode_scalar_to_vector_candidate_p.  Add {S,U}{MIN,MAX} support.
(scalar_to_vector_candidate_p): Remove by inlining into single
caller.
(general_remove_non_convertible_regs): Rename from
dimode_remove_non_convertible_regs.
(remove_non_convertible_regs): Remove by inlining into single caller.
(convert_scalars_to_vector): Handle SImode and DImode chains
in addition to TImode chains.
* config/i386/i386.md (<maxmin><MAXMIN_IMODE>3): New expander.
(*<maxmin><MAXMIN_IMODE>3_1): New insn-and-split.
(*<maxmin>di3_doubleword): Likewise.

* gcc.target/i386/pr91154.c: New testcase.
* gcc.target/i386/minmax-3.c: Likewise.
* gcc.target/i386/minmax-4.c: Likewise.
* gcc.target/i386/minmax-5.c: Likewise.
* gcc.target/i386/minmax-6.c: Likewise.
* gcc.target/i386/minmax-1.c: Add -mno-stv.
* gcc.target/i386/minmax-2.c: Likewise.

Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>
From-SVN: r274481

[AArch64] Use SVE BIC for conditional arithmetic

This patch uses BIC to pattern-match conditional AND with an inverted
third input.  It also adds extra tests for AND, ORR and EOR.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md (*cond_bic<mode>_2)
(*cond_bic<mode>_any): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_logical_1.c: New test.
* gcc.target/aarch64/sve/cond_logical_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_2.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_3.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_4.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_5.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_5_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274480

[AArch64] Use SVE UXT[BHW] as a form of predicated AND

UXTB, UXTH and UXTW are equivalent to predicated ANDs with the constants
0xff, 0xffff and 0xffffffff respectively.  This patch uses them in the
patterns for IFN_COND_AND.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_print_operand): Allow %e to
take the equivalent mask, as well as a bit count.
* config/aarch64/predicates.md (aarch64_sve_uxtb_immediate)
(aarch64_sve_uxth_immediate, aarch64_sve_uxt_immediate)
(aarch64_sve_pred_and_operand): New predicates.
* config/aarch64/iterators.md (sve_pred_int_rhs2_operand): New
code attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_INT_BINARY:optab><SVE_I:mode>): Use it.
(*cond_uxt<mode>_2, *cond_uxt<mode>_any): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_uxt_1.c: New test.
* gcc.target/aarch64/sve/cond_uxt_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_2.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_3.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_4.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_4_run.c: Likewise.

From-SVN: r274479

[AArch64] Add SVE conditional conversion patterns

This patch adds patterns to match conditional conversions between
integers and like-sized floats.  The patterns are actually more
general than that, but the other combinations can only be tested
via the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FCVTI:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
(*cond_<SVE_COND_ICVTF:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>):
New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_convert_1.c: New test.
* gcc.target/aarch64/sve/cond_convert_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_2.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_3.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_5.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_6.c: Likewise.
* gcc.target/aarch64/sve/cond_convert_6_run.c: Likewise.

From-SVN: r274478

[AArch64] Add SVE conditional floating-point unary patterns

This patch adds patterns to match conditional unary operations
on floating-point modes.  At the moment we rely on combine to merge
separate arithmetic and vcond_mask operations, and since the latter
doesn't accept zero operands, we miss out on the opportunity to use
the movprfx /z alternative.  (This alternative is tested by the ACLE
patches though.)

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_2): New pattern.
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_any): Likewise.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_unary_1.c: Add tests for
floating-point types.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_3.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_4.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274477

[AArch64] Add SVE conditional integer unary patterns

This patch adds patterns to match conditional unary operations
on integers.  At the moment we rely on combine to merge separate
arithmetic and vcond_mask operations, and since the latter doesn't
accept zero operands, we miss out on the opportunity to use the
movprfx /z alternative.  (This alternative is tested by the ACLE
patches though.)

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_2): New pattern.
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_any): Likewise.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_unary_1.c: New test.
* gcc.target/aarch64/sve/cond_unary_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_3.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_4_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274476

Add more entries to the C++ get_std_name_hint array

* name-lookup.c (get_std_name_hint): Add more entries.

From-SVN: r274475

[Ada] Improve performance of Containers.Functional_Base

This patch modifies the implementation of Functional_Base to damp the
cost of its subprograms at runtime in specific cases. Instead of copying
the entire underlying array to create a new container, containers can
share the same Array_Base attribute. Performance on common use cases of
formal and functional containers is improved with this patch.

2019-08-14  Joffrey Huguet  <huguet@adacore.com>

gcc/ada/

* libgnat/a-cofuba.ads: Add a Length attribute to type
Container. Add a type Array_Base which replaces the previous
Elements attribute of Container.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
* libgnat/a-cofuba.adb (Resize): New subprogram. It is used to
resize the underlying array of a container if necessary.
(=, <=, Find, Get, Intersection, Length, Num_Overlaps, Set,
Union): Update to match changes in type declarations.
(Add): Modify body to damp the time and space cost in a specific
case.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
(Remove): Modify body to damp the time and space cost in a
specific case.

From-SVN: r274474

[Ada] Alignment may be specified as zero

An Alignment clause or an aspect_specification for Alignment may be
specified as 0, which is treated the same as 1.

2019-08-14  Bob Duff  <duff@adacore.com>

gcc/ada/

* sem_ch13.adb (Get_Alignment_Value): Return 1 for Alignment 0,
and do not give an error.
* doc/gnat_rm/representation_clauses_and_pragmas.rst: Update the
corresponding documentation.
* gnat_rm.texi: Regenerate.

gcc/testsuite/

* gnat.dg/alignment15.adb: New testcase.

From-SVN: r274473

[Ada] Further cleanup in inlining machinery

This is visible if you pass a very small number by means of -gnateinn.

2019-08-14  Eric Botcazou  <ebotcazou@adacore.com>

gcc/ada/

* inline.adb (Add_Pending_Instantiation): Fix off-by-one error
in the comparison against the maximum number of instantiations.

From-SVN: r274472

[Ada] Further cleanup in inlining machinery

No practical functional changes.

2019-08-14  Eric Botcazou  <ebotcazou@adacore.com>

gcc/ada/

* inline.adb (Add_Pending_Instantiation): Use greater-or-equal
in the comparison against the maximum number of instantiations.

From-SVN: r274471

[Ada] Do not crash with -gnatR3 on Ghost aspects

2019-08-14  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

* sem_aux.adb (Next_Rep_Item): If a node in the rep chain
involves a Ghost aspect it may have been replaced by a null
statement; use the original node to find next Rep_Item.
* repinfo.adb (List_Entities): Do not list an Ignored
Ghost_Entity, for which information may have been deleted.

From-SVN: r274470

[Ada] Warn about unknown condition in Compile_Time_Warning

The compiler now warns if the condition in a pragma Compile_Time_Warning
or Compile_Time_Error does not have a compile-time-known value. The
warning is not given for pragmas in a generic template, but is given for
pragmas in an instance.

The -gnatw_c and -gnatw_C switches turn the warning on and off. The
default is on.

2019-08-14  Bob Duff  <duff@adacore.com>

gcc/ada/

* sem_prag.ads, sem_prag.adb
(Process_Compile_Time_Warning_Or_Error): In parameterless
version, improve detection of whether we are in a generic unit
to cover the case of an instance within a generic unit.
(Process_Compile_Time_Warning_Or_Error): Rename the
two-parameter version to be
Validate_Compile_Time_Warning_Or_Error, and do not export it.
Issue a warning if the condition is not known at compile time.
The key point is that the warning must be given only for pragmas
deferred to the back end, because the back end discovers
additional values that are known at compile time.  Previous
changes in this ticket have enabled this by deferring to the
back end without checking for special cases such as 'Size.
(Validate_Compile_Time_Warning_Or_Error): Rename to be
Defer_Compile_Time_Warning_Error_To_BE.
* warnsw.ads, warnsw.adb (Warn_On_Unknown_Compile_Time_Warning):
Add new switches -gnatw_c and -gnatw_C to control the above
warning.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Document new switches.
* gnat_ugn.texi: Regenerate.

gcc/testsuite/

* gnat.dg/warn27.adb: New testcase.

From-SVN: r274469

[Ada] Further cleanup in the inlining machinery

2019-08-14  Eric Botcazou  <ebotcazou@adacore.com>

gcc/ada/

* sem_ch12.adb (Might_Inline_Subp): Rework comment and restrict
the shortcut based on Is_Inlined to the back-end inlining case.

From-SVN: r274468

[Ada] Incorrect error on inline protected function

This patch fixes a bug where if a protected function has a pragma
Inline, and has no local variables, and the body consists of a single
extended_return_statement, and the result type is an indefinite
composite subtype, and inlining is enabled, the compiler gives an error,
even though the program is legal.

2019-08-14  Bob Duff  <duff@adacore.com>

gcc/ada/

* inline.adb (Check_And_Split_Unconstrained_Function): Ignore
protected functions to get rid of spurious error. The
transformation done by this procedure triggers legality errors
in the generated code in this case.

gcc/testsuite/

* gnat.dg/inline19.adb, gnat.dg/inline19.ads: New testcase.

From-SVN: r274467