git.libre-soc.org Git - binutils-gdb.git/log

PowerPC table driven -Mraw disassembly

opcodes/
* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
Don't special case PPC_OPCODE_RAW.
(lookup_prefix): Likewise.
(lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
(print_insn_powerpc): ..update caller.
* ppc-opc.c (EXT): Define.
(powerpc_opcodes): Mark extended mnemonics with EXT.
(prefix_opcodes, vle_opcodes): Likewise.
(XISEL, XISEL_MASK): Add cr field and simplify.
(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
all isel variants to where the base mnemonic belongs. Sort dstt,
dststt and dssall.
gas/
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.

readelf and objdump help

Splitting up help strings makes it more likely that at least some of
the help translation survives adding new options.

* readelf.c (parse_args): Call dwarf_select_sections_all on
--debug-dump without optarg.
(usage): Associate -w and --debug-dump options closely.
Split up help message. Remove extraneous blank lines around
ctf help.
* objdump.c (usage): Similarly.

sim: bfin: fix the otp fix fix

Need to shift the upper 32-bits and not just combine directly with
the lower 32-bits.

MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions

Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.

With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.

opcodes/
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
COP3 opcode instructions.

MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests

Add tests for the generic C0, C1, C2, C3 coprocessor instructions.

gas/
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

MIPS/GAS/testsuite: Run RFE test across all ISAs

Verify that the RFE instruction is not only accepted where supported,
but rejected where it is not as well.

gas/
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.

MIPS/GAS/testsuite: Run coprocessor tests across all ISAs

Verify that individual coprocessor instructions are not only accepted
where supported, but rejected where they are not as well.

gas/
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3d.d: New test.
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.

MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership

Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:

- remove CP0 memory access instructions from MIPS II up as the LWC0 and
  SWC0 opcodes have been reused for the LL and SC instructions
  respectively[1]; strictly speaking LWC0 and SWC0 have never really
  been defined in the first place[2], but let's keep them for now in
  case an odd implementation did,

- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
  they have been removed as from those ISAs,

- remove CP0 control register move instructions from MIPS32 up, as they
  have been removed as from that ISA[5],

- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
  has been removed as from those ISAs in favour to ERET,

- remove CP2 instructions from Vr5400 CPUs as their encodings have been
  reused for the multimedia instruction set extensions[8] and no CP2
  registers exist[9],

- remove CP3 memory access instructions from MIPS III up as coprocessor
  3 has been removed as from that ISA[10][11] and from MIPS32 up as the
  LWC3 opcode has been reused for the PREF instruction and consequently
  all the four memory access instructions removed from the ISA (though
  the COP3 opcode has been retained)[12].

Update the testsuite accordingly.

References:

[1]  Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
     Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
     - MIPS II Architecture", p. A-178

[2]  same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12

[3]  "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
     Technologies, Inc., January 29, 1997, Section 14.25 "CP0
     Instructions", Subsection "Branch on Coprocessor 0", p. 285

[4]  "MIPS32 Architecture For Programmers, Volume II: The MIPS32
     Instruction Set", MIPS Technologies, Inc., Document Number:
     MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
     Encoding of rs Field", p. 242

[5]  same

[6]  Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
     Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
     Opcode Bit Encoding", p. A-182

[8]  "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
     NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
     Section 1.2.3 "CPU Instruction Set Overview", p. 9

[9]  "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
     NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
     Section 19.2 "Multimedia Instruction Format", p. 681

[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
     Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
     COP3 and CP3 load/store", p. A-176

[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
     Architecture", p. A-179

[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
     Instruction Set", MIPS Technologies, Inc., Document Number:
     MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
     of the Opcode Field", p. 241

opcodes/
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
"cop2", and "cop3" entries.

gas/
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.

MIPS/opcodes: Remove DMFC3 and DMTC3 instructions

Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2]
with the LDC3 and SDC3 instructions having been replaced with LD and SD
instructions respectively and therefore the doubleword move instructions
from and to that coprocessor have never materialized (for 32-bit ISAs
coprocessor 3 has likewise been removed as from MIPS32r2[3]).  Remove
the DMFC3 and DMTC3 instructions from the opcode table then to avoid
confusion.

References:

[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
    Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3
    and CP3 load/store", p. A-176

[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture",
    p. A-179

[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
    Opcode Field", p. 317

opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
entries and associated comments.

MIPS/GAS/testsuite: Add tests for coprocessor branch instructions

Cover basic CP0, CP2, CP3 branch and branch-likely instructions across
the relevant ISA levels. Omit CP1 branches, covered elsewhere.

gas/
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

MIPS/opcodes: Disassemble the RFE instruction

Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.

It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:

  00: 42000010 c0 0x10

to be produced rather than:

  00: 42000010 rfe

even for ISA levels that do include the RFE instruction.

Move the "rfe" entry ahead of "c0" then, correcting the problem.  Add a
suitable test case.

opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".

gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.

MIPS/opcodes: Properly handle ISA exclusion

Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.

include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.

MIPS/opcodes: Factor out ISA matching against flags

In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.

include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.

MIPS/opcodes: Add legacy CP1 control register names

The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.

opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".

gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.

MIPS/GAS/testsuite: Add tests for coprocessor access instructions

Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.

gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

MIPS/opcodes: Do not use CP0 register names for control registers

The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1].  Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested.  This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart.  Consequently
nonsensical disassembly is produced like:

cfc0 v0,c0_random

Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.

Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take.  Adjust the
test cases affected accordingly.

While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.

References:

[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
    rs Field", p. 242

[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
    Instructions", pp. 195, 216

include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.

gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.

opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'.  Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.

binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.

MIPS/opcodes: Add TX39 CP0 register names

The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names.  Add a test case accordingly.

References:

[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
    Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
    coprocessor (CP0) registers", pp. 9-10

opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".

gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.

MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases

Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:

mipsisa32r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux  -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3

This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled.  The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.

binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.

MIPS/opcodes: Free up redundant `g' operand code

In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.

Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.

Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.

opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.

include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.

microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1

The DMTC1 instruction operates on a floating-point general register as
its second operand, however in the disassembly of the microMIPS encoding
a floating-point control register is shown instead.  This is due to an
incorrect ordering of the two "dmtc1" entries in the opcode table, which
gives precedence to one using the `G' aka coprocessor format over one
using the `S' or floating-point register format.

The coprocessor format, or OP_REG_COPRO, is used so that GAS supports
referring to FPRs by their numbers in assembly, such as $0, $1, etc.
however in the case of CP1/FPU it is also used by the disassembler to
decode those numbers to the names of corresponding control registers.
This in turn causes nonsensical disassembly such as:

dmtc1 a1,c1_fir

in a reference to $f0.  It has been like this ever since microMIPS ISA
support has been added.

Correct the ordering of the two entries then by swapping them with each
other, making disassembly output consistent with the regular MIPS DMTC1
instruction as well all the remaining CP1 move instructions.  Adjust all
the test cases affected accordingly.

opcodes/
* micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
entries with each other.

gas/
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.

MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1

Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.

gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.

Automatic date update in version.in

x86: Restore PC16 relocation overflow check

The x86-64 psABI has

---
A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16
or R_X86_64_PC8 relocations is not conformant to this ABI, these
relocations are only added for documentation purposes.
---

Since x86 PC16 relocations have been used for 16-bit programs in an ELF32
or ELF64 container, PC16 relocation should wrap-around in 16-bit address
space.  Revert

commit a7664973b24a242cd9ea17deb5eaf503065fc0bd
Author: Jan Beulich <jbeulich@suse.com>
Date:   Mon Apr 26 10:41:35 2021 +0200

    x86: correct overflow checking for 16-bit PC-relative relocs

and xfail the related tests.  Also revert

commit 50c95a739c91ae70cf8481936611aa1f5397a384
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed May 26 12:13:13 2021 -0700

    x86: Propery check PC16 reloc overflow in 16-bit mode instructions

while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs.

bfd/

PR ld/27905
* elf32-i386.c: Don't include "libiberty.h".
(elf_howto_table): Revert commits a7664973b24 and 50c95a739c9.
(elf_i386_rtype_to_howto): Revert commit 50c95a739c9.
(elf_i386_info_to_howto_rel): Likewise.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Revert commits
a7664973b24 and 50c95a739c9.
(elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise.
* elfxx-x86.h (elf_x86_obj_tdata): Likewise.
(elf_x86_has_code16): Likewise.

binutils/

PR ld/27905
* readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9.

gas/

PR ld/27905
* config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Likewise.
* testsuite/gas/i386/code16-2.d: Updated.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.

include/

PR ld/27905
* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed.

ld/

PR ld/27905
* testsuite/ld-i386/pcrel16-2.d: xfail.
* testsuite/ld-x86-64/pcrel16-2.d: Likewise.

sim: h8300 add special case test.

* addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>.
* andb.s: Likewise.
* cmpb.s: Likewise.
* orb.s: Likewise.
* subb.s: Likewise.
* xorb.s: Likewise.
* movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>
@reg+,@reg+ / @-reg,@-reg.
* movw.s: Likewise.
* movl.s: Likewise.

sim: h8300 Fixed different behavior in preinc/predec.

* sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC.
* compile.c (decode): Rewrite oprand type for specific case.
(fetch_1): Add handling OP_REG_DEC and OP_REG_INC.
(step_once): Fix operand fetch order.

Automatic date update in version.in

PowerPC: Add new xxmr and xxlnot extended mnemonics

opcodes/
* ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.

gas/
* testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests.
* testsuite/gas/ppc/vsx.s: Likewise.

gdb: fix tab after space indentation issues

I spotted some indentation issues where we had some spaces followed by
tabs at beginning of line, that I wanted to fix. So while at it, I did
a quick grep to find and fix all I could find.

gdb/ChangeLog:

* Fix tab after space indentation issues throughout.

Change-Id: I1acb414dd9c593b474ae2b8667496584df4316fd

gdb: fix some indentation issues

I wrote a small script to spot a pattern of indentation mistakes I saw
happened in breakpoint.c. And while at it I ran it on all files and
fixed what I found. No behavior changes intended, just indentation and
addition / removal of curly braces.

gdb/ChangeLog:

* Fix some indentation mistakes throughout.

gdbserver/ChangeLog:

* Fix some indentation mistakes throughout.

Change-Id: Ia01990c26c38e83a243d8f33da1d494f16315c6e

gdb: remove iterate_over_bp_locations function

Remove it, change users (well, a single one) to use all_bp_locations.
This requires moving all_bp_locations to breakpoint.h to expose it.

gdb/ChangeLog:

* breakpoint.h (iterate_over_bp_locations): Remove. Update
users to use all_bp_locations.
(all_bp_locations): New.
* breakpoint.c (all_bp_locations): Make non-static.
(iterate_over_bp_locations): Remove.

Change-Id: Iaf1f716d6c2c5b2975579b3dc113a86f5d0975be

gdb: remove iterate_over_breakpoints function

Now that we have range functions that let us use ranged for loops, we
can remove iterate_over_breakpoints in favor of those, which are easier
to read and write. This requires exposing the declaration of
all_breakpoints and all_breakpoints_safe in breakpoint.h, as well as the
supporting types.

Change some users of iterate_over_breakpoints to use all_breakpoints,
when they don't need to delete the breakpoint, and all_breakpoints_safe
otherwise.

gdb/ChangeLog:

* breakpoint.h (iterate_over_breakpoints): Remove. Update
callers to use all_breakpoints or all_breakpoints_safe.
(breakpoint_range, all_breakpoints, breakpoint_safe_range,
all_breakpoints_safe): Move here.
* breakpoint.c (all_breakpoints, all_breakpoints_safe): Make
non-static.
(iterate_over_breakpoints): Remove.
* python/py-finishbreakpoint.c (bpfinishpy_detect_out_scope_cb):
Return void.
* python/py-breakpoint.c (build_bp_list): Add comment, reverse
return value logic.
* guile/scm-breakpoint.c (bpscm_build_bp_list): Return void.

Change-Id: Idde764a1f577de0423e4f2444a7d5cdb01ba5e48

gdb: add all_bp_locations_at_addr function

Add the all_bp_locations_at_addr function, which returns a range of all
breakpoint locations at exactly the given address.  This lets us
replace:

  bp_location *loc, **loc2p, *locp;
  ALL_BP_LOCATIONS_AT_ADDR (loc2p, locp, address)
    {
      loc = *loc2p;

      // use loc
    }

with

  for (bp_location *loc : all_bp_locations_at_addr (address))
    {
      // use loc
    }

The all_bp_locations_at_addr returns a bp_locations_at_addr_range
object, which is really just a wrapper around two std::vector iterators
representing the beginning and end of the interesting range.  These
iterators are found when constructing the bp_locations_at_addr_range
object using std::equal_range, which seems a perfect fit for this use
case.

One thing I noticed about the current ALL_BP_LOCATIONS_AT_ADDR is that
if you call it with a NULL start variable, that variable gets filled in
and can be re-used for subsequent iterations.  This avoids the cost of
finding the start of the interesting range again for the subsequent
iterations.  This happens in build_target_command_list, for example.
The same effect can be achieved by storing the range in a local
variable, it can be iterated on multiple times.

Note that the original comment over ALL_BP_LOCATIONS_AT_ADDR says:

    Iterates through locations with address ADDRESS for the currently
    selected program space.

I don't see anything restricting the iteration to a given program space,
as we iterate over all bp_locations, which as far as I know contains all
breakpoint locations, regardless of the program space.  So I just
dropped that part of the comment.

gdb/ChangeLog:

* breakpoint.c (get_first_locp_gte_addr): Remove.
(ALL_BP_LOCATIONS_AT_ADDR): Remove.  Replace all uses with
all_bp_locations_at_addr.
(struct bp_locations_at_addr_range): New.
(all_bp_locations_at_addr): New.
(bp_locations_compare_addrs): New.

Change-Id: Icc8c92302045c47a48f507b7f1872bdd31d4ba59

gdb: add all_bp_locations function

Add the all_bp_locations function to replace the ALL_BP_LOCATIONS macro.
For simplicity, all_bp_locations simply returns a const reference to the
bp_locations vector. But the callers just treat it as a range to
iterate on, so if we ever change the breakpoint location storage, we can
change the all_bp_locations function to return some other range type,
and the callers won't need to be changed.

gdb/ChangeLog:

* breakpoint.c (ALL_BP_LOCATIONS): Remove, update users to use
all_bp_locations.
(all_bp_locations): New.

Change-Id: Iae71a1ba135c1a5bcdb4658bf3cf9793f0e9f81c

gdb: make bp_locations an std::vector

Change the type of the global location list, bp_locations, to be an
std::vector.

Adjust the users to deal with that, mostly in an obvious way by using
.data() and .size().  The user where it's slightly less obvious is
update_global_location_list.  There, we std::move the old location list
out of the global vector into a local variable.  The code to fill the
new location list gets simpler, as it's now simply using .push_back(),
no need to count the locations beforehand.

In the rest of update_global_location_list, the code is adjusted to work
with indices instead of `bp_location **`, to iterate on the location
list.  I believe it's a bit easier to understand this way.  But more
importantly, when we build with _GLIBCXX_DEBUG, the operator[] of the
vector does bound checking, so we will know if we ever access past a
vector size (which we won't if we access by raw pointer).  I think that
work can further be done to make that function easier to understand,
notably find better names than "loc" and "loc2" for variables, but
that's work for later.

gdb/ChangeLog:

* breakpoint.c (bp_locations): Change to std::vector, update all
users.
(bp_locations_count): Remove.
(update_global_location_list): Change to work with indices
rather than bp_location**.

Change-Id: I193ce40f84d5dc930fbab8867cf946e78ff0df0b

gdb: add breakpoint::locations method

Add the breakpoint::locations method, which returns a range that can be
used to iterate over a breakpoint's locations.  This shortens

  for (bp_location *loc = b->loc; loc != nullptr; loc = loc->next)

into

  for (bp_location *loc : b->locations ())

Change all the places that I found that could use it.

gdb/ChangeLog:

* breakpoint.h (bp_locations_range): New.
(struct breakpoint) <locations>: New.  Use where possible.

Change-Id: I1ba2f7d93d57e544e1f8609124587dcf2e1da037

gdb: add all_tracepoints function

Same idea as the previous patches, but to replace the ALL_TRACEPOINTS
macro.  Define a new filtered_iterator that only keeps the breakpoints
for which is_tracepoint returns true (just like the macro did).

I would have like to make it so tracepoint_range yields some
`tracepoint *` instead of some `breakpoint *`, that would help simplify
the callers, who wouldn't have to do the cast themselves.  But I didn't
find an obvious way to do it.  It can always be added later.

It turns out there is already an all_tracepoints function, which returns
a vector containing all the breakpoints that are tracepoint.  Remove it,
most users will just work seamlessly with the new function.  The
exception is start_tracing, which iterated multiple times on the vector.
Adapt this one so it iterates multiple times on the returned range.

Since the existing users of all_tracepoints are outside of breakpoint.c,
this requires defining all_tracepoints and a few supporting types in
breakpoint.h.  So, move breakpoint_iterator from breakpoint.c to
breakpoint.h.

gdb/ChangeLog:

* breakpoint.h (all_tracepoints): Remove.
(breakpoint_iterator): Move here.
(struct tracepoint_filter): New.
(tracepoint_iterator): New.
(tracepoint_range): New.
(all_tracepoints): New.
* breakpoint.c (ALL_TRACEPOINTS): Remove, replace all users with
all_tracepoints.
(breakpoint_iterator): Move to header.
(all_tracepoints): New.
* tracepoint.c (start_tracing): Adjust.

Change-Id: I76b1bba4215dbec7a03846c568368aeef7f1e05a

gdb: add all_breakpoints_safe function

Same as the previous patch, but intended to replace the
ALL_BREAKPOINTS_SAFE macro, which allows deleting the current breakpoint
while iterating.  The new range type simply wraps the range added by the
previous patch with basic_safe_range.

I didn't remove the ALL_BREAKPOINTS_SAFE macro, because there is one
spot where it's more tricky to remove, in the
check_longjmp_breakpoint_for_call_dummy function.  More thought it
needed for this one.

gdb/ChangeLog:

* breakpoint.c (breakpoint_safe_range): New.
(all_breakpoints_safe): New.  Use instead of
ALL_BREAKPOINTS_SAFE where possible.

Change-Id: Ifccab29f135e1f85700e3697ed60f0b643c7682f

gdb: add all_breakpoints function

Introduce the all_breakpoints function, which returns a range that can
be used to iterate on breakpoints. Replace all uses of the
ALL_BREAKPOINTS macro with this.

In one instance, I could replace the breakpoint iteration with a call to
get_breakpoint.

gdb/ChangeLog:

* breakpoint.c (ALL_BREAKPOINTS): Remove, replace all uses with
all_breakpoints.
(breakpoint_iterator): New.
(breakpoint_range): New.
(all_breakpoints): New.

Change-Id: I229595bddad7c9100b179a9dd56b04b8c206e86c

Add optional full_window argument to TuiWindow.write

To prevent flickering when first calling erase, then write, this new
argument indicates that the passed string contains the full contents of
the window.  This fills every unused cell of the window with a space, so
it's not necessary to call erase beforehand.

gdb/ChangeLog:

2021-05-27  Hannes Domani  <ssbssa@yahoo.de>

* python/py-tui.c (tui_py_window::output): Add full_window
argument.
(gdbpy_tui_write): Parse "full_window" argument.

gdb/doc/ChangeLog:

2021-05-27  Hannes Domani  <ssbssa@yahoo.de>

* python.texi (TUI Windows In Python): Document "full_window"
argument.

gdb: add option to reverse order of _initialize function calls

An earlier patch in this series fixed a dependency problem between two
_initialize functions.  That problem was uncovered by reversing the
order of the initialize function calls.

In short, symtab.c tried to add the alias "maintenance
flush-symbol-cache" for the command "maintenance flush symbol-cache".
Because the "maintenance flush" prefix command was not yet created (it
happens in maint.c, initialized later in this reversed order), the
add_alias_cmd function returned NULL.  That result was passed to
deprecate_cmd, which didn't expected that value, and that caused a
segfault.  This was fixed by changing alias creation functions to take
the target command as a cmd_list_element, instead of by name.

This patch adds a runtime option to reverse the order of the initialize
calls at will.  I chose to use an environment variable for this, over a
parameter (even a "maintenance" one), because:

- The init functions are called before the early init commands are
   executed, so we could use -iex to turn this mode on early enough.
   This is obvious when you remember that commands / parameters are
   created by initialize funcitions :).

- This is not something anybody would want to tweak after startup
   anyway.

gdb/ChangeLog:

* make-init-c: Add option to reverse function calls.

gdb/testsuite/ChangeLog:

* gdb.base/reverse-init-functions.exp: New.

Change-Id: I543e609cf526e7cb145a006a794d0e6851b63f45

gdb: add make-init-c script

I would like to modify how the init.c file is generated (its content).
But as it is, a shell script with multiple sed invocations in a Makefile
target, it's not very maintainable.  Replace that with a shell script
that does the same, but in a more readable way.

The Makefile rule uses the "-" prefix in front of the for loop, I
presume to ignore any error coming from the fact that xml-builtin.c and
cp-name-parser.c are not found in the srcdir (they are generated source
files).  I prefer not to blindly ignore errors, so filter these files
out of INIT_FILES instead (we already filter out other files).

There are no expected meaningful changes to the generated init.c file.
Just the _initialize_all_file declaration that is moved down and "void"
in parenthesis that is removed.

The new regular expression is a bit tighter than the existing one, it
requires the init function to be followed by exactly ` ()`.  Update
bpf-tdep.c accordingly.

gdb/ChangeLog:

* Makefile.in (INIT_FILES_FILTER_OUT): New.
(INIT_FILES): Use INIT_FILES_FILTER_OUT.
(stamp-init): Use make-init-c.
* bpf-tdep.c (_initialize_bpf_tdep): Remove "void".
* silent-rules.mk (ECHO_INIT_C): Change.
* make-init-c: New file.

Change-Id: I6d6b12cbccf24ab79d1219bff05df01624c684f9

gdb: remove add_alias_cmd overload that accepts a string

Same idea as previous patch, but for add_alias_cmd. Remove the overload
that accepts the target command as a string (the target command name),
leaving only the one that takes the cmd_list_element.

gdb/ChangeLog:

* command.h (add_alias_cmd): Accept target as
cmd_list_element. Update callers.

Change-Id: I546311f411e9e7da9302322d6ffad4e6c56df266

gdb: make add_info_alias accept target as a cmd_list_element

Same idea as previous patch, but for add_info_alias.

gdb/ChangeLog:

* command.h (add_info_alias): Accept target as
cmd_list_element. Update callers.

Change-Id: If830d423364bf42d7bea5ac4dd3a81adcfce6f7a

gdb: make add_com_alias accept target as a cmd_list_element

The alias creation functions currently accept a name to specify the
target command.  They pass this to add_alias_cmd, which needs to lookup
the target command by name.

Given that:

- We don't support creating an alias for a command before that command
   exists.
- We always use add_info_alias just after creating that target command,
   and therefore have access to the target command's cmd_list_element.

... change add_com_alias to accept the target command as a
cmd_list_element (other functions are done in subsequent patches).  This
ensures we don't create the alias before the target command, because you
need to get the cmd_list_element from somewhere when you call the alias
creation function.  And it avoids an unecessary command lookup.  So it
seems better to me in every aspect.

gdb/ChangeLog:

* command.h (add_com_alias): Accept target as
cmd_list_element.  Update callers.

Change-Id: I24bed7da57221cc77606034de3023fedac015150

gdb/python: use return values of add_setshow functions in add_setshow_generic

In add_setshow_generic, we create set/show commands using add_setshow_*
functions, then look up the commands by name to set the context pointer.
It would be simpler and more efficient to use the return values of the
add_setshow_* functions, do that.

gdb/ChangeLog:

* python/py-param.c (add_setshow_generic): Use return values of
add_setshow functions.

Change-Id: I04d50736e1001ddb732d81e088468876df9c88ff

gdb: remove unnecessary lookup_cmd when deprecating commands

Remove a few instances where we look up a command by name, but could
just use the return value of a previous "add command" function call
instead.

gdb/ChangeLog:

* mi/mi-main.c (_initialize_mi_main):
* python/py-auto-load.c (gdbpy_initialize_auto_load):
* remote.c (_initialize_remote):

Change-Id: I6d06f9ca636e340c88c1064ae870483ad392607d

gdb: make add_setshow commands return set_show_commands

Some add_set_show commands return a single cmd_list_element, the one for
the "set" command.  A subsequent patch will need to access the show
command's cmd_list_element as well.  Change these functions to return a
new structure type that holds both pointers.

I initially only modified add_setshow_boolean_cmd (the one I needed),
but I think it's better to change the whole chain to keep everything in
sync.

gdb/ChangeLog:

* command.h (set_show_commands): New.
(add_setshow_enum_cmd, add_setshow_auto_boolean_cmd,
add_setshow_boolean_cmd, add_setshow_filename_cmd,
add_setshow_string_cmd, add_setshow_string_noescape_cmd,
add_setshow_optional_filename_cmd, add_setshow_integer_cmd,
add_setshow_uinteger_cmd, add_setshow_zinteger_cmd,
add_setshow_zuinteger_cmd, add_setshow_zuinteger_unlimited_cmd):
Return set_show_commands.  Adjust callers.
* cli/cli-decode.c (add_setshow_cmd_full): Return
set_show_commands, remove result parameters, adjust callers.

Change-Id: I17492b01b76002d09effc84830f9c6db26f1db7a

Document gdb.SYMBOL_LOC_LABEL

Looks like it was missing from the beginning.

gdb/doc/ChangeLog:

2021-05-27 Hannes Domani <ssbssa@yahoo.de>

* python.texi (Symbols In Python): Document gdb.SYMBOL_LOC_LABEL.

[gdb/symtab] Fix segfault in process_psymtab_comp_unit

When running test-case gdb.dwarf2/dw2-dummy-cu.exp without -readnow, we run
into:
...
(gdb) file outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu^M
Reading symbols from outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu...^M
ERROR: Couldn't load dw2-dummy-cu into GDB (eof).
...

The problem is that we're running into a segfault:
...
Thread 1 "gdb" received signal SIGSEGV, Segmentation fault.
process_psymtab_comp_unit (this_cu=0x2141090, per_objfile=0x1aa4140,
    want_partial_unit=false, pretend_language=language_minimal)
    at /home/vries/gdb_versions/devel/src/gdb/dwarf2/read.c:7023
7023      switch (reader.comp_unit_die->tag)
...
due to reader.comp_unit_die == nullptr:
...
(gdb) p reader.comp_unit_die
$1 = (die_info *) 0x0
...

Indeed, there's no CU DIE in the test-case:
...
$ readelf -wi outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu
Contents of the .debug_info section:

  Compilation Unit @ offset 0x0:
   Length:        0x7 (32-bit)
   Version:       2
   Abbrev Offset: 0x0
   Pointer Size:  4
$
...

Fix this by handling reader.comp_unit_die == nullptr in
process_psymtab_comp_unit.

Update the test-case to trigger this PR, as per PR27920 - "[gdb/testsuite]
hardcoding -readnow skips testing of partial symbols".

Tested on x86_64-linux.

gdb/ChangeLog:

2021-05-27  Tom de Vries  <tdevries@suse.de>

PR symtab/27919
* dwarf2/read.c (process_psymtab_comp_unit):

gdb/testsuite/ChangeLog:

2021-05-27  Tom de Vries  <tdevries@suse.de>

PR symtab/27919
PR testsuite/27920
* gdb.dwarf2/dw2-dummy-cu.exp: Use maint expand-symtabs instead of
-readnow.

[gdb/testsuite] Prevent proc override in gdb-index.exp

When running these two test-cases in this specific order we get:
...
$ make check 'RUNTESTFLAGS=gdb.dwarf2/gdb-index.exp \
    gdb.dwarf2/gdb-add-index-symlink.exp'
  ...
Running gdb.dwarf2/gdb-index.exp ...
Running gdb.dwarf2/gdb-add-index-symlink.exp ...
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: gdb-index file created
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: Unable to call \
  gdb-add-index with a symlink to a symfile
...

The problem is that gdb-index.exp introduces a proc add_gdb_index which
overrides the one in lib/gdb.exp and stays active after the test is done.
Consequently it's used in gdb-add-index-symlink.exp, which should use the one
from lib/gdb.exp.

Fix this by renaming proc add_gdb_index in gdb-index.exp.

Tested on x86_64-linux.

gdb/testsuite/ChangeLog:

2021-05-27  Tom de Vries  <tdevries@suse.de>

PR testsuite/27921
* gdb.dwarf2/gdb-index.exp (add_gdb_index): Rename to ...
(local_add_gdb_index): ... this.

[gdb/symtab] Fix typo in dwarf error message

Fix "Cannot not" typo in dwarf error message.

Tested on x86_64-linux.

gdb/ChangeLog:

2021-05-27 Tom de Vries <tdevries@suse.de>

* dwarf2/read.c (find_partial_die): Fix "Cannot not" typo in dwarf
error.

[gdb/symtab] Fix Dwarf Error: cannot find DIE

When loading the debug info package
libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug from openSUSE Leap 15.2, we
run into a dwarf error:
...
$ gdb -q -batch libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug
Dwarf Error: Cannot not find DIE at 0x18a936e7 \
  [from module libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug]
...
The DIE @ 0x18a936e7 does in fact exist, and is part of a CU @ 0x18a23e52.
No error message is printed when using -readnow.

What happens is the following:
- a dwarf2_per_cu_data P is created for the CU.
- a dwarf2_cu A is created for the same CU.
- another dwarf2_cu B is created for the same CU.
- the dwarf2_cu B is set in per_objfile->m_dwarf2_cus, such that
  per_objfile->get_cu (P) returns B.
- P->load_all_dies is set to 1.
- all dies are read into the A->partial_dies htab
- dwarf2_cu A is destroyed.
- we try to find the partial_die for the DIE @ 0x18a936e7 in B->partial_dies.
  We can't find it, but do not try to load all dies, because P->load_all_dies
  is already set to 1.
- an error message is generated.

The question is why we're creating dwarf2_cu A and B for the same CU.

The dwarf2_cu A is created here:
...
(gdb) bt
#0  dwarf2_cu::dwarf2_cu (this=0x79a9660, per_cu=0x23c0b30,
     per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1  0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffd040,
     this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
     existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2  0x0000000000676eb3 in process_psymtab_comp_unit (this_cu=0x23c0b30,
      per_objfile=0x1ad01b0, want_partial_unit=false,
      pretend_language=language_minimal) at dwarf2/read.c:7028
...

And the dwarf2_cu B is created here:
...
(gdb) bt
#0  dwarf2_cu::dwarf2_cu (this=0x885e8c0, per_cu=0x23c0b30,
     per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1  0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffcc50,
     this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
     existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2  0x0000000000678118 in load_partial_comp_unit (this_cu=0x23c0b30,
     per_objfile=0x1ad01b0, existing_cu=0x0) at dwarf2/read.c:7436
#3  0x000000000069721d in find_partial_die (sect_off=(unknown: 0x18a55054),
     offset_in_dwz=0, cu=0x0) at dwarf2/read.c:19391
#4  0x000000000069755b in partial_die_info::fixup (this=0x9096900,
     cu=0xa6a85f0) at dwarf2/read.c:19512
#5  0x0000000000697586 in partial_die_info::fixup (this=0x8629bb0,
     cu=0xa6a85f0) at dwarf2/read.c:19516
#6  0x00000000006787b1 in scan_partial_symbols (first_die=0x8629b40,
     lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
     at dwarf2/read.c:7563
#7  0x0000000000678878 in scan_partial_symbols (first_die=0x796ebf0,
     lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
     at dwarf2/read.c:7580
#8  0x0000000000676b82 in process_psymtab_comp_unit_reader
     (reader=0x7fffffffd040, info_ptr=0x7fffc1b3f29b, comp_unit_die=0x6ea90f0,
     pretend_language=language_minimal) at dwarf2/read.c:6954
#9  0x0000000000676ffd in process_psymtab_comp_unit (this_cu=0x23c0b30,
     per_objfile=0x1ad01b0, want_partial_unit=false,
     pretend_language=language_minimal) at dwarf2/read.c:7057
...

So in frame #9, a cutu_reader is created with dwarf2_cu A.  Then a fixup takes
us to the following CU @ 0x18aa33d6, in frame #5.  And a similar fixup in
frame #4 takes us back to CU @ 0x18a23e52.  At that point, there's no
information available that we're already trying to read that CU, and we end up
creating another cutu_reader with dwarf2_cu B.

It seems that there are two related problems:
- creating two dwarf2_cu's is not optimal
- the unoptimal case is not handled correctly

This patch addresses the last problem, by moving the load_all_dies flag from
dwarf2_per_cu_data to dwarf2_cu, such that it is paired with the partial_dies
field, which ensures that the two can be kept in sync.

Tested on x86_64-linux.

gdb/ChangeLog:

2021-05-27  Tom de Vries  <tdevries@suse.de>

PR symtab/27898
* dwarf2/cu.c (dwarf2_cu::dwarf2_cu): Add load_all_dies init.
* dwarf2/cu.h (dwarf2_cu): Add load_all_dies field.
* dwarf2/read.c (load_partial_dies, find_partial_die): Update.
* dwarf2/read.h (dwarf2_per_cu_data::dwarf2_per_cu_data): Remove
load_all_dies init.
(dwarf2_per_cu_data): Remove load_all_dies field.

Revert "gdb: change dwarf_die_debug to bool"

This was wrong: dwarf_die_debug is used as an integer, for example where
it is passed to dump_die. It is documented in the command's help, which
I missed the first time.

This reverts commit 749369c430d88c4abc9acde5cfc7b5218651de10.

Change-Id: I1d09c3da57f8885f4f9fe9f4eae0cf86006e617a

gdb: change dwarf_die_debug to bool

gdb/ChangeLog:

* dwarf2/read.c (dwarf_die_debug): Change type to bool.
(_initialize_dwarf2_read): Update.

Change-Id: I6d9e2fe4b662409a540acb2c0b82c7d5314d541b

readelf -w and --debug-dump option help

* readelf (usage): Order -w letters to match --debug-dump= and
move common '=' for --debug-dump out of brackets.

nds32: __builtin_strncpy bound equals destination size

* config/tc-nds32.c (do_pseudo_push_bhwd, do_pseudo_pop_bhwd),
(do_pseudo_pusha, do_pseudo_pushi): Avoid fortify strncpy bound
error.

Automatic date update in version.in

x86: Propery check PC16 reloc overflow in 16-bit mode instructions

commit a7664973b24a242cd9ea17deb5eaf503065fc0bd
Author: Jan Beulich <jbeulich@suse.com>
Date:   Mon Apr 26 10:41:35 2021 +0200

    x86: correct overflow checking for 16-bit PC-relative relocs

caused linker failure when building 16-bit program in a 32-bit ELF
container.  Update GNU_PROPERTY_X86_FEATURE_2_USED with

#define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)

to indicate that 16-bit mode instructions are used in the input object:

https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA

to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.

1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.

bfd/

PR ld/27905
* elf32-i386.c: Include "libiberty.h".
(elf_howto_table): Add 16-bit R_386_PC16 entry.
(elf_i386_rtype_to_howto): Add a BFD argument.  Use 16-bit
R_386_PC16 if input has 16-bit mode instructions.
(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
call.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
R_X86_64_PC16 entry.
(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
has 16-bit mode instructions.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
elf_x86_has_code16 if relocatable input is marked with
GNU_PROPERTY_X86_FEATURE_2_CODE16.
* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
(elf_x86_has_code16): New.

binutils/

PR ld/27905
* readelf.c (decode_x86_feature_2): Support
GNU_PROPERTY_X86_FEATURE_2_CODE16.

gas/

PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.

include/

PR ld/27905
* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New.

ld/

PR ld/27905
* testsuite/ld-i386/code16.d: New file.
* testsuite/ld-i386/code16.t: Likewise.
* testsuite/ld-x86-64/code16.d: Likewise.
* testsuite/ld-x86-64/code16.t: Likewise.
* testsuite/ld-i386/i386.exp: Run code16.
* testsuite/ld-x86-64/x86-64.exp: Likewise.

gdb: don't zero-initialize reg_buffer contents

The reg_buffer constructor zero-initializes (value-initializes, in C++
speak) the gdb_bytes of the m_registers array.  This is not necessary,
as these bytes are only meaningful if the corresponding register_status
is REG_VALID.  If the corresponding register_status is REG_VALID, then
they will have been overwritten with the actual register data when
reading the registers from the system into the reg_buffer.

Fix that by removing the empty parenthesis following the new expression,
meaning that the bytes will now be default-initialized, meaning they'll
be left uninitialized.  For reference, this is explained here:

  https://en.cppreference.com/w/cpp/language/new#Construction

These new expressions were added in 835dcf92618e ("Use std::unique_ptr
in reg_buffer").  As mentioned in that commit message, the use of
value-initialisation was done on purpose to keep existing behavior, but
now there is some data that suggest it would be beneficial not to do it,
which is why I suggest changing it.

This doesn't make a big difference on typical architectures where the
register buffer is not that big.  However, on ROCm (AMD GPU), the
register buffer is about 65000 bytes big, so the reg_buffer constructor
shows up in profiling.  If you want to make some tests and profile it on
a standard system, it's always possible to change:

  - m_registers.reset (new gdb_byte[m_descr->sizeof_raw_registers] ());
  + m_registers.reset (new gdb_byte[65000] ());

and run a program that constantly hits a breakpoint with a false
condition.  For example, by doing this change and running the following
program:

    static void break_here () {}

    int main ()
    {
      for (int i = 0; i < 100000; i++)
        break_here ();
    }

with the following GDB incantation:

   /usr/bin/time  ./gdb -nx --data-directory=data-directory  -q test -ex "b break_here if 0" -ex r -batch

I get, for value-intializing:

    11.75user 7.68system 0:18.54elapsed 104%CPU (0avgtext+0avgdata 56644maxresident)k

And for default-initializing:

    6.83user 8.42system 0:14.12elapsed 108%CPU (0avgtext+0avgdata 56512maxresident)k

gdb/ChangeLog:

* regcache.c (reg_buffer::reg_buffer): Default-initialize
m_registers array.

Change-Id: I5071a4444dee0530ce1bc58ebe712024ddd2b158

x86-64: Add ilp32-12 to check R_X86_64_32 for x32

* testsuite/ld-x86-64/ilp32-12.d: New file.
* testsuite/ld-x86-64/ilp32-12.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run ilp32-12.

i386: Replace movsb with movsxb

PR gas/27906
* doc/c-i386.texi: Replace movsb with movsxb as an alias for
movsbq.

Introduce htab_delete_entry

In a bigger series I'm working on, it is convenient to have a
libiberty hash table that manages objects allocated with 'new'.  To
make this simpler, I wrote a small template function to serve as a
concise wrapper.  Then I realized that this could be reused in a few
other places.

gdb/ChangeLog
2021-05-26  Tom Tromey  <tom@tromey.com>

* dwarf2/read.c (allocate_type_unit_groups_table)
(handle_DW_AT_stmt_list, allocate_dwo_file_hash_table): Use
htab_delete_entry.
(free_line_header_voidp): Remove.
* completer.c
(completion_tracker::completion_hash_entry::deleter): Remove.
(completion_tracker::discard_completions): Use htab_delete_entry.
* utils.h (htab_delete_entry): New template function.

RISC-V: Allow to link the objects with unknown prefixed extensions.

Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, ....  The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.

The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.

bfd/
    * elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
    prefixed extension name if check_unknown_prefixed_ext is false.
    * elfnn-riscv.c (riscv_merge_arch_attr_info): Set
    check_unknown_prefixed_ext to false for linker.
gas/
    * config/tc-riscv.c (riscv_set_arch): Set
    check_unknown_prefixed_ext to true for assembler.

Automatic date update in version.in

Fix documentation of gdb.SYMBOL_LOC_COMMON_BLOCK

gdb/doc/ChangeLog:

2021-05-25 Hannes Domani <ssbssa@yahoo.de>

* python.texi (Symbols In Python): Fix gdb.SYMBOL_LOC_COMMON_BLOCK.

Arm: Fix forward thumb references [PR gas/25235]

When assembling a forward reference the symbol will be unknown and so during
do_t_adr we cannot set the thumb bit. The bit it set so early to prevent
relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the
symbol is Thumb.

But because it's done so early we miss the case for forward references.
This patch changes it so that we additionally check the thumb bit during the
internal relocation processing.

In principle we should be able to only set the bit during reloc processing but
that would require changes to the other relocations that the instruction could
be relaxed to.

This approach still allows early relaxations (which means that we have less
iteration of internal reloc processing) while still fixing the forward reference
case.

gas/ChangeLog:

2021-05-24 Tamar Christina <tamar.christina@arm.com>

PR gas/25235
* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
(relax_adr): Thumb symbols 4 bytes.
* testsuite/gas/arm/pr25235.d: New test.
* testsuite/gas/arm/pr25235.s: New test.

Add range checks to local array accesses in elf32-arm.c.

bfd * elf32-arn.c (struct elf_arm_obj_tdata): Add num_entries field.
(elf32_arm_num_entries): New macro.
(elf32_arm_allocate_local_sym_info): Initialise the new field.
Allocate arrays individually so that buffer overruns can be
detected by memory checkers.
(elf32_arm_create_local_iplt): Check num_entries.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_final_link_relocate): Likewise.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_size_dynamic_sections): Likewise.
(elf32_arm_output_arch_local_syms): Likewise.

Fix formatting in elf32-arm.c

Regen cris files

* cris-desc.c: Regenerate.
* cris-desc.h: Regenerate.
* cris-opc.h: Regenerate.
* po/POTFILES.in: Regenerate.

[GOLD] PR27815, gold fails to build with latest GCC

Don't use nullptr, it requires -std=c++11 on versions of gcc prior to
6.1. It would be possible to arrange to pass -std=c++11 automatically
when required (top level configure does that for gcc builds) but that
seems overkill and since we're not up-to-date on the top level config
files would mean someone would need to sync those over.

PR gold/27815
* gc.h (gc_process_relocs): Use cast in Section_id constructor.

asan: _bfd_elf_parse_attributes heap buffer overflow

I exposed a problem with the change in commit 574ec1084d to the outer
loop of _bfd_elf_parse_attributes.  "p_end - p >= 4" is better than
"p < p_end - 4" as far as pointer UB is concerned if the size of the
attritbute section is say, 3 bytes.  However you do need to ensure p
never exceeds p_end, and that length remaining is kept consistent with
the pointer.

* elf-attrs.c (elf_attr_strdup): New function.
(_bfd_elf_attr_strdup): Use it here.
(elf_add_obj_attr_string): New function, extracted from..
(bfd_elf_add_obj_attr_string): ..here.
(elf_add_obj_attr_int_string): New function, extracted from..
(bfd_elf_add_obj_attr_int_string): ..here.
(_bfd_elf_parse_attributes): Don't allocate an extra byte for a
string terminator.  Instead ensure parsing doesn't go past
end of sub-section.  Use size_t variables for lengths.

Automatic date update in version.in

opcodes: cris: move desc & opc files from sim/

All other cgen ports keep their generated desc & opc files under
opcodes/, so move the cris files over too. The cris-opc.c file,
while not generated, is already here to complement.

gnulib: import ffs

The Blackfin sim uses this function, but Windows/mingw doesn't provide it.

MAINTAINERS: Update path to readline config.{sub,guess} files

Complement commit 6999161a2a3b ("Move readline to the readline/readline
subdirectory") and update the path to readline config.{sub,guess} files
documented in MAINTAINERS.

* MAINTAINERS: Update path to readline config.{sub,guess} files.

Update config.sub and config.guess for MIPS R3 and R5 ISA support

Complement commit ae52f4830604 ("Add MIPS r3 and r5 support.") and get
changes for config.sub to recognize MIPS CPU patterns for the R3 and R5
ISA levels, used by GAS to set defaults in gas/configure.ac. Oddly, R6
ISA support has been correctly added already.

/
* config.guess: Import from upstream.
* config.sub: Likewise.

readline/
* readline/support/config.guess: Import from upstream.
* readline/support/config.sub: Likewise.

Prevent flickering when redrawing the TUI python window

tui_win_info::refresh_window first redraws the background window, then
tui_wrefresh draws the python text on top of it, which flickers.

By using wnoutrefresh for the background window, the actual drawing on
the screen is only done once, without flickering.

gdb/ChangeLog:

2021-05-24 Hannes Domani <ssbssa@yahoo.de>

* python/py-tui.c (tui_py_window::refresh_window):
Avoid flickering.

gdb/doc: add '@:' after 'e.g.' to help texinfo

Add '@:' after 'e.g.' to let texinfo know that this is not the end of
a sentence. This is only needed when there's a space immediately
after the last '.'.

gdb/doc/ChangeLog:

* gdb.texi (Initialization Files): Add '@:' after 'e.g.'.
(Source Path): Likewise.
(GDB/MI Development and Front Ends): Likewise.
(ARM Features): Likewise.
(gdb man): Likewise.

RISC-V: PR25212, Report errors for invalid march and mabi combinations.

This patch clarify the following invalid combinations of march and mabi,
* ilp32f/lp64f abi without f extension.
* ilp32d/lp64d abi without d extension.
* ilp32q/lp64q abi without q extension.
* e extension with any abi except ilp32e

GNU assembler reports errors when finding the above invalid combinations.
But LLVM-MC reports warnings and ignores these invalid cases.  It help to
set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve.  This
looks good and convenient, so perhaps we can do the same things.  However,
if you don't set the mabi, GNU assembler also try to set the suitable
ABI according to march/elf-attribute.  Compared to LLVM-MC, we will choose
double/quad abi if d/f extension is set.

gas/
    PR 25212
    * config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
    will choose ilp32e abi for rv32e.  Besides, report errors for the
    invalid march and mabi combinations.
    * testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase.  Only accept
    ilp32e abi for rve extension.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    Renamed all mabi testcases to their march-mabi settings.

sim: cris: fix memory setup typos

The cleanup to use BFD_VMA_FMT also adjusted this line, but used the
incorrect format: while BFD_VMA_FMT needs an explicit "x", PRIx32 does
not, so the spurious "x" here confused the parser and broke execution.

sim: bfin: fix the otp fix

I misread the code and thought data0/... were bu64 when they were
actually bu32. Fix the call to assemble the 2 64-bit values instead
of passing the 2 halves of the first 64-bit value.

sim: bfin: fix build warnings w/newer gcc

The bfin_otp_write_page_val func wants a pointer to an bu64[2] array,
but this code passes it a pointer to a single bu64. It's in a struct
with a known compatible layout:
bu64 data0, data1, data2, data3;
But gcc doesn't allow these kinds of tricks anymore. Use the more
verbose form to make the compiler happy since this is not performance
sensitive code.

Automatic date update in version.in

sim: rl78: rename open symbol to avoid collisions

If the header files define open(), make sure our local open var
doesn't shadow it.

sim: cris: add unistd.h for environ decl

We include environ.h for the fallback, but we still need to include
unistd.h in case it provides it as gnulib will detect.

sim: bfin: add strings.h for ffs()

[gdb/tdep] Use pid to choose process 64/32-bitness

In a linux kernel mailing list discussion, it was mentioned that "gdb has
this odd thing where it takes the 64-bit vs 32-bit data for the whole process
from one thread, and picks the worst possible thread to do it (ie explicitly
not even the main thread, ...)" [1].

The picking of the thread is done here in
x86_linux_nat_target::read_description:
...
  /* GNU/Linux LWP ID's are process ID's.  */
  tid = inferior_ptid.lwp ();
  if (tid == 0)
    tid = inferior_ptid.pid (); /* Not a threaded program.  */
...

To understand what this code does, let's investigate a scenario in which
inferior_ptid.lwp () != inferior_ptid.pid ().

Say we start exec jit-attach-pie, identified with pid x.  The main thread
starts another thread that sleeps, and then the main thread waits for the
sleeping thread.  So we have two threads, identified with LWP IDs x and x+1:
...
PID  LWP  CMD
x    x    ./jit-attach-pie
x    x+1  ./jit-attach-pie
...
[ The thread with LWP x is known as the thread group leader. ]

When attaching to this exec using the pid, gdb does a stop_all_threads which
iterates over all the threads, first LWP x, and then LWP x+1.

So the state we arrive with at x86_linux_nat_target::read_description is:
...
(gdb) p inferior_ptid
$1 = {m_pid = x, m_lwp = x+1, m_tid = 0}
...
and consequently we probe 64/32-bitness from thread LWP x+1.

[ Note that this is different from when gdb doesn't attach but instead
launches the exec itself, in which case there's just one thread to begin with,
and consequently the probed thread is LWP x. ]

According to aforementioned remark, a better choice would have been the main
thread, that is, LWP x.

This patch implement that choice, by simply doing:
...
  tid = inferior_ptid.pid ();
...

The fact that gdb makes a per-process permanent choice for 64/32-bitness is a
problem in itself: each thread can be in either 64 or 32 bit mode, and change
forth and back.  That is a problem that this patch doesn't fix.

Now finally: why does this matter in the context of the linux kernel
discussion?  The discussion was related to a patch that exposed io_uring
threads to user-space.  This made it possible that one of those threads would
be picked out to select 64/32-bitness.  Given that such threads are atypical
user-space threads in the sense that they don't return to user-space and don't
have a userspace register state, reading their registers returns garbage, and
so it could f.i. occur that in a 64-bit process with all normal user-space
threads in 64-bit mode, the probing would return 32-bit.

It may be that this is worked-around on the kernel side by providing userspace
register state in those threads such that current gdb is happy.  Nevertheless,
it seems prudent to fix this on the gdb size as well.

Tested on x86_64-linux.

[1] https://lore.kernel.org/io-uring/CAHk-=wh0KoEZXPYMGkfkeVEerSCEF1AiCZSvz9TRrx=Kj74D+Q@mail.gmail.com/

gdb/ChangeLog:

2021-05-23  Tom de Vries  <tdevries@suse.de>

PR tdep/27822
* target.h (struct target_ops): Mention target_thread_architecture in
read_description comment.
* x86-linux-nat.c (x86_linux_nat_target::read_description): Use
pid to determine if process is 64-bit or 32-bit.
* aarch64-linux-nat.c (aarch64_linux_nat_target::read_description):
Same.
* ppc-linux-nat.c (ppc_linux_nat_target::read_description): Same.
        * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Same.
* s390-linux-nat.c (s390_linux_nat_target::read_description): Same.
* arm-linux-nat.c (arm_linux_nat_target::read_description): Same.
Likewise, use pid to determine if kernel supports reading VFP
registers.

elf: Use official name LoongArch for EM_LOONGARCH.

The official name for Loongson Architecture is LoongArch, it is better
to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid
confusion and keep consistent with the various of software in the future.

The official documentation in Chinese:
http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf

The translated version in English:
https://loongson.github.io/LoongArch-Documentation/

    binutils/
        * readelf.c (get_machine_name): Change Loongson Loongarch to
LoongArch.

    include/
        * elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to
LoongArch.

Automatic date update in version.in

Fix option type comments for CMDARG_EARLYINIT_FILE and CMDARG_EARLYINIT_COMMAND.

The comments in the enum cmdarg_kind were using -sx and -sex instead
of -eix and -eiex.

(Note that gdb --help does not speak about these options).

(pushed as obvious)

Re: Fix offset for ia64 PCREL60B relocation on HP-UX

PR 25599
* config/tc-ia64.c (emit_one_bundle): Expand comment for HP-UX
adjustment. Add assertion.
* testsuite/gas/ia64/reloc-mlx.d: Pass when slot 2 specified
for PCREL60B.

bfd dwarf2 sanity checking

This patch is aimed at the many places in dwarf2.c that blindly
increment a data pointer after calling functions that are meant to
read a fixed number of bytes.  The problem with that is with damaged
dwarf we might increment a data pointer past the end of data, which is
UB and complicates (ie. bugs likely) any further use of that data
pointer.  To fix those problems, I've moved incrementing of the data
pointer into the functions that do the reads.  _bfd_safe_read_leb128
gets the same treatment for consistency.

* libbfd.c (_bfd_safe_read_leb128): Remove length_return parameter.
Replace data pointer with pointer to pointer.  Increment pointer
over bytes read.
* libbfd-in.h (_bfd_safe_read_leb128): Update prototype.
* elf-attrs.c (_bfd_elf_parse_attributes): Adjust to suit.  Be
careful not to increment data pointer past end.  Remove now
redundant pr17512 check.
* wasm-module.c (READ_LEB128): Adjust to suit changes to
_bfd_safe_read_leb128.
* dwarf2.c (read_n_bytes): New inline function, old one renamed to..
(read_blk): ..this.  Allocate and return block.  Increment bfd_byte**
arg.
(read_3_bytes): New function.
(read_1_byte, read_1_signed_byte, read_2_bytes, read_4_bytes),
(read_8_bytes, read_string, read_indirect_string),
(read_indirect_line_string, read_alt_indirect_string): Take a
byte_byte** arg which is incremented over bytes read.  Remove any
bytes_read return.  Rewrite limit checks to compare lengths
rather than pointers.
(read_abbrevs, read_attribute_value, read_formatted_entries),
(decode_line_info, find_abstract_instance, read_ranges),
(read_rnglists, scan_unit_for_symbols, parse_comp_unit),
(stash_comp_unit): Adjust to suit.  Rewrite limit checks to
compare lengths rather than pointers.
* libbfd.h: Regenerate.

[GOLD] PR27815, gold fails to build with latest GCC

...gold/gc.h:250:37: error: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second: [-Werror]
250 | (*secvec).push_back(Section_id(NULL, 0));
| ^~~~~~~~~~~~~~~~~~~

PR gold/27815
* gc.h (gc_process_relocs): Use nullptr in Section_id constructor.

sim: mips: Add shadow mappings for 32-bit memory address space

32-bit MIPS programs run on the 64-bit simulator model in 64-bit
sign-extended space. The mapping from 64-bit sign-extended addresses to
32-bit addresses was removed by commit
26f8bf63bf36f9062a5cc1afacf71462a4abe0c8, breaking the 64-bit simulator
model. Add shadow mappings from 64-bit sign extended address space to
32-bit address spaces, in lieu of the AddressTranslation function.

2021-05-04 Faraz Shahbazker <fshahbazker@wavecomp.com>

sim/mips/ChangeLog:
* interp.c (sim_open): Add shadow mappings from 32-bit
address space to 64-bit sign-extended address space.

sim: mips: Only truncate sign extension bits for 32-bit target models

64-bit BFD for MIPS applies a standard sign extension on all addresses
assuming 64-bit target.  These bits are required for 64-bit and can only
be safely truncated for 32-bit target models. This partially reverts commit
b36d953bced0a4fecdde1823abac70ed7038ee95

The sign-extension logic modeled by BFD is an integral part of the
MIPS64 architecture spec. It appears in the virtual address map, where
sign extension allows for 32-bit compatibility segments [1] with 64-bit
addressing. Truncating these addresses prematurely (commit
models (-DWITH_TARGET_WORD_BITSIZE=64).

In the ISA itself, direct addressing (Load-Upper-Immediate) and indirect
addressing (Load-Word) both automatically sign-extend their results. These
instructions regenerate the sign-extended addresses even if we don't start
with one (see pr gdb/19447).

Moreover, some instructions like ADD*/SUB* have unpredictable behaviour when
an operand is not correctly sign extended [3]. This affects PC-relative
addressing in particular, so arithmetic on the link-address generated in the
return address register by a jump-and-link is no longer possible, neither is
the use of the PC-relative addressing instructions provided by MIPSR6.

[1] "MIPS64 Architecture for Programmers Volume III: The MIPS64
    Privileged Resource Architecture", Document Number: MD00091,
    Revision 6.02, December 10, 2015, Section 4.3 "Virtual Address
    Spaces", pp. 29-31
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00091-2B-MIPS64PRA-AFP-06.03.pdf

[2] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Reference Manual", Document Number: MD00087,
    Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
    List of Instructions", pp. 321
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf

[3] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Reference Manual", Document Number: MD00087,
    Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
    List of Instructions", pp. 56
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf

2021-04-23  Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/mips/ChangeLog:
* interp.c (sim_create_inferior): Only truncate sign extension
bits for 32-bit target models
.

sim/d10v: Use offsetof in a static assertion about structure layout.

clang 11 fails to compile the static assertion as it cannot compute
the pointer value at a compile time:

gdb/sim/d10v/interp.c:1149:37: error: static_assert expression is not an integral constant expression
static_assert ((uintptr_t) &State == (uintptr_t) &State.regs,
~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Instead, assert that the offset of State.regs is 0.

sim/d10v/ChangeLog:

* interp.c (sim_create_inferior): Use offsetof in static
assertion.

Automatic date update in version.in

[gdb/testsuite] Add target board cc-with-gnu-debuglink.exp

Add target board cc-with-gnu-debuglink.exp that splits off debuginfo into a
seperate .debug file and links to it using .gnu_debuglink.

Tested on x86_64-linux.

gdb/ChangeLog:

2021-05-21 Tom de Vries <tdevries@suse.de>

PR testsuite/25047
* contrib/cc-with-tweaks.sh: Handle -l.

gdb/testsuite/ChangeLog:

2021-05-21 Tom de Vries <tdevries@suse.de>

PR testsuite/25047
* boards/cc-with-gnu-debuglink.exp: New file.

testsuite/gdb.dwarf2: avoid dead code in dw2-inline-with-lexical-scope.c

The test in gdb.dwarf2/dw2-inline-with-lexical-scope.c fails with icc.
The reason is, icc did not emit code for a dead statement, which in
turn caused some labels to be collapsed.  Fix this by replacing the
dead code with assignment to a global value.  The statement itself
does not change the test scenario.

Also fix a whitespacing problem around an assignment operator.

gdb/testsuite/ChangeLog:
2021-05-21  Tankut Baris Aktemur  <tankut.baris.aktemur@intel.com>

* gdb.dwarf2/dw2-inline-with-lexical-scope.c (func): Replace
a dead code with an assignment to a global var.  Fix a
whitespacing problem around an assignment operator.

[gdb/breakpoint] Fix assert in jit_event_handler

Consider a minimal test-case test.c:
...
int main (void) { return 0; }
...
which we can compile into llvm byte code using clang:
...
$ clang -g -S -emit-llvm --target=x86_64-unknown-unknown-elf test.c
...
and then run using lli, which uses the llvm jit:
...
$ lli test.ll
...

If we run this under gdb, we run into an assert:
...
$ gdb -q -batch -ex run --args /usr/bin/lli test.ll
Dwarf Error: Cannot not find DIE at 0x18a936e7 \
  [from module libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug]

[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib64/libthread_db.so.1".
src/gdb/jit.c:1178: internal-error: \
  void jit_event_handler(gdbarch*, objfile*): \
  Assertion `jiter->jiter_data != nullptr' failed.
...

This is caused by the following.

When running jit_breakpoint_re_set_internal, we first handle
libLLVM.so.10.debug, and set a jit breakpoint.

Next we handle libLLVM.so.10:
...
(gdb) p the_objfile.original_name
$42 = 0x2494170 "libLLVM.so.10"
...
but the minimal symbols we find are from libLLVM.so.10.debug:
...
(gdb) p reg_symbol.objfile.original_name
$43 = 0x38e7c50 "libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug"
(gdb) p desc_symbol.objfile.original_name
$44 = 0x38e7c50 "libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug"
...
and consequently, the objf_data is the one from libLLVM.so.10.debug:
...
      jiter_objfile_data *objf_data
        = get_jiter_objfile_data (reg_symbol.objfile);
...
and so we hit this:
...
      if (objf_data->cached_code_address == addr)
        continue;
...
and no second jit breakpoint is inserted.

Subsequently, the jit breakpoint is triggered and handled, but when finding
the symbol for the breakpoint address we get:
...
(gdb) p jit_bp_sym.objfile.original_name
$52 = 0x2494170 "libLLVM.so.10"
...

The assert 'jiter->jiter_data != nullptr' triggers because it checks
libLLVM.so.10 while the one with jiter_data setup is libLLVM.so.10.debug.

This fixes the assert:
...
       jiter_objfile_data *objf_data
-        = get_jiter_objfile_data (reg_symbol.objfile);
-        = get_jiter_objfile_data (the_objfile);
...
but consequently we'll have two jit breakpoints, so we also make sure we don't
set a jit breakpoint on separate debug objects like libLLVM.so.10.debug.

Tested on x86_64-linux.

gdb/ChangeLog:

2021-05-21  Tom de Vries  <tdevries@suse.de>

PR breakpoint/27889
* jit.c (jit_breakpoint_re_set_internal): Skip separate debug
objects.  Call get_jiter_objfile_data with the_objfile.