lkcl [Mon, 16 Nov 2020 00:38:40 +0000 (00:38 +0000)]
lkcl [Mon, 16 Nov 2020 00:21:39 +0000 (00:21 +0000)]
lkcl [Mon, 16 Nov 2020 00:18:33 +0000 (00:18 +0000)]
lkcl [Sun, 15 Nov 2020 21:20:55 +0000 (21:20 +0000)]
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 19:52:03 +0000 (19:52 +0000)]
swap major opcodes around
lkcl [Sun, 15 Nov 2020 17:59:05 +0000 (17:59 +0000)]
lkcl [Sun, 15 Nov 2020 16:27:45 +0000 (16:27 +0000)]
lkcl [Sun, 15 Nov 2020 16:25:48 +0000 (16:25 +0000)]
lkcl [Sun, 15 Nov 2020 16:22:38 +0000 (16:22 +0000)]
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 16:14:12 +0000 (16:14 +0000)]
add headings for modes
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 16:08:47 +0000 (16:08 +0000)]
mention mode-switching idea (to 32-bit for 1 cycle)
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 15:38:53 +0000 (15:38 +0000)]
add C-Bank switching instruction
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 12:05:57 +0000 (12:05 +0000)]
try an addi
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 03:12:30 +0000 (03:12 +0000)]
mention idea TODO of going into 32-bit mode for 1 instruction
https://bugs.libre-soc.org/show_bug.cgi?id=238#c2
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 03:10:44 +0000 (03:10 +0000)]
clarify 16-bit encoding
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 03:04:20 +0000 (03:04 +0000)]
add fmr. minor shuffle
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 02:39:58 +0000 (02:39 +0000)]
add fmr. in 16-bit mode
Luke Kenneth Casson Leighton [Sun, 15 Nov 2020 02:25:12 +0000 (02:25 +0000)]
add system, spr and unallocated C16
lkcl [Sun, 15 Nov 2020 01:50:28 +0000 (01:50 +0000)]
lkcl [Sun, 15 Nov 2020 01:16:35 +0000 (01:16 +0000)]
lkcl [Sun, 15 Nov 2020 01:11:59 +0000 (01:11 +0000)]
lkcl [Sat, 14 Nov 2020 23:15:00 +0000 (23:15 +0000)]
lkcl [Sat, 14 Nov 2020 23:14:19 +0000 (23:14 +0000)]
lkcl [Sat, 14 Nov 2020 23:13:19 +0000 (23:13 +0000)]
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 22:46:26 +0000 (22:46 +0000)]
add CR operations
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 22:26:37 +0000 (22:26 +0000)]
move 16 bit compressed to separate page
lkcl [Sat, 14 Nov 2020 21:49:35 +0000 (21:49 +0000)]
lkcl [Sat, 14 Nov 2020 21:28:00 +0000 (21:28 +0000)]
lkcl [Sat, 14 Nov 2020 21:17:37 +0000 (21:17 +0000)]
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 19:09:02 +0000 (19:09 +0000)]
whitespace and update C tables
Luke Kenneth Casson Leighton [Thu, 12 Nov 2020 14:40:06 +0000 (14:40 +0000)]
add OFSC 2020 talk
lkcl [Sat, 14 Nov 2020 18:28:28 +0000 (18:28 +0000)]
lkcl [Sat, 14 Nov 2020 17:57:18 +0000 (17:57 +0000)]
lkcl [Sat, 14 Nov 2020 03:04:54 +0000 (03:04 +0000)]
lkcl [Sat, 14 Nov 2020 02:22:59 +0000 (02:22 +0000)]
lkcl [Fri, 13 Nov 2020 22:03:23 +0000 (22:03 +0000)]
Cesar_Strauss [Fri, 13 Nov 2020 10:24:23 +0000 (10:24 +0000)]
Add Tomasulo model example
lkcl [Fri, 13 Nov 2020 02:19:25 +0000 (02:19 +0000)]
lkcl [Fri, 13 Nov 2020 02:07:06 +0000 (02:07 +0000)]
lkcl [Fri, 13 Nov 2020 02:06:00 +0000 (02:06 +0000)]
lkcl [Fri, 13 Nov 2020 00:11:48 +0000 (00:11 +0000)]
lkcl [Wed, 11 Nov 2020 22:24:46 +0000 (22:24 +0000)]
lkcl [Wed, 11 Nov 2020 21:51:46 +0000 (21:51 +0000)]
lkcl [Wed, 11 Nov 2020 21:27:32 +0000 (21:27 +0000)]
Tobias Platen [Wed, 11 Nov 2020 18:48:15 +0000 (19:48 +0100)]
add dcbz and tlbio instruction needed by mmu
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:21:51 +0000 (16:21 +0000)]
add minerva nmigen-soc example
lkcl [Mon, 9 Nov 2020 11:02:59 +0000 (11:02 +0000)]
lkcl [Mon, 9 Nov 2020 10:59:14 +0000 (10:59 +0000)]
lkcl [Mon, 9 Nov 2020 10:48:36 +0000 (10:48 +0000)]
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 19:32:12 +0000 (19:32 +0000)]
add EOMA68+LibreSOC gadie section
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 18:44:58 +0000 (18:44 +0000)]
add EOMA68+LibreSOC gadie section
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:56:49 +0000 (17:56 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:49:33 +0000 (17:49 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:49:22 +0000 (17:49 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:32:15 +0000 (17:32 +0000)]
add gaddie pitch section for LibreSOC
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 14:36:54 +0000 (14:36 +0000)]
update nlnet FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:57:13 +0000 (11:57 +0000)]
update FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:50:11 +0000 (11:50 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:49:50 +0000 (11:49 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:49:06 +0000 (11:49 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 18:55:29 +0000 (18:55 +0000)]
add to nlnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:54:55 +0000 (15:54 +0000)]
add to NLnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:49:33 +0000 (15:49 +0000)]
add to NLnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:29:11 +0000 (15:29 +0000)]
show tab on imag
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:26:35 +0000 (15:26 +0000)]
update FPGA connector images
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:26:26 +0000 (15:26 +0000)]
add circuit refs
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:22:53 +0000 (15:22 +0000)]
change to use 3.3v on VERSA X3
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:21:23 +0000 (15:21 +0000)]
add NLnet FAQ
Cole Poirier [Wed, 4 Nov 2020 01:37:45 +0000 (17:37 -0800)]
HDL_wokflow update ulx3s jtag jumper wire connection images to be
smaller
Cole Poirier [Wed, 4 Nov 2020 01:09:32 +0000 (17:09 -0800)]
HDL_workflow/ECP5_FPGA provide two images showing different orientation
of stlinkv2
Cole Poirier [Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)]
update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:31:45 +0000 (14:31 +0000)]
colour-mark X3 VERSA ECP5 JTAG pins
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:26:35 +0000 (14:26 +0000)]
update jtag table, add colour to images
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:11:28 +0000 (14:11 +0000)]
add stlinkv2 photos
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:10:33 +0000 (14:10 +0000)]
add stlinkv2 connector images
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:53:28 +0000 (13:53 +0000)]
swap wires around to match ulx3s
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:50:32 +0000 (13:50 +0000)]
format table
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:47:29 +0000 (13:47 +0000)]
add ECP5 JTAG connections
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:35:24 +0000 (13:35 +0000)]
add image links to ECP5 page
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:33:28 +0000 (13:33 +0000)]
add versa ecp5 x3 photo
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:29:07 +0000 (13:29 +0000)]
add VERSA-ECP5 images, rename FPGA page
Cole Poirier [Sun, 1 Nov 2020 22:17:06 +0000 (14:17 -0800)]
add images to wiki for ulx3s jtag stlinkv2 wires
add page use ulx3s fpga gpio pins for Libre-SOC JTAG connections to STLINKV2
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:23:35 +0000 (12:23 +0000)]
add cross-ref links
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:15:20 +0000 (12:15 +0000)]
adjust image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:11:29 +0000 (12:11 +0000)]
add description of table
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:48:15 +0000 (11:48 +0000)]
change image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:47:33 +0000 (11:47 +0000)]
add image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:47:04 +0000 (11:47 +0000)]
add start of isa-to-virtual regs
projects / libreriscv.git / log