Alain Péteut [Tue, 2 Jul 2019 08:44:12 +0000 (10:44 +0200)]
build.plat: add iter_extra_files method.
* vendor.*: employ iter_extra_files.
whitequark [Tue, 2 Jul 2019 18:06:50 +0000 (18:06 +0000)]
back.rtlil: emit \sig$next wires instead of \$next\sig. NFC.
Just a bit more readable.
whitequark [Tue, 2 Jul 2019 18:05:34 +0000 (18:05 +0000)]
back.rtlil: do not emit $next wires for comb signals.
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.
This change results in major improvements in Verilog readability.
See also #98.
whitequark [Tue, 2 Jul 2019 17:44:55 +0000 (17:44 +0000)]
hdl.rec: implement slicing by component names.
Fixes #121.
whitequark [Tue, 2 Jul 2019 17:35:00 +0000 (17:35 +0000)]
hdl.rec: implement Record.like.
Fixes #120.
Alain Péteut [Tue, 2 Jul 2019 07:47:40 +0000 (09:47 +0200)]
vendor.xilinx_7series: read extra .xdc files.
whitequark [Mon, 1 Jul 2019 19:56:49 +0000 (19:56 +0000)]
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).
Fixes #116.
whitequark [Mon, 1 Jul 2019 01:53:56 +0000 (01:53 +0000)]
back.rtlil: fix Array regression in
32446831.
Fixes #117.
whitequark [Fri, 28 Jun 2019 08:34:02 +0000 (08:34 +0000)]
back.pysim: create unique ResetSynchronizer internal domains.
Commit
300d47ca introduced the same bug commit
779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.
whitequark [Fri, 28 Jun 2019 07:49:14 +0000 (07:49 +0000)]
back.pysim: override ResetSynchronizer implementation.
This was rewritten to use Yosys cells in
779f3ee9 to avoid leaking
the interior clock domain, but the simulator doesn't understand Yosys
cells. So, use the old implementation in the simulator.
whitequark [Fri, 28 Jun 2019 07:34:10 +0000 (07:34 +0000)]
lib.cdc: avoid interior clock domains in ResetSynchronizer.
Such clock domains will "leak" into the enclosing scope, which is
generally undesirable. Also, this is instructive for a platform
overriding the behavior, since it provides guidance on how to
correctly instantiate platform-specific flops.
I've considered also doing this for MultiReg(), but it is very
challenging in presence of non-reset-less CDC FFs, since Yosys'
$dffsr primitive has separate set and clear inputs, and reshuffling
the reset value for those results in quite a bit of additional logic.
(That said, it might have to be done anyway, precisely because
letting Yosys generate this additional logic might prove too much
for the toolchain to cope with, and again, platform-independent
code should provide guidance to platform-specific code.)
whitequark [Fri, 28 Jun 2019 07:22:54 +0000 (07:22 +0000)]
lib.cdc: eliminate no_retiming attributes.
See #115 for rationale.
whitequark [Fri, 28 Jun 2019 07:05:10 +0000 (07:05 +0000)]
vendor.lattice_ice40: fix instance of negedge FF due to a typo.
Alain Péteut [Thu, 27 Jun 2019 18:56:37 +0000 (20:56 +0200)]
build.plat: fix dedent overrides.
whitequark [Fri, 28 Jun 2019 05:10:29 +0000 (05:10 +0000)]
README: tone down the instability warning to reflect current status.
whitequark [Fri, 28 Jun 2019 04:37:08 +0000 (04:37 +0000)]
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
This means that instead of:
with m.Case(0b00):
<body>
with m.Case(0b01):
<body>
it is legal to write:
with m.Case(0b00, 0b01):
<body>
with no change in semantics, and slightly nicer RTLIL or Verilog
output.
Fixes #103.
whitequark [Fri, 28 Jun 2019 04:14:38 +0000 (04:14 +0000)]
hdl.ir, back.rtlil: allow specifying attributes on instances.
Fixes #107.
whitequark [Thu, 27 Jun 2019 04:51:45 +0000 (04:51 +0000)]
examples: add concise UART example.
This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.
whitequark [Wed, 26 Jun 2019 05:22:09 +0000 (05:22 +0000)]
back.pysim: fix scope screwup.
whitequark [Tue, 25 Jun 2019 21:53:08 +0000 (21:53 +0000)]
compat.fhdl.structure: fix typo.
whitequark [Tue, 25 Jun 2019 21:52:03 +0000 (21:52 +0000)]
compat.fhdl.structure: simplify handling of default case.
whitequark [Tue, 25 Jun 2019 17:53:09 +0000 (17:53 +0000)]
hdl.{ast,dst}: directly represent RTLIL default case.
This makes RTLIL mildly nicer:
casez ({ \$5 , \$3 , \$1 })
3'bzz1:
\$next\o = \$7 ;
3'bz1z:
\$next\o = \$9 ;
3'b1zz:
\$next\o = \$11 ;
- 3'bz:
+ default:
{ \$next\co , \$next\o } = \$13 ;
endcase
whitequark [Tue, 25 Jun 2019 15:51:52 +0000 (15:51 +0000)]
vendor.xilinx_{spartan6,7series}: speedgrade→speed.
For consistency with ECP5.
whitequark [Tue, 25 Jun 2019 15:47:53 +0000 (15:47 +0000)]
vendor.lattice_ecp5: implement.
Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:05:25 +0000 (10:05 +0800)]
README: update nMigen libs paragraph
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:00:31 +0000 (10:00 +0800)]
README: add clarification about HLS
whitequark [Wed, 19 Jun 2019 06:09:08 +0000 (06:09 +0000)]
vendor.lattice_ice40: use different --package for 4k devices.
Jean-François Nguyen [Mon, 17 Jun 2019 18:01:26 +0000 (20:01 +0200)]
vendor.xilinx_7series: fix IOB packing.
whitequark [Sat, 15 Jun 2019 16:07:40 +0000 (16:07 +0000)]
vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
whitequark [Sat, 15 Jun 2019 16:01:37 +0000 (16:01 +0000)]
vendor.xilinx_{7series,spartan6}: cleanup. NFC.
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
whitequark [Sat, 15 Jun 2019 15:55:10 +0000 (15:55 +0000)]
vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
Alain Péteut [Sun, 16 Jun 2019 12:06:39 +0000 (14:06 +0200)]
build.plat: dedent overrides.
whitequark [Fri, 14 Jun 2019 20:44:02 +0000 (20:44 +0000)]
vendor.lattice_ice40: never place an inverter on global buffer output.
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
Jean-François Nguyen [Thu, 13 Jun 2019 12:33:24 +0000 (14:33 +0200)]
vendor.xilinx_7series: implement inverters.
Jean-François Nguyen [Wed, 12 Jun 2019 14:56:05 +0000 (16:56 +0200)]
vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.
whitequark [Thu, 13 Jun 2019 03:54:46 +0000 (03:54 +0000)]
compat.fhdl.structure: fix Case().makedefault().
Fixes #100.
whitequark [Thu, 13 Jun 2019 03:52:04 +0000 (03:52 +0000)]
compat.fhdl.structure: always order default case as the very last.
whitequark [Thu, 13 Jun 2019 03:56:49 +0000 (03:56 +0000)]
hdl.ast: tighten assertion in Switch().
whitequark [Wed, 12 Jun 2019 22:28:45 +0000 (22:28 +0000)]
Simplify code by using Signal.like(name_suffix="..") appropriately.
whitequark [Wed, 12 Jun 2019 22:21:23 +0000 (22:21 +0000)]
hdl.ast: add name_suffix=".." option to Signal.like().
This simplifies creation of related signals with nice names during
metaprogramming, e.g.
def make_ff(m, sig):
sig_ff = Signal.like(sig, name_suffix="_ff")
m.d.sync += sig_ff.eq(sig)
return sig_ff
Jean-François Nguyen [Tue, 11 Jun 2019 17:57:55 +0000 (19:57 +0200)]
vendor.xilinx_7series: implement DDR I/O buffers.
whitequark [Wed, 12 Jun 2019 17:38:14 +0000 (17:38 +0000)]
vendor.lattice_ice40: fix typo.
whitequark [Wed, 12 Jun 2019 14:42:39 +0000 (14:42 +0000)]
build.{dsl,res,plat}: add PinsN and DiffPairsN.
whitequark [Tue, 11 Jun 2019 07:01:44 +0000 (07:01 +0000)]
hdl.ast: implement values with custom lowering.
whitequark [Tue, 11 Jun 2019 03:54:22 +0000 (03:54 +0000)]
back.pysim: check for a clock being added twice.
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.
Fixes #27.
whitequark [Tue, 11 Jun 2019 03:43:09 +0000 (03:43 +0000)]
back.rtlil: mask memory init values.
This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.
Fixes #96.
whitequark [Tue, 11 Jun 2019 03:38:44 +0000 (03:38 +0000)]
hdl.mem: coerce memory init values to integers.
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/
48940855/254415 for details.
Fixes #93.
Simon Kirkby [Sun, 9 Jun 2019 10:24:01 +0000 (18:24 +0800)]
lib.cdc: fix typo.
Jean-François Nguyen [Thu, 6 Jun 2019 22:48:51 +0000 (00:48 +0200)]
vendor.xilinx_spartan6: implement.
Jean-François Nguyen [Thu, 6 Jun 2019 22:54:52 +0000 (00:54 +0200)]
vendor.xilinx_7series: fix typos.
whitequark [Thu, 6 Jun 2019 20:40:49 +0000 (20:40 +0000)]
build.dsl: fix precondition check in Pins.
Jean-François Nguyen [Thu, 6 Jun 2019 11:53:17 +0000 (13:53 +0200)]
vendor.xilinx_7series: implement.
whitequark [Wed, 5 Jun 2019 12:51:53 +0000 (12:51 +0000)]
build.res: allow querying frequency of a previously constrained clock.
whitequark [Wed, 5 Jun 2019 08:48:36 +0000 (08:48 +0000)]
build.{dsl,res,plat}: apply clock constraints to signals, not resources.
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.
Fixes #86.
whitequark [Wed, 5 Jun 2019 07:02:08 +0000 (07:02 +0000)]
build.dsl: replace extras= with Attrs().
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
whitequark [Wed, 5 Jun 2019 02:48:41 +0000 (02:48 +0000)]
Typos and style fixes. NFC.
whitequark [Tue, 4 Jun 2019 16:09:08 +0000 (16:09 +0000)]
vendor.lattice_ice40: normalize device names.
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
whitequark [Tue, 4 Jun 2019 13:11:15 +0000 (13:11 +0000)]
hdl.ir: rephrase elaboratable warning to not look like an error.
whitequark [Tue, 4 Jun 2019 13:09:36 +0000 (13:09 +0000)]
compat.fhdl.module: silence "unused elaboratable" warnings.
whitequark [Tue, 4 Jun 2019 13:03:56 +0000 (13:03 +0000)]
compat.fhdl.specials: fix platform lowering for TSTriple again.
whitequark [Tue, 4 Jun 2019 12:26:09 +0000 (12:26 +0000)]
compat.fhdl.specials: fix platform lowering.
get_tristate only has O/OE; the triple is created by get_input_output.
whitequark [Tue, 4 Jun 2019 12:00:02 +0000 (12:00 +0000)]
compat.fhdl.module: implement some TODO'd deprecation warnings.
whitequark [Tue, 4 Jun 2019 11:40:56 +0000 (11:40 +0000)]
build.run: fix product extraction to work on Windows.
Before this commit, it would fail with a "Permission denied" error.
whitequark [Tue, 4 Jun 2019 11:34:18 +0000 (11:34 +0000)]
build.plat: hide executed commands in quiet builds on Windows.
whitequark [Tue, 4 Jun 2019 11:33:51 +0000 (11:33 +0000)]
build.plat: allow (easily) overriding with an empty string on Windows.
whitequark [Tue, 4 Jun 2019 11:10:46 +0000 (11:10 +0000)]
compat.fhdl.module: CompatModule should be elaboratable.
Fixes #83.
whitequark [Tue, 4 Jun 2019 10:23:27 +0000 (10:23 +0000)]
build.res: use ConstraintError iff a constraint invariant is violated.
In particular don't use it for type errors.
whitequark [Tue, 4 Jun 2019 10:19:54 +0000 (10:19 +0000)]
hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
whitequark [Tue, 4 Jun 2019 09:47:04 +0000 (09:47 +0000)]
vendor.board: split off into nmigen-boards package.
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)
Fixes #80.
whitequark [Tue, 4 Jun 2019 09:13:24 +0000 (09:13 +0000)]
build.run: simplify using build products locally, e.g. for programming.
whitequark [Tue, 4 Jun 2019 08:37:52 +0000 (08:37 +0000)]
build.res: simplify emission of port constraints on individual bits.
whitequark [Tue, 4 Jun 2019 08:18:50 +0000 (08:18 +0000)]
Clean up imports.
This commit:
* moves lists of universally useful imports from `nmigen` to
`nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
* replaces lots of imports from individual parts of `nmigen.hdl`
with a star import from `nmigen.hdl`;
* replaces imports in tests with what we expect downstream code
to use;
* adds some missing imports in `nmigen.formal`.
whitequark [Tue, 4 Jun 2019 07:53:34 +0000 (07:53 +0000)]
build.run: extract from build.plat.
whitequark [Tue, 4 Jun 2019 06:43:10 +0000 (06:43 +0000)]
vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer.
Fixes #82.
whitequark [Tue, 4 Jun 2019 06:20:01 +0000 (06:20 +0000)]
vendor.board.tinyfpga_bx: fix typo.
whitequark [Mon, 3 Jun 2019 16:47:41 +0000 (16:47 +0000)]
vendor.conn.pmod: implement.
Fixes #79.
whitequark [Mon, 3 Jun 2019 16:16:44 +0000 (16:16 +0000)]
examples: reorganize into examples/basic and examples/board.
whitequark [Mon, 3 Jun 2019 16:14:59 +0000 (16:14 +0000)]
vendor.board: extract package.
whitequark [Mon, 3 Jun 2019 15:38:49 +0000 (15:38 +0000)]
vendor.tinyfpga_bx: add connectors.
whitequark [Mon, 3 Jun 2019 15:03:43 +0000 (15:03 +0000)]
vendor.icestick: add connectors.
whitequark [Mon, 3 Jun 2019 15:03:34 +0000 (15:03 +0000)]
vendor.ice40_hx1k_blink_evn: add (some) connectors.
I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.
whitequark [Mon, 3 Jun 2019 15:02:15 +0000 (15:02 +0000)]
build.{plat,res}: add support for connectors.
Fixes #77.
whitequark [Mon, 3 Jun 2019 13:03:49 +0000 (13:03 +0000)]
build.dsl: add support for connectors.
whitequark [Mon, 3 Jun 2019 09:39:38 +0000 (09:39 +0000)]
compat.fhdl.specials: TSTriple is not an elaboratable.
whitequark [Mon, 3 Jun 2019 09:23:11 +0000 (09:23 +0000)]
vendor.fpga.lattice_ice40: implement differential output buffers.
whitequark [Mon, 3 Jun 2019 08:38:12 +0000 (08:38 +0000)]
vendor.fpga.lattice_ice40: implement differential input buffers.
whitequark [Mon, 3 Jun 2019 07:54:28 +0000 (07:54 +0000)]
vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
whitequark [Mon, 3 Jun 2019 07:43:02 +0000 (07:43 +0000)]
vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers.
whitequark [Mon, 3 Jun 2019 05:56:18 +0000 (05:56 +0000)]
lib.io: add i_clk and o_clk to pin layout with xdr>=1.
whitequark [Mon, 3 Jun 2019 07:16:09 +0000 (07:16 +0000)]
hdl.rec: unbreak hasattr(rec, ...).
hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().
whitequark [Mon, 3 Jun 2019 04:39:05 +0000 (04:39 +0000)]
build.{dsl,plat,res}: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
whitequark [Mon, 3 Jun 2019 04:28:53 +0000 (04:28 +0000)]
lib.io: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
whitequark [Mon, 3 Jun 2019 03:32:30 +0000 (03:32 +0000)]
build.{res,plat}: use xdr=0 as default, not xdr=1.
The previous behavior was semantically incorrect.
whitequark [Mon, 3 Jun 2019 03:17:20 +0000 (03:17 +0000)]
build.res: allow requesting raw ports, with dir="-".
This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
whitequark [Mon, 3 Jun 2019 03:29:27 +0000 (03:29 +0000)]
lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.
whitequark [Mon, 3 Jun 2019 03:01:56 +0000 (03:01 +0000)]
vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
whitequark [Mon, 3 Jun 2019 02:54:17 +0000 (02:54 +0000)]
build.res: if not specified, request resource #0.
This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
whitequark [Mon, 3 Jun 2019 02:48:55 +0000 (02:48 +0000)]
vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
whitequark [Mon, 3 Jun 2019 02:39:14 +0000 (02:39 +0000)]
hdl.ir: accept LHS signals like slices as Instance io ports.
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
whitequark [Mon, 3 Jun 2019 02:22:55 +0000 (02:22 +0000)]
hdl.dsl: allow adding submodules with computed name, like with domains.
projects / nmigen.git / log