yosys.git
5 years agoFix stitching
Eddie Hung [Thu, 14 Feb 2019 01:04:23 +0000 (17:04 -0800)]
Fix stitching

5 years agoUse ConstEval to compute LUT masks
Eddie Hung [Thu, 14 Feb 2019 01:00:00 +0000 (17:00 -0800)]
Use ConstEval to compute LUT masks

5 years agoMerge remote-tracking branch 'origin/read_aiger' into xaig
Eddie Hung [Wed, 13 Feb 2019 22:09:36 +0000 (14:09 -0800)]
Merge remote-tracking branch 'origin/read_aiger' into xaig

5 years agoMerge https://github.com/YosysHQ/yosys into xaig
Eddie Hung [Wed, 13 Feb 2019 22:08:31 +0000 (14:08 -0800)]
Merge https://github.com/YosysHQ/yosys into xaig

5 years agoRip out some more stuff
Eddie Hung [Wed, 13 Feb 2019 18:44:52 +0000 (10:44 -0800)]
Rip out some more stuff

5 years agoFix sign handling of real constants
Clifford Wolf [Wed, 13 Feb 2019 11:36:47 +0000 (12:36 +0100)]
Fix sign handling of real constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRip out unused functions in abc9
Eddie Hung [Wed, 13 Feb 2019 00:25:22 +0000 (16:25 -0800)]
Rip out unused functions in abc9

5 years agoAdd support for read_aiger -wideports
Eddie Hung [Tue, 12 Feb 2019 20:58:10 +0000 (12:58 -0800)]
Add support for read_aiger -wideports

5 years agoAdd support for read_aiger -map
Eddie Hung [Tue, 12 Feb 2019 20:16:37 +0000 (12:16 -0800)]
Add support for read_aiger -map

5 years agoParse 'm' in xaiger
Eddie Hung [Tue, 12 Feb 2019 17:36:22 +0000 (09:36 -0800)]
Parse 'm' in xaiger

5 years agoWIP for ABC with aiger
Eddie Hung [Tue, 12 Feb 2019 17:31:22 +0000 (09:31 -0800)]
WIP for ABC with aiger

5 years agoMissing headers for Xcode?
Eddie Hung [Tue, 12 Feb 2019 17:24:13 +0000 (09:24 -0800)]
Missing headers for Xcode?

5 years agoMerge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
Eddie Hung [Tue, 12 Feb 2019 17:21:46 +0000 (09:21 -0800)]
Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger

5 years agoUse module->add{Not,And}Gate() functions
Eddie Hung [Tue, 12 Feb 2019 17:21:15 +0000 (09:21 -0800)]
Use module->add{Not,And}Gate() functions

5 years agoMerge pull request #802 from whitequark/write_verilog_async_mem_ports
Clifford Wolf [Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)]
Merge pull request #802 from whitequark/write_verilog_async_mem_ports

write_verilog: correctly emit asynchronous transparent ports

5 years agoMerge pull request #806 from daveshah1/fsm_opt_no_reset
Clifford Wolf [Tue, 12 Feb 2019 13:39:39 +0000 (14:39 +0100)]
Merge pull request #806 from daveshah1/fsm_opt_no_reset

fsm_opt: Fix runtime error for FSMs without a reset state

5 years agoAdd read_xaiger
Eddie Hung [Mon, 11 Feb 2019 23:19:17 +0000 (15:19 -0800)]
Add read_xaiger

5 years agoAdd write_xaiger
Eddie Hung [Mon, 11 Feb 2019 23:18:42 +0000 (15:18 -0800)]
Add write_xaiger

5 years agoDo not break for constraints
Eddie Hung [Mon, 11 Feb 2019 21:28:00 +0000 (13:28 -0800)]
Do not break for constraints

5 years agoNo increment line_count for binary ANDs
Eddie Hung [Mon, 11 Feb 2019 21:24:21 +0000 (13:24 -0800)]
No increment line_count for binary ANDs

5 years agoDo not ignore newline after AND in binary AIG
Eddie Hung [Mon, 11 Feb 2019 19:51:44 +0000 (11:51 -0800)]
Do not ignore newline after AND in binary AIG

5 years agoCopy backends/aiger/aiger.cc to xaiger.cc
Eddie Hung [Fri, 8 Feb 2019 22:53:12 +0000 (14:53 -0800)]
Copy backends/aiger/aiger.cc to xaiger.cc

5 years agoMerge remote-tracking branch 'origin/dff_init' into read_aiger
Eddie Hung [Fri, 8 Feb 2019 22:42:08 +0000 (14:42 -0800)]
Merge remote-tracking branch 'origin/dff_init' into read_aiger

5 years agoCompile abc9
Eddie Hung [Fri, 8 Feb 2019 21:58:47 +0000 (13:58 -0800)]
Compile abc9

5 years agoRefactor kernel/cost.h definition into cost.cc
Eddie Hung [Fri, 8 Feb 2019 21:58:20 +0000 (13:58 -0800)]
Refactor kernel/cost.h definition into cost.cc

5 years agoCopy abc.cc to abc9.cc
Eddie Hung [Fri, 8 Feb 2019 21:23:54 +0000 (13:23 -0800)]
Copy abc.cc to abc9.cc

5 years agoaddDff -> addDffGate as per @daveshah1
Eddie Hung [Fri, 8 Feb 2019 21:17:53 +0000 (13:17 -0800)]
addDff -> addDffGate as per @daveshah1

5 years agoFix tabulation
Eddie Hung [Fri, 8 Feb 2019 21:17:02 +0000 (13:17 -0800)]
Fix tabulation

5 years ago-module_name arg to go before -clk_name
Eddie Hung [Fri, 8 Feb 2019 20:49:55 +0000 (12:49 -0800)]
-module_name arg to go before -clk_name

5 years agoSupport and differentiate between ASCII and binary AIG testing
Eddie Hung [Fri, 8 Feb 2019 20:41:59 +0000 (12:41 -0800)]
Support and differentiate between ASCII and binary AIG testing

5 years agoAdd missing "[options]" to read_blif help
Eddie Hung [Fri, 8 Feb 2019 20:41:39 +0000 (12:41 -0800)]
Add missing "[options]" to read_blif help

5 years agoAllow module name to be determined by argument too
Eddie Hung [Fri, 8 Feb 2019 20:40:43 +0000 (12:40 -0800)]
Allow module name to be determined by argument too

5 years agoRefactor into AigerReader class
Eddie Hung [Fri, 8 Feb 2019 20:04:26 +0000 (12:04 -0800)]
Refactor into AigerReader class

5 years agoParse binary AIG files
Eddie Hung [Fri, 8 Feb 2019 19:45:16 +0000 (11:45 -0800)]
Parse binary AIG files

5 years agoAdd binary AIGs converted from AAG
Eddie Hung [Fri, 8 Feb 2019 19:41:25 +0000 (11:41 -0800)]
Add binary AIGs converted from AAG

5 years agoRefactor to parse_aiger_header()
Eddie Hung [Fri, 8 Feb 2019 18:54:31 +0000 (10:54 -0800)]
Refactor to parse_aiger_header()

5 years agoAdd comment
Eddie Hung [Fri, 8 Feb 2019 16:37:44 +0000 (08:37 -0800)]
Add comment

5 years agoHandle reset logic in latches
Eddie Hung [Fri, 8 Feb 2019 16:37:18 +0000 (08:37 -0800)]
Handle reset logic in latches

5 years agoChange literal vars from int to unsigned
Eddie Hung [Fri, 8 Feb 2019 16:09:30 +0000 (08:09 -0800)]
Change literal vars from int to unsigned

5 years agoCreate clk outside of latch loop
Eddie Hung [Fri, 8 Feb 2019 16:08:49 +0000 (08:08 -0800)]
Create clk outside of latch loop

5 years agoHandle latch symbols too
Eddie Hung [Fri, 8 Feb 2019 16:05:27 +0000 (08:05 -0800)]
Handle latch symbols too

5 years agoRemove return after log_error
Eddie Hung [Fri, 8 Feb 2019 16:04:48 +0000 (08:04 -0800)]
Remove return after log_error

5 years agoAdd support for symbol tables
Eddie Hung [Fri, 8 Feb 2019 16:03:40 +0000 (08:03 -0800)]
Add support for symbol tables

5 years agoStub for binary AIGER
Eddie Hung [Fri, 8 Feb 2019 15:31:04 +0000 (07:31 -0800)]
Stub for binary AIGER

5 years agofsm_opt: Fix runtime error for FSMs without a reset state
David Shah [Thu, 7 Feb 2019 10:35:36 +0000 (10:35 +0000)]
fsm_opt: Fix runtime error for FSMs without a reset state

Signed-off-by: David Shah <dave@ds0.me>
5 years agoCope WIDTH of ff/latch cells is default of zero
Eddie Hung [Wed, 6 Feb 2019 23:51:12 +0000 (15:51 -0800)]
Cope WIDTH of ff/latch cells is default of zero

5 years agoRefactor
Eddie Hung [Wed, 6 Feb 2019 22:58:47 +0000 (14:58 -0800)]
Refactor

5 years agoRemove check for cell->name[0] == '$'
Eddie Hung [Wed, 6 Feb 2019 22:53:40 +0000 (14:53 -0800)]
Remove check for cell->name[0] == '$'

5 years agoMerge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig
Eddie Hung [Wed, 6 Feb 2019 22:31:11 +0000 (14:31 -0800)]
Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig

5 years agoRevert most of autotest.sh; for non *.v use Yosys to translate
Eddie Hung [Wed, 6 Feb 2019 22:30:19 +0000 (14:30 -0800)]
Revert most of autotest.sh; for non *.v use Yosys to translate

5 years agoRefactor
Eddie Hung [Wed, 6 Feb 2019 22:28:44 +0000 (14:28 -0800)]
Refactor

5 years agowrite_verilog to cope with init attr on q when -noexpr
Eddie Hung [Wed, 6 Feb 2019 22:17:09 +0000 (14:17 -0800)]
write_verilog to cope with init attr on q when -noexpr

5 years agoAdd INIT parameter to all ff/latch cells
Eddie Hung [Wed, 6 Feb 2019 22:16:26 +0000 (14:16 -0800)]
Add INIT parameter to all ff/latch cells

5 years agoAdd tests for simple cases using defparam
Eddie Hung [Wed, 6 Feb 2019 22:15:17 +0000 (14:15 -0800)]
Add tests for simple cases using defparam

5 years agoAdd -B option to autotest.sh to append to backend_opts
Eddie Hung [Wed, 6 Feb 2019 22:14:55 +0000 (14:14 -0800)]
Add -B option to autotest.sh to append to backend_opts

5 years agoExtend testcase
Eddie Hung [Wed, 6 Feb 2019 22:02:11 +0000 (14:02 -0800)]
Extend testcase

5 years agoAdd testcase
Eddie Hung [Wed, 6 Feb 2019 20:49:30 +0000 (12:49 -0800)]
Add testcase

5 years agoRename ASCII tests
Eddie Hung [Wed, 6 Feb 2019 20:20:36 +0000 (12:20 -0800)]
Rename ASCII tests

5 years agoWIP
Eddie Hung [Wed, 6 Feb 2019 20:19:48 +0000 (12:19 -0800)]
WIP

5 years agoAdd missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id...
Clifford Wolf [Wed, 6 Feb 2019 15:35:59 +0000 (16:35 +0100)]
Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd tests
Eddie Hung [Tue, 5 Feb 2019 00:46:24 +0000 (16:46 -0800)]
Add tests

5 years agowrite_verilog: correctly emit asynchronous transparent ports.
whitequark [Tue, 29 Jan 2019 02:24:00 +0000 (02:24 +0000)]
write_verilog: correctly emit asynchronous transparent ports.

This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.

5 years agoMerge pull request #798 from mmicko/master
Clifford Wolf [Sun, 27 Jan 2019 08:25:18 +0000 (09:25 +0100)]
Merge pull request #798 from mmicko/master

Fixed Anlogic simulation model

5 years agoMerge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf [Sun, 27 Jan 2019 08:23:41 +0000 (09:23 +0100)]
Merge pull request #800 from whitequark/write_verilog_tribuf

write_verilog: write $tribuf cell as ternary

5 years agoMerge branch 'whitequark-write_verilog_keyword'
Clifford Wolf [Sun, 27 Jan 2019 08:17:29 +0000 (09:17 +0100)]
Merge branch 'whitequark-write_verilog_keyword'

5 years agoRemove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf [Sun, 27 Jan 2019 08:17:02 +0000 (09:17 +0100)]
Remove asicworld tests for (unsupported) switch-level modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agowrite_verilog: write $tribuf cell as ternary.
whitequark [Sun, 27 Jan 2019 00:21:31 +0000 (00:21 +0000)]
write_verilog: write $tribuf cell as ternary.

5 years agowrite_verilog: escape names that match SystemVerilog keywords.
whitequark [Sat, 26 Jan 2019 23:55:46 +0000 (23:55 +0000)]
write_verilog: escape names that match SystemVerilog keywords.

5 years agoMerge pull request #796 from whitequark/proc_clean_typo
David Shah [Fri, 25 Jan 2019 21:33:06 +0000 (21:33 +0000)]
Merge pull request #796 from whitequark/proc_clean_typo

proc_clean: fix critical typo

5 years agoFixed Anlogic simulation model
Miodrag Milanovic [Fri, 25 Jan 2019 18:25:25 +0000 (19:25 +0100)]
Fixed Anlogic simulation model

5 years agoproc_clean: fix critical typo.
whitequark [Wed, 23 Jan 2019 22:08:38 +0000 (22:08 +0000)]
proc_clean: fix critical typo.

5 years agoMerge pull request #793 from whitequark/proc_clean_fix_fully_def
Clifford Wolf [Sat, 19 Jan 2019 08:31:17 +0000 (09:31 +0100)]
Merge pull request #793 from whitequark/proc_clean_fix_fully_def

proc_clean: fix fully def check to consider compare/signal length

5 years agoproc_clean: fix fully def check to consider compare/signal length.
whitequark [Fri, 18 Jan 2019 23:22:02 +0000 (23:22 +0000)]
proc_clean: fix fully def check to consider compare/signal length.

Fixes #790.

5 years agoCleanups in igloo2 example design
Clifford Wolf [Thu, 17 Jan 2019 13:54:04 +0000 (14:54 +0100)]
Cleanups in igloo2 example design

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd SF2 IO buffer insertion
Clifford Wolf [Thu, 17 Jan 2019 13:38:37 +0000 (14:38 +0100)]
Add SF2 IO buffer insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove Igloo2 example
Clifford Wolf [Thu, 17 Jan 2019 12:35:52 +0000 (13:35 +0100)]
Improve Igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf [Thu, 17 Jan 2019 12:33:45 +0000 (13:33 +0100)]
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "write_edif -gndvccy"
Clifford Wolf [Thu, 17 Jan 2019 12:33:11 +0000 (13:33 +0100)]
Add "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd optional nullstr argument to log_id()
Clifford Wolf [Sun, 13 Jan 2019 16:00:58 +0000 (17:00 +0100)]
Add optional nullstr argument to log_id()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of $shiftx in Verilog back-end
Clifford Wolf [Tue, 15 Jan 2019 09:55:27 +0000 (10:55 +0100)]
Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #788 from whitequark/master
Clifford Wolf [Tue, 15 Jan 2019 08:52:01 +0000 (09:52 +0100)]
Merge pull request #788 from whitequark/master

Document $tribuf and some gates

5 years agoMerge pull request #787 from whitequark/flowmap_relax
Clifford Wolf [Tue, 15 Jan 2019 08:50:58 +0000 (09:50 +0100)]
Merge pull request #787 from whitequark/flowmap_relax

flowmap: implement depth relaxation

5 years agomanual: document some gates.
whitequark [Mon, 14 Jan 2019 16:17:25 +0000 (16:17 +0000)]
manual: document some gates.

5 years agomanual: explain $tribuf cell.
whitequark [Mon, 14 Jan 2019 16:08:58 +0000 (16:08 +0000)]
manual: explain $tribuf cell.

5 years agoImprove igloo2 example
Clifford Wolf [Tue, 8 Jan 2019 19:16:36 +0000 (20:16 +0100)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoflowmap: clean up terminology.
whitequark [Tue, 8 Jan 2019 02:05:06 +0000 (02:05 +0000)]
flowmap: clean up terminology.

  * "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.

5 years agoflowmap: implement depth relaxation.
whitequark [Fri, 4 Jan 2019 13:06:51 +0000 (13:06 +0000)]
flowmap: implement depth relaxation.

5 years agoFix typo in manual
Clifford Wolf [Mon, 7 Jan 2019 09:07:28 +0000 (10:07 +0100)]
Fix typo in manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in $memrd sharing
Clifford Wolf [Mon, 7 Jan 2019 09:01:11 +0000 (10:01 +0100)]
Bugfix in $memrd sharing

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #782 from whitequark/flowmap_dfs
Clifford Wolf [Mon, 7 Jan 2019 08:47:57 +0000 (09:47 +0100)]
Merge pull request #782 from whitequark/flowmap_dfs

 flowmap: construct a max-volume max-flow min-cut, not just any one

5 years agoSwitch "bugpoint" from system() to run_command()
Clifford Wolf [Mon, 7 Jan 2019 08:45:21 +0000 (09:45 +0100)]
Switch "bugpoint" from system() to run_command()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #783 from whitequark/bugpoint
Clifford Wolf [Mon, 7 Jan 2019 08:42:17 +0000 (09:42 +0100)]
Merge pull request #783 from whitequark/bugpoint

bugpoint: new pass

5 years agobugpoint: new pass.
whitequark [Mon, 7 Jan 2019 00:11:49 +0000 (00:11 +0000)]
bugpoint: new pass.

A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)

5 years agoflowmap: construct a max-volume max-flow min-cut, not just any one.
whitequark [Sun, 6 Jan 2019 19:51:37 +0000 (19:51 +0000)]
flowmap: construct a max-volume max-flow min-cut, not just any one.

5 years agoMerge pull request #780 from phire/rename_from_wire
Clifford Wolf [Sun, 6 Jan 2019 10:35:31 +0000 (11:35 +0100)]
Merge pull request #780 from phire/rename_from_wire

Rename cells based on the wires they drive.

5 years agoRename cells based on the wires they drive.
Scott Mansell [Sun, 6 Jan 2019 01:40:10 +0000 (14:40 +1300)]
Rename cells based on the wires they drive.

5 years agoAdd skeleton Yosys-Libero igloo2 example project
Clifford Wolf [Sat, 5 Jan 2019 16:02:01 +0000 (17:02 +0100)]
Add skeleton Yosys-Libero igloo2 example project

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in Verilog string handling
Clifford Wolf [Sat, 5 Jan 2019 11:10:24 +0000 (12:10 +0100)]
Bugfix in Verilog string handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoflowmap: add -minlut option, to allow postprocessing with opt_lut.
whitequark [Fri, 4 Jan 2019 21:18:03 +0000 (21:18 +0000)]
flowmap: add -minlut option, to allow postprocessing with opt_lut.

5 years agoMerge pull request #777 from mmicko/achronix_cell_sim_fix
Clifford Wolf [Fri, 4 Jan 2019 14:18:18 +0000 (15:18 +0100)]
Merge pull request #777 from mmicko/achronix_cell_sim_fix

Fix cells_sim.v for Achronix FPGA