Wesley W. Terpstra [Tue, 21 Mar 2017 23:47:13 +0000 (16:47 -0700)]
bootrom: set a0 to hartid and a1 to dtb before boot
Wesley W. Terpstra [Tue, 21 Mar 2017 23:44:43 +0000 (16:44 -0700)]
configstring: rename variables to dts
Wesley W. Terpstra [Tue, 21 Mar 2017 23:40:01 +0000 (16:40 -0700)]
riscv: remove dependency on num_cores
Wesley W. Terpstra [Tue, 21 Mar 2017 23:06:49 +0000 (16:06 -0700)]
bootrom: include compiled dtb
Wesley W. Terpstra [Sat, 4 Mar 2017 03:02:03 +0000 (19:02 -0800)]
sim: create DTS instead of config string
Wesley W. Terpstra [Sat, 4 Mar 2017 02:51:37 +0000 (18:51 -0800)]
sim: define emulated CPU clock rate to be 1GHz
Wesley W. Terpstra [Sat, 4 Mar 2017 02:50:37 +0000 (18:50 -0800)]
autoconf: put location of 'dtc' into config.h
Andrew Waterman [Mon, 20 Mar 2017 07:48:16 +0000 (00:48 -0700)]
PUM -> SUM; expose MXR to S-mode
Andrew Waterman [Thu, 16 Mar 2017 19:36:32 +0000 (12:36 -0700)]
Simplify interrupt-stack discipline
https://github.com/riscv/riscv-isa-manual/commit/
f2ed45b1791bb602657adc2ea9ab5fc409c62542
Andrew Waterman [Mon, 13 Mar 2017 21:48:52 +0000 (14:48 -0700)]
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
Andrew Waterman [Tue, 7 Mar 2017 09:58:41 +0000 (01:58 -0800)]
Don't overload illegal instruction trap in interactive code
Andrew Waterman [Mon, 27 Feb 2017 00:13:17 +0000 (16:13 -0800)]
Sv57 and Sv64 are not spec'd yet
Andrew Waterman [Sat, 25 Feb 2017 23:28:27 +0000 (15:28 -0800)]
New counter enable scheme
https://github.com/riscv/riscv-isa-manual/issues/10
Andrew Waterman [Tue, 21 Feb 2017 02:48:35 +0000 (18:48 -0800)]
serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
Andrew Waterman [Tue, 21 Feb 2017 01:17:17 +0000 (17:17 -0800)]
Take M-mode interrupts over S-mode interrupts
Andrew Waterman [Tue, 21 Feb 2017 01:16:58 +0000 (17:16 -0800)]
permit MMIO loads to MSIP bit
Andrew Waterman [Sun, 19 Feb 2017 01:24:04 +0000 (17:24 -0800)]
Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
Andrew Waterman [Sat, 18 Feb 2017 11:03:10 +0000 (03:03 -0800)]
Spike uarch needs TLB flush after SPTBR write
Andrew Waterman [Wed, 15 Feb 2017 11:06:34 +0000 (03:06 -0800)]
sfence.vm -> sfence.vma
Andrew Waterman [Wed, 8 Feb 2017 22:16:08 +0000 (14:16 -0800)]
Encode VM type in sptbr, not mstatus
https://github.com/riscv/riscv-isa-manual/issues/4
Also, refactor gdbserver code to not duplicate VM decoding logic.
Tim Newsome [Tue, 7 Feb 2017 17:07:59 +0000 (09:07 -0800)]
Merge pull request #83 from bacam/gdb-protocol-fixes
Gdb protocol fixes
Andrew Waterman [Fri, 3 Feb 2017 03:25:49 +0000 (19:25 -0800)]
Fix interrupt delegation for coprocessors
Andrew Waterman [Thu, 2 Feb 2017 07:11:59 +0000 (23:11 -0800)]
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
Resolves #76
Andrew Waterman [Thu, 2 Feb 2017 06:33:38 +0000 (22:33 -0800)]
Set xPIE=1 on xRET
Resolves #88.
Andrew Waterman [Sun, 8 Jan 2017 02:03:16 +0000 (18:03 -0800)]
Only allow SIP.SSIP to be toggled if the interrupt is delegated
Andrew Waterman [Sun, 8 Jan 2017 01:56:22 +0000 (17:56 -0800)]
Make SIP.STIP read-only
h/t Ron Minnich
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8
David Craven [Sat, 31 Dec 2016 15:24:42 +0000 (16:24 +0100)]
Comply with GNU coding standards.
Currently the DESTDIR variable is not used correctly which leads to
bogus RUNPATH entries.
https://www.gnu.org/prep/standards/html_node/DESTDIR.html
Brian Campbell [Fri, 30 Dec 2016 21:14:50 +0000 (21:14 +0000)]
Only read exception flag in gdb register read/write. (#85)
The flag is 32 bits, and if we read 64/128 bits then we get fragments of
S1 too and can accidentally send an error. Fixes #84.
Brian Campbell [Wed, 21 Dec 2016 17:53:45 +0000 (17:53 +0000)]
Fix gdb communication error (#82)
Brian Campbell [Tue, 20 Dec 2016 12:32:51 +0000 (12:32 +0000)]
Remove extra gdb protocol responses on register writes
Brian Campbell [Mon, 19 Dec 2016 17:54:19 +0000 (17:54 +0000)]
Fix gdb protocol register read of S0
Stefan O'Rear [Sat, 17 Dec 2016 02:24:41 +0000 (18:24 -0800)]
Use correct format codes for reg_t and size_t
Fixes 32-bit build.
Tim Newsome [Fri, 16 Dec 2016 05:12:34 +0000 (21:12 -0800)]
Fix single stepping over faulting instructions. (#80)
Tim Newsome [Mon, 12 Dec 2016 20:48:58 +0000 (12:48 -0800)]
Reuse the ebreak constants in encoding.h.
Andy Wright [Thu, 1 Dec 2016 20:04:34 +0000 (15:04 -0500)]
Added comments about the modified Duff's Device in execute.cc (#77)
Andrew Waterman [Mon, 14 Nov 2016 00:10:30 +0000 (16:10 -0800)]
Fix 32-bit host portability bug
Ben Gamari [Sat, 12 Nov 2016 01:06:12 +0000 (19:06 -0600)]
Ensure that g++ knows it is building a PCH (#75)
It seems that g++ 5.4 doesn't realize that it is building a precompiled
header unless you pass it -x c++-header.
Andrew Waterman [Thu, 10 Nov 2016 21:40:37 +0000 (13:40 -0800)]
AMOs should always return store faults, not load faults
This commit also factors out the common AMO code into mmu_t.
Tim Newsome [Mon, 31 Oct 2016 20:10:45 +0000 (13:10 -0700)]
Make reading/writing fpu regs work.
Temporarily turn them on in mstatus if necessary.
Tim Newsome [Mon, 31 Oct 2016 19:25:15 +0000 (12:25 -0700)]
Minor code cleanup.
Tim Newsome [Mon, 31 Oct 2016 18:57:15 +0000 (11:57 -0700)]
Check for exception after register write.
Tim Newsome [Fri, 28 Oct 2016 21:01:42 +0000 (14:01 -0700)]
Check for exception after reading a register.
Tim Newsome [Fri, 28 Oct 2016 20:30:43 +0000 (13:30 -0700)]
Fix error message.
It was erroneously complaining that gdb sent too much data even when it
wasn't.
Tim Newsome [Tue, 25 Oct 2016 20:17:40 +0000 (13:17 -0700)]
Increase gdb receive buffer.
Newer gdbs send larger memory write packets when downloading.
Also improve error reporting when gdb sends packets that don't fit in
the buffer.
Andrew Waterman [Mon, 10 Oct 2016 20:32:25 +0000 (13:32 -0700)]
Don't force load trigger timing to After
Allow the CSR writer to make the choice.
@timsifive @colinschmidt this fixes the failing rv64mi-p-breakpoint test.
Tim Newsome [Fri, 7 Oct 2016 15:56:05 +0000 (08:56 -0700)]
Don't die when gdb thinks XLEN is 64 but it's 32.
Instead, just give gdb what it asks for.
Also when gdb does a register write, let the user know that it's likely
misconfigured and tell them how to fix it.
This is probably as well as issue #72 can be fixed in spike.
Tim Newsome [Fri, 30 Sep 2016 21:08:26 +0000 (14:08 -0700)]
Return an error to gdb when memory reads fail. (#71)
Tim Newsome [Thu, 29 Sep 2016 18:24:04 +0000 (11:24 -0700)]
Update trigger behavior. (#70)
M-mode writes to tdata1 with dmode set are ignored instead of raising an
exception.
Add the same behavior for tdata2.
Scott Beamer [Tue, 13 Sep 2016 20:42:05 +0000 (13:42 -0700)]
restore clang support by fixing printf identifiers
Andrew Waterman [Sat, 10 Sep 2016 01:35:09 +0000 (18:35 -0700)]
allow MAFDC bits in MISA to be modified
Tim Newsome [Tue, 6 Sep 2016 17:25:36 +0000 (10:25 -0700)]
Remove generic debug tests. (#65)
They live in riscv-tests/debug now, since they also test gdb, and can be
used to test other targets besides spike.
Andrew Waterman [Fri, 2 Sep 2016 20:43:40 +0000 (13:43 -0700)]
Merge pull request #62 from riscv/trigger
Implement address and data triggers.
Tim Newsome [Fri, 2 Sep 2016 20:28:14 +0000 (13:28 -0700)]
Merge branch 'master' into trigger
Conflicts:
riscv/encoding.h
riscv/processor.cc
Tim Newsome [Fri, 2 Sep 2016 20:08:46 +0000 (13:08 -0700)]
Rebuild debug ROM because CSR encoding changed.
Tim Newsome [Fri, 2 Sep 2016 19:37:38 +0000 (12:37 -0700)]
Support triggers on TLB misses.
Tim Newsome [Thu, 1 Sep 2016 20:05:44 +0000 (13:05 -0700)]
Theoretically support trigger timing.
Tim Newsome [Wed, 31 Aug 2016 22:51:58 +0000 (15:51 -0700)]
Rename tdata[0-2] to tdata[1-3].
Add timing bit (but it doesn't do anything).
Implement dmode bit.
Tim Newsome [Wed, 31 Aug 2016 22:51:03 +0000 (15:51 -0700)]
Save/restore tselect. Set dmode.
Tim Newsome [Mon, 29 Aug 2016 21:40:07 +0000 (14:40 -0700)]
Fix indent.
Tim Newsome [Mon, 29 Aug 2016 18:49:47 +0000 (11:49 -0700)]
Rename tdata0--tdata2 to tdata1--tdata3.
Andrew Waterman [Sat, 27 Aug 2016 02:51:09 +0000 (19:51 -0700)]
Add (degenerate) performance counter facility
Andrew Waterman [Fri, 26 Aug 2016 04:36:09 +0000 (21:36 -0700)]
Allow reads from tdrdata registers
Andrew Waterman [Fri, 26 Aug 2016 04:27:10 +0000 (21:27 -0700)]
partially update spike to newer debug spec
Andrew Waterman [Fri, 26 Aug 2016 03:24:14 +0000 (20:24 -0700)]
Fix spike interactive (-d) mode
Andrew Waterman [Tue, 23 Aug 2016 01:33:28 +0000 (18:33 -0700)]
remove HWBPCOUNT field of DCSR
Tim Newsome [Mon, 22 Aug 2016 16:49:20 +0000 (09:49 -0700)]
Implement address and data triggers.
So far I only have testcases for instruction and data address.
Not implemented is the mechanism that lets the debugger prevent a user
program from using triggers at all. I'll be adding that soonish.
The critical path is unchanged, but my experimenting shows the
simulation is slowed down about 8% by this code. Reducing the size of
trigger_match() (which is never called during my benchmark) fixes that,
but making it not be inlined has no effect. I suspect the slowdown comes
from cache alignment or something similar, and on a different CPU or
after more code changes the speed will come back.
Andrew Waterman [Wed, 17 Aug 2016 21:00:58 +0000 (14:00 -0700)]
Allow mstatus.MPP to store bad values; instead, validate on MRET
Either approach is legal, but this more closely matches Rocket.
Colin Schmidt [Tue, 16 Aug 2016 18:42:16 +0000 (11:42 -0700)]
remove old rvc directory (#61)
Tim Newsome [Thu, 28 Jul 2016 21:51:31 +0000 (14:51 -0700)]
Add support for virtual priv register. (#59)
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
Andrew Waterman [Fri, 22 Jul 2016 21:05:06 +0000 (14:05 -0700)]
Set U bit in misa register
Tim Newsome [Tue, 19 Jul 2016 18:19:47 +0000 (11:19 -0700)]
Make address translation work in 32-bit. (#58)
Tim Newsome [Wed, 13 Jul 2016 20:26:09 +0000 (13:26 -0700)]
Fix single step over csrw instructions. (#57)
csrw instructions instantly return if the PC isn't serialized. Take note
of this, and don't enter debug mode until the instruction we just
executed actually completed.
Andrew Waterman [Tue, 12 Jul 2016 19:43:30 +0000 (12:43 -0700)]
Don't treat RVC NOP as illegal instruction
Andrew Waterman [Tue, 12 Jul 2016 19:43:07 +0000 (12:43 -0700)]
Fix page table walker not respecting valid bit
Andrew Waterman [Wed, 6 Jul 2016 10:22:18 +0000 (03:22 -0700)]
Update to new PTE format
Tim Newsome [Fri, 1 Jul 2016 16:51:26 +0000 (09:51 -0700)]
Remove debug printf that was cluttering up output.
Andrew Waterman [Wed, 29 Jun 2016 22:00:22 +0000 (15:00 -0700)]
Disassemble RVC instructions based on XLEN
The interpretation of RVC opcodes depends on XLEN, and the disassembler
always assumed RV32.
h/t Michael Clark
Tim Newsome [Tue, 14 Jun 2016 20:34:54 +0000 (13:34 -0700)]
Make gdbserver code work with small Debug RAM.
Tim Newsome [Tue, 14 Jun 2016 00:55:47 +0000 (17:55 -0700)]
Support debugging 32-bit spike instances.
Andrew Waterman [Thu, 23 Jun 2016 06:29:16 +0000 (23:29 -0700)]
Parameterize debug ROM contents on XLEN
Andrew Waterman [Thu, 23 Jun 2016 06:28:39 +0000 (23:28 -0700)]
Remove fence.i from debug ROM
Andrew Waterman [Thu, 23 Jun 2016 06:25:55 +0000 (23:25 -0700)]
Don't use I$ in debug mode
This avoids the need for fence.i.
Andrew Waterman [Thu, 23 Jun 2016 05:52:29 +0000 (22:52 -0700)]
Remove legacy HTIF; implement HTIF directly
Andrew Waterman [Thu, 23 Jun 2016 05:51:12 +0000 (22:51 -0700)]
Fix paddr_bits computation prior to VM setup
Andrew Waterman [Sat, 18 Jun 2016 03:58:01 +0000 (20:58 -0700)]
Merge sasid into sptbr
Andrew Waterman [Thu, 9 Jun 2016 21:20:54 +0000 (14:20 -0700)]
Trap on tdrdata registers when tdrselect[XLEN-1]=0
Jonathan Neuschäfer [Sat, 4 Jun 2016 12:13:45 +0000 (14:13 +0200)]
make check: Fail if the tests failed
Tim Newsome [Thu, 9 Jun 2016 17:18:32 +0000 (10:18 -0700)]
Fix 2 bugs in Debug ROM: (#52)
1. Debug ROM wasn't actually writing 0xffffffff to the last word in
Debug RAM after an exception happened.
2. Fix a race where debug interrupts were cleared before that write
would have happened, so a debugger (gdbserver.cc in this case) might get
the wrong idea about whether an exception happened or not.
Why wasn't this wreaking havoc before?
Andrew Waterman [Thu, 9 Jun 2016 03:04:17 +0000 (20:04 -0700)]
Add degenerate HW breakpoint implementation
Tim Newsome [Fri, 3 Jun 2016 22:07:04 +0000 (15:07 -0700)]
Keep DCSR_XDEBUGVER unsigned.
neuschaefer [Fri, 3 Jun 2016 20:45:05 +0000 (22:45 +0200)]
Minor usability improvements (#48)
* spike_main/disasm.cc: Print unknown CSR numbers in hex
* interactive mode: Print "Unknown command" when appropriate
Tim Newsome [Fri, 3 Jun 2016 20:08:09 +0000 (13:08 -0700)]
DCSR cause was moved, bug debug ROM wasn't updated
As a result Debug ROM would always take the spontaneous halt code path.
This didn't hurt spike since (so far?) the spike debug handler doesn't
attempt to do anything quick while code is running. But now the ROM is
more correct.
Tim Newsome [Thu, 2 Jun 2016 18:01:37 +0000 (11:01 -0700)]
Fix 'make check' when run from build directory.
Andrew Waterman [Wed, 1 Jun 2016 20:54:46 +0000 (13:54 -0700)]
Fix build when not building inside root directory
Andrew Waterman [Wed, 1 Jun 2016 20:54:38 +0000 (13:54 -0700)]
Add gitignore
Tim Newsome [Wed, 1 Jun 2016 15:39:31 +0000 (08:39 -0700)]
Move sethaltnot and cleardebint.
Now it matches Krste's memory map.
Tim Newsome [Tue, 24 May 2016 21:37:23 +0000 (14:37 -0700)]
New encoding.h for new CSR addresses.
Tim Newsome [Tue, 24 May 2016 16:39:44 +0000 (09:39 -0700)]
Move cleardebint, per spec.
Tim Newsome [Mon, 23 May 2016 23:24:59 +0000 (16:24 -0700)]
Use .word for mret, for now.
The current assembler doesn't seem to know it?
Tim Newsome [Mon, 23 May 2016 23:17:28 +0000 (16:17 -0700)]
Change DCSR bits to match spec.
Cleaned up debug ROM code a little.