Gabor Dozsa [Thu, 2 Jun 2016 09:48:20 +0000 (10:48 +0100)]
style: remove extra newline from white space verifier fix method
Change-Id: I7bce7d1cb04efe20d31445eb67ea5ffd2a4a41f4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Thu, 2 Jun 2016 09:48:16 +0000 (10:48 +0100)]
style: respect per verifier ignores for git commit
Change-Id: Id00379bdb17594e627ee49c077fb75f499ea550e
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 2 Jun 2016 09:37:16 +0000 (10:37 +0100)]
style: Move the last bits of file_types.py to the style package
The commit that refactored the style checkers into a new Python
package (style: Refactor the style checker as a Python package)
accidentally left a fragment of file_types.py in the old location
(util/style.py). This was caused by a race between the commit that
moved the file and Nate's commit that added a copyright header to the
file.
This commit moves the last fragment (the copyright header) and removes
the old file.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
946f1f6fee034ae79bd50ea7dfc3299a60f070c0
Curtis Dunham [Tue, 31 May 2016 15:55:47 +0000 (16:55 +0100)]
stats: update and fix
e273e86a873d
Andreas Sandberg [Tue, 31 May 2016 11:14:40 +0000 (12:14 +0100)]
arm: Enable LPAE support by default
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's
enable it by default.
Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Andreas Sandberg [Tue, 31 May 2016 11:14:37 +0000 (12:14 +0100)]
arm: Correctly check translation mode (aarch64/aarch32)
According to the ARM ARM (see AArch32.TranslateAddress in the
pseudocode library), the TLB should be operating in aarch64 mode if
the EL0 is aarch32 and EL1 is aarch64. This is currently not the case
in gem5, which breaks 64/32 interprocessing. Update the check to match
the reference manual.
Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Tue, 31 May 2016 10:27:00 +0000 (11:27 +0100)]
scons: Use the new test framework from scons
Rewrite the SCons script responsible for launching tests to use the
new test framework. The biggest visible change after this changeset is
that SCons no longer produces a "status" file in test build
directories. Instead, it creates a status.pickle file. That file can
be inspected using the new tests.py script. Another visible change is
that timed out tests are now reported as failed rather than a using a
separate summary message.
Since the pickle file will remain in the build directory after running
tests, it's now possible to convert the test results into other
formats. For example:
./tests/tests.py show --format junit -o junit.xml \
`find build/ -name status.pickle`
To better facilitate running outside of scons, there is now a set of
targets that generate test listings that can be used by the test
script. There are currently three targets, quick.list, long.list, and
all.list. For example:
scons build/ARM/tests/opt/all.list
for F in `cat build/ARM/tests/opt/all.list`; do
./tests/tests.py run build/ARM/gem5.opt $F
done
Change-Id: I2c0f8ca0080d7af737362e198eda4cb3a72e6c36
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Tue, 31 May 2016 10:26:59 +0000 (11:26 +0100)]
tests: Fix incorrect stat.txt ignore when updating refs
ClassicTest was incorrectly ignoring stats.txt when updating reference
statistics. This was caused by ignore rules being applied too
aggressively when listing reference files. This changeset splits the
ignore rules into two different lists: 1) diff_ignore_files that lists
the files that shouldn't be diff:ed using the normal diff tool, and 2)
ref_ignore_files which lists files that should be ignored by the test
system.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Tue, 31 May 2016 10:07:18 +0000 (11:07 +0100)]
stats: update for snoop filter tweak
--HG--
extra : source :
2323557eb4f4866fa1ea1575a9f5969e0022adc1
Stephan Diestelhorst [Fri, 27 May 2016 16:05:58 +0000 (17:05 +0100)]
mem, config: Selective use of snoop filter
Disable the default snoop filter in the SystemXBar so that the
typical membus does not have a snoop filter by default. Instead,
add the snoop filter only when there are caches added to the system
(with the caches / l2cache options).
The underlying problem is that the snoop filter grows without
bounds (for now) if there are no caches to tell it that lines have
been evicted. This causes slow regression runs for all the atomic
regressions. This patch fixes this behaviour.
--HG--
extra : source :
f97c20511828209757440839ed48d741d02d428f
Andreas Hansson [Mon, 30 May 2016 06:10:48 +0000 (02:10 -0400)]
scons: Bump minimum gcc version to 4.8
After reaching consensus on the mailing list, this patch officially
makes gcc 4.8 the minimum.
A few checks in the SConstruct are cleaned up as a result. This patch
also adds "-fno-omit-frame-pointer" when using ASAN (which is part of
the gcc/clang recommended flags).
Ilias Vougioukas [Fri, 27 May 2016 15:55:01 +0000 (16:55 +0100)]
cpu: fix lastStopped unserialisation
MinorCPU fix for corrupt numCycles when resuming from a previous simulation.
---
src/cpu/minor/cpu.cc | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
Akash Bagdia [Fri, 27 May 2016 15:54:59 +0000 (16:54 +0100)]
power: Allow voltage to be configured via cmd line
---
src/python/m5/params.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Matteo Andreozzi [Fri, 27 May 2016 15:46:03 +0000 (16:46 +0100)]
scons: Enable override suggestions on gcc 5.0+
---
SConstruct | 4 ++++
1 file changed, 4 insertions(+)
Andreas Sandberg [Fri, 27 May 2016 14:02:01 +0000 (15:02 +0100)]
arm: Use the target EL state when determining fault format
We currently check the current state instead of the state of the
target EL when determining how we report a fault. This breaks
interprocessing since EL0 in aarch32 would report its fault status
using the aarch32 registers even if EL1 is in aarch64. Fix this to
report the fault using the format of the target EL.
Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Andreas Sandberg [Thu, 26 May 2016 16:38:15 +0000 (17:38 +0100)]
arm: Fix incorrect TLB permission check in aarch32
The TLB currently assumes that the pxn bit in an LPAE page descriptor
disables execution from unprivileged mode. However, according to the
architecture manual, this bit should disable execution from privileged
modes. Update the TLB implementation to reflect this behavior.
Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Thu, 26 May 2016 16:33:38 +0000 (17:33 +0100)]
arm: Make EL checks available in SE mode
A lot of code assumes that it is possible to test what the highest EL
is and if it is 64 bit. These calls currently don't work in SE mode
since they rely on an instance of an ArmSystem.
Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Fix memory leak in handling of deferred snoops
This patch fixes a memory leak where deferred snoop packets never got
deallocated. On the call to MSHR::handleSnoop these snoops were
treated as if a response will be sent, as the MSHR was
pendingModified. Consequently, a copy of the packet was created and
added to the MSHR targets. However, an preceeding target to the same
MSHR, originally from a CPU, was serviced before the snoop, and caused
the block to be invalidated. This happens for ReadExReq and
UpgradeReq.
Note that the original snoop will receive a response, just not from
the cache in question, but instead from the cache upstream that issued
the ReadExReq or UpgradeReq.
Change-Id: I4ac012fbc8a46cf693ca390fe9476105d444e6f4
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
dev, arm: Add a flag to enable/disable gem5 GIC extensions
Make it possible to disable gem5 gic extensions by setting the
gem5_extensions param to False from Python.
Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
cpu: Add a basic progress check to the TrafficGen
This patch adds a progress check to the TrafficGen so that it is
easier to detect deadlock scenarios where the generator gets stuck
waiting for a retry, and makes no further progress.
Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Do not set cacheResponding on MSHR snoop if not responding
This patch changes the flow control for HSHR::handleSnoop to ensure
that we only set cacheResponding on the snoop packet if we are
actually responding. This avoids situations where a responder is
stalling indefinitely on a response that never arrives.
Change-Id: I691dd01755b614b30203581aa74fc743b350eacc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: Fix MemChecker unique_ptr type mismatch
This patch fixes the type of the unique_ptr instances, to ensure that
the data that is allocated with new[] is also deleted with
delete[]. The issue was highlighted by ASAN.
Change-Id: I2c5510424959d862a9954d83e728d901bb18d309
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
arm: Fix heap overflow issue in Neon64Load operation
This patch fixes an issue identified by ASAN where the Neon64Load
operation assumes the packet always contains 16 bytes.
Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Hansson [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
arm, dev: Remove superfluous loop increment in flash device
As identified by clang-3.8, there was a superfluous loop increment in
the flash device which is now removed.
Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
Nikos Nikoleris [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: fix headers include order in the cache related classes
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: remove redudant check whether the cache forwards snoops
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: change NULL to nullptr in the cache related classes
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
mem: fix the line length in the cache related classes
Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 26 May 2016 10:56:24 +0000 (11:56 +0100)]
tests: Add test infrastructure as a Python module
Implement gem5's test infrastructure as a Python module and a run
script that can be used without scons. The new implementation has
several features that were lacking from the previous test
infrastructure such as support for multiple output formats, automatic
runtime tracking, and better support for being run in a cluster
environment.
Tests consist of one or more steps (TestUnit). Units are run in two
stages, the first a run stage and then a verify stage. Units in the
verify stage are automatically skipped if any unit run stage wasn't
run. The library currently contains TestUnit implementations that run
gem5, diff stat files, and diff output files.
Existing tests are implemented by the ClassicTest class and "just
work". New tests can that don't rely on the old "run gem5 once and
diff output" strategy can be implemented by subclassing the Test base
class or ClassicTest.
Test results can be output in multiple formats. The module currently
supports JUnit, text (short and verbose), and Python's pickle
format. JUnit output allows CI systems to automatically get more
information about test failures. The pickled output contains all state
necessary to reconstruct a tests results object and is mainly intended
for the build system and CI systems.
Since many JUnit parsers parsers assume that test suite names look
like Java package names. We currently output path-like names with
slashes separating components. Test names are translated according to
these rules:
* '.' -> '-"
* '/' -> '.'
The test tool, tests.py, supports the following features:
* Test listing. Example: ./tests.py list arm/quick
* Running tests. Example:
./tests.py run -o output.pickle --format pickle \
../build/ARM/gem5.opt \
quick/se/00.hello/arm/linux/simple-timing
* Displaying pickled results. Example:
./tests.py show --format summary *.pickle
Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joel Hestness <jthestness@gmail.com>
Bjoern A. Zeeb [Thu, 19 May 2016 20:19:35 +0000 (15:19 -0500)]
config, x86: Properly space pad the X86IntelMPBus Entry descriptions
According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.
(*) http://www.intel.com/design/pentium/datashts/
24201606.pdf
Committed by Jason Lowe-Power <power.jg@gmail.com>
Bjoern A. Zeeb [Thu, 19 May 2016 20:19:35 +0000 (15:19 -0500)]
arm,dev: PL011 UART_FR read status enhancement
Given we do not simulate a FIFO currently there are only two states
we can be in upon read: empty or full. Properly signal the latter.
Add and sort constants for states in the header file.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Bjoern A. Zeeb [Thu, 19 May 2016 20:19:35 +0000 (15:19 -0500)]
x86, dev: properly space the APIC registers
Registers are 0x10 and not 0x8 apart. The latter leads to invalid
calculations of index in array which in turn means that we will not
find the interrupt we were looking (been notified) for in the OS.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Bjoern A. Zeeb [Thu, 19 May 2016 20:19:34 +0000 (15:19 -0500)]
dev, virtio: properly set PCI address space to use IOREG
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped.
Set the correct bit on the PCI address accordingly.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Tony Gutierrez [Mon, 16 May 2016 19:36:24 +0000 (15:36 -0400)]
gpu-compute: fix bug in GPUDynInst::isScalarRegister()
Andreas Sandberg [Mon, 9 May 2016 10:32:11 +0000 (11:32 +0100)]
scons: Rewrite git style hook installer
The SCons script currently assumes that .git is a proper directory
with all git meta data. This isn't the case if the working directory
was checked out using git worktrees. In such case .git is a file with
meta data telling git where the repository data is stored.
This changeset updates changes the SConstruct file to rely on git
rev-parse to get the real git directory.
Change-Id: I3d0475eabc12e868193797067a88e540a9b6e927
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Mon, 9 May 2016 10:32:07 +0000 (11:32 +0100)]
tests: Enable test running outside of gem5's source tree
The learning gem5 scripts currently assumes that the current working
directory is the root of gem5's source tree. This isn't necessarily
the case when running the tests using gem5's new test runner.
Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Steve Reinhardt [Sat, 7 May 2016 18:43:06 +0000 (14:43 -0400)]
tests: update EIO ref stats for removed cache stats
Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:
e55afadc4e19.
Tony Gutierrez [Fri, 6 May 2016 21:00:54 +0000 (17:00 -0400)]
gpu-compute: fix spacing in GPUDynInst ctor
Tony Gutierrez [Fri, 6 May 2016 20:44:38 +0000 (16:44 -0400)]
gpu-compute: fix uninitialized member bug in GPUDynInst
the n_reg field in the GPUDynInst is not currently set in the constructor.
if it is not set externally, there are assertion failures that may occur
if the random value it gets is just right. here we set it to 0 by default.
Andreas Sandberg [Fri, 6 May 2016 14:52:34 +0000 (15:52 +0100)]
dev, arm: Update GIC to use GICv2 register naming
The GICv2 has a new and slightly more consistent register
naming. Update gem5's GIC register names to match the new
documentation.
Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Fri, 6 May 2016 14:51:45 +0000 (15:51 +0100)]
arm: Update dts to work with the new HDLCD driver
The dts files in system/arm/dt currently assume that an (unreleased)
gem5-specific virtual encoder is used as a remote endpoint for the
HDLCD. This driver won't be released as a more general virtual encoder
is about to be posted on the Linux DRI devel list and this encoder has
now been merged with gem5's kernel tree. This changeset updates gem5's
dts files to use that encoder.
Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
Curtis Dunham [Thu, 28 Apr 2016 14:20:03 +0000 (15:20 +0100)]
scons: emit correct message before installing git hook
Change-Id: Ied2e018a9a1b6db446edbaac871ac4efd795ec36
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Thu, 28 Apr 2016 14:19:58 +0000 (15:19 +0100)]
style: ignore test data in style checks
Change-Id: If797eaf3842b5c1604942bb60f091800ee814a2a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Thu, 28 Apr 2016 14:18:52 +0000 (15:18 +0100)]
style: respect ignores for git commit
Previously it ignored the ignores for git but not Mercurial.
Change-Id: I178fe879ebd268e863063eb9e30ec87e8ac8faec
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Thu, 28 Apr 2016 14:17:50 +0000 (15:17 +0100)]
style: improve compatibility with old git versions
Older versions of git need the '=' to connect --diff-filter to
its argument.
Change-Id: Ic62057567db061684be88a7c2d80a6a5d4c11dcf
Andreas Sandberg [Thu, 28 Apr 2016 14:17:28 +0000 (15:17 +0100)]
style: Don't include diff context in git style hook
The git style hook currently includes a few lines of diff context when
determining changed regions. This is undesirable as this triggers
false positives when modifying existing files with a lot of style
violations. This change sets the amount of context to 0, which is the
default value when requesting staged regions from the git helper.
Change-Id: Ibe03123e329ea0241281e104183a68d6c495b190
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Andreas Sandberg [Thu, 28 Apr 2016 14:16:52 +0000 (15:16 +0100)]
tests: Remove stale reference output files
Remove test reference files that are not generated any more:
* chair.cook.ppm: This file should be generated by eon and not
mcf, so it shouldn't be included as an output from mcf.
* system.pc.terminal: The terminal device has been renamed so this
file is no longer generated.
Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Wed, 27 Apr 2016 14:34:58 +0000 (15:34 +0100)]
arm: Remove BreakPCEvent on guest kernel panic
The LinuxArmSystem class normally provides support for panicing gem5
if the simulated kernel panics. When this is turned off (default),
gem5 uses a BreakPCEvent to provide a debugger hook into the simulator
when the kernel crashes. This hook unconditionally kills gem5 with a
SIGTRAP unless gem5 is compiled in fast mode. This is undesirable
since the panic_on_panic param already provides similar functionality.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Wed, 27 Apr 2016 14:34:48 +0000 (15:34 +0100)]
kvm, arm: Make GIC interrupt lines configurable
Add support for overriding the number of interrupt lines in the ARM
KvmGic.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Wed, 27 Apr 2016 14:34:31 +0000 (15:34 +0100)]
kvm, arm: Refactor KVM GIC device
Factor out the kernel device wrapper from the KvmGIC and put it in a
separate class. This will simplify a future kernel/gem5 hybrid GIC.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Wed, 27 Apr 2016 14:33:58 +0000 (15:33 +0100)]
dev: Fix incorrect terminal backlog handling
The Terminal device currently uses the peek functionality in gem5's
circular buffer implementation to send existing buffered content on
the terminal when a new client attaches. This functionallity is
however not implemented correctly and re-sends the same block multiple
time.
Add the required functionality to peek with an offset into the
circular buffer and change the Terminal::accept() implementation to
send the buffered contents.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Matthew Poremba [Tue, 26 Apr 2016 16:07:51 +0000 (12:07 -0400)]
ruby: Rename pkt to m_pkt so it may be accessed via SLICC
Allow usage of packet class in ruby for convenience purposes. This may be
used to access members of the packet/request class (e.g., via helper
functions) and/or push protocol specific information to the packets
SenderState without needing to modify SLICC types and protocols in multiple
locations.
Andreas Hansson [Mon, 25 Apr 2016 07:46:12 +0000 (03:46 -0400)]
tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing
memcheck.py script.
--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
Jason Power [Thu, 21 Apr 2016 22:25:31 +0000 (17:25 -0500)]
tests: Update learning gem5 tests scripts with copyright
Andreas Hansson [Thu, 21 Apr 2016 08:48:24 +0000 (04:48 -0400)]
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
Andreas Hansson [Thu, 21 Apr 2016 08:48:20 +0000 (04:48 -0400)]
mem: Include WriteLineReq in cache demand stats
Somehow the WriteLineReq were never added to the list of commands
considered demand.
Andreas Hansson [Thu, 21 Apr 2016 08:48:19 +0000 (04:48 -0400)]
mem: Remove unused cache stats
Prune cache stats that are never actually used.
Andreas Hansson [Thu, 21 Apr 2016 08:48:07 +0000 (04:48 -0400)]
mem: Deallocate all write-queue entries when sent
This patch removes the write-queue entry tracking previously used for
uncacheable writes. The write-queue entry is now deallocated as soon
as the packet is sent. As a result we also forego the stats for
uncacheable writes. Additionally, there is no longer a need to attach
the write-queue entry to the packet.
Andreas Hansson [Thu, 21 Apr 2016 08:48:06 +0000 (04:48 -0400)]
mem: Align downstream cache packet creation in atomic and timing
This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
Andreas Hansson [Thu, 21 Apr 2016 08:48:04 +0000 (04:48 -0400)]
config: Add missing point of coherency to memcheck script
Bring in line with changes to the XBar class.
Andreas Sandberg [Mon, 18 Apr 2016 09:40:50 +0000 (10:40 +0100)]
scons: Fix Python 2.6 compatibility
Don't use Python 2.7-style with statements in the SConstruct file.
Andreas Sandberg [Mon, 18 Apr 2016 09:31:38 +0000 (10:31 +0100)]
style: Fix Python 2.6 compatibility
The style checker code needs to disable autojunk when diffing source
files using Python's difflib. Support for this was only introduced in
Python 2.7, which leads to a TypeError exception on older Python
version. This changeset adds a fallback mechanism for old Python
versions.
Joel Hestness [Fri, 15 Apr 2016 17:34:02 +0000 (12:34 -0500)]
ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.
To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.
Bjoern A. Zeeb [Fri, 15 Apr 2016 15:03:03 +0000 (10:03 -0500)]
arm,dev: remove PMU assertion hit on reset
Remve the assertion that we always need to add a delta larger than
zero as that does not seem to be true when we hit it in the
'PMU reset cycle counter to zero' case.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Bjoern A. Zeeb [Fri, 15 Apr 2016 15:02:58 +0000 (10:02 -0500)]
mem: FreeBSD does not provide MAP_NORESERVE either
Like OS X, FreeBSD does not support MAP_NORESERVE.
Handle accordingly and update comment.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Abdul Mutaal Ahmad [Fri, 15 Apr 2016 14:55:26 +0000 (09:55 -0500)]
misc: Bugfix in TLM memInhibit Command
memInhibitAsserted() has been removed from packet.hh. This change has been
reflected in TLM based SystemC memory.
This patch also adds a number of panics asserting the SystemC memory only
sees requests it expects.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Mohammad Alian [Thu, 14 Apr 2016 18:07:42 +0000 (14:07 -0400)]
dist: config file for distributed switch
Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.
Andreas Hansson [Wed, 13 Apr 2016 16:13:44 +0000 (12:13 -0400)]
misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:
1. -Wmisleading-indentation
In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.
2. -Wshift-negative-value
gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.
That is all. Porting done.
Andreas Hansson [Tue, 12 Apr 2016 09:28:39 +0000 (05:28 -0400)]
misc: Appease clang...again
Once again, clang is having issues with recently committed code.
Unfortunately HSAIL_X86 is still broken.
Andreas Hansson [Sat, 9 Apr 2016 16:13:40 +0000 (12:13 -0400)]
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Curtis Dunham [Fri, 8 Apr 2016 16:01:45 +0000 (11:01 -0500)]
stats: update stats for thermals, indirect BP
Rekai Gonzalez Alberquilla [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Add priority to QueuedPrefetcher
Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.
For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
Rekai Gonzalez Alberquilla [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Handful extra features for BasePrefetcher
Some common functionality added to the base prefetcher, mainly dealing with
extracting the block address, page address, block index inside the page and
some other information that can be inferred from the block address. This is
used for some prefetching algorithms, and having the methods in the base,
as well as the block size and other information is the sensible way.
Victor Garcia [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Add Program Counter to MemTraceProbe
Rekai Gonzalez Alberquilla [Wed, 27 May 2015 12:50:01 +0000 (13:50 +0100)]
mem: Add unused prefetch counter in caches
Added stat to the cache to account for HardPF'ed blocks that are evicted
before being referenced (over-prefetching).
Mitch Hayenga [Thu, 7 Apr 2016 14:30:20 +0000 (09:30 -0500)]
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of
20264eb after the revert (
bd1c6789) and includes
some fixes of that commit.
Mitch Hayenga [Tue, 5 Apr 2016 17:20:19 +0000 (12:20 -0500)]
cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis. This makes that so.
This is a re-spin of
fb51231 after the revert (
bd1c6789).
Mitch Hayenga [Tue, 5 Apr 2016 16:48:37 +0000 (11:48 -0500)]
cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
This is a re-spin of
fb9d142 after the revert (
bd1c6789).
Mitch Hayenga [Tue, 5 Apr 2016 16:44:27 +0000 (11:44 -0500)]
cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
Sascha Bischoff [Wed, 6 Apr 2016 16:55:17 +0000 (17:55 +0100)]
misc: Bail out of DVFS dot if we cannot resolve the domains
This changeset updates the dot output to bail out if it is unable to
resolve the voltage or clock domains (which will cause it to raise an
AttributeError). Additionally, the DVFS dot output is disabled by
default for speed purposes.
Minor fixup for
0aeca8f.
Andreas Sandberg [Thu, 7 Apr 2016 09:42:07 +0000 (10:42 +0100)]
Revert to
74c1e6513bd0 (sim: Thermal support for Linux)
Andreas Sandberg [Wed, 6 Apr 2016 18:43:31 +0000 (19:43 +0100)]
Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:
e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
0b6fb073c6bbc24be533ec431eb51fbf1b269508
Mitch Hayenga [Tue, 5 Apr 2016 17:39:21 +0000 (12:39 -0500)]
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Curtis Dunham [Tue, 5 Apr 2016 17:20:19 +0000 (12:20 -0500)]
cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis. This makes that so.
Mitch Hayenga [Tue, 5 Apr 2016 16:48:37 +0000 (11:48 -0500)]
cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
Mitch Hayenga [Tue, 5 Apr 2016 16:44:27 +0000 (11:44 -0500)]
cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
David Guillen Fandos [Tue, 5 Apr 2016 15:52:28 +0000 (10:52 -0500)]
power: Add support for power models
This patch adds some basic support for power models in gem5.
The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.
The model allows it to be extended to use other kinds of models.
Finally, the thermal model is updated to use the power usage as input.
Akash Bagdia [Tue, 9 Dec 2014 10:42:08 +0000 (10:42 +0000)]
power: Low-power idle power state for idle CPUs
Add functionality to the BaseCPU that will put the entire CPU into a low-power
idle state whenever all threads in it are idle.
Akash Bagdia [Tue, 18 Nov 2014 14:00:48 +0000 (14:00 +0000)]
power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
David Guillen Fandos [Wed, 13 May 2015 14:02:25 +0000 (15:02 +0100)]
sim: Thermal support for Linux
This patch enables Linux to read the temperature using hwmon infrastructure.
In order to use this in your gem5 you need to compile the kernel using the
following configs:
CONFIG_HWMON=y
CONFIG_SENSORS_VEXPRESS=y
And a proper dts file (containing an entry such as):
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
temp@0 {
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
};
David Guillen Fandos [Tue, 12 May 2015 09:26:47 +0000 (10:26 +0100)]
sim: Adding thermal model support
This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
Mitch Hayenga [Tue, 5 Apr 2016 13:08:12 +0000 (08:08 -0500)]
cpu: Add instruction opclass histogram to minor
Sascha Bischoff [Tue, 15 Dec 2015 09:40:56 +0000 (09:40 +0000)]
misc: Add secondary dot output for DVFS domains
This patch adds a secondary dot output file which shows the DVFS domains. This
has been done separately for now to avoid cluttering the already existing
diagram. Due to the way that the clock domains are assigned to components in
gem5, this output must be generated after the C++ objects have been
instantiated. This further motivates the need to generate this file separately
to the current dot output, and not to replace it entirely.
Sascha Bischoff [Fri, 11 Dec 2015 17:29:53 +0000 (17:29 +0000)]
sim: Add additional debug information when draining
This patch adds some additional information when draining the system which
allows the user to debug which SimObject(s) in the system is failing to drain.
Only enabled for the builds with tracing enabled and is subject to the Drain
debug flag being set at runtime.
Sascha Bischoff [Fri, 1 Apr 2016 15:22:44 +0000 (16:22 +0100)]
sim: Fix clock_domain unserialization
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level was not restored
due to a bug in the code, which detected the post-unserialize update
as superfluous. This patch splits the setting of the clock domain into
two parts. The original interface of perfLevel is retained, but the
actual update takes place in signalPerfLevelUpdate, which is private
to the class. The perfLevel method checks that if the new performance
level is different to the previous performance level, and will only
call signalPerfLevelUpdate if there is a change. Therefore, the
performance level is only updated, and voltage domains notified, if
there is an actual change. The split functionality allows
signalPerfLevelUpdate to be called by startup() to explicitly force an
update post unserialization.
Geoffrey Blake [Tue, 5 Apr 2016 10:29:02 +0000 (05:29 -0500)]
cpu: Query CPU for inst executed from Python
This patch adds the ability for the simulator to query the number of
instructions a CPU has executed so far per hw-thread. This can be used
to enable more flexible periodic events such as taking checkpoints
starting 1s into simulation and X instructions thereafter.
Steve Reinhardt [Fri, 1 Apr 2016 23:38:16 +0000 (16:38 -0700)]
syscall_emul: remove mmapFlagTable
After all this it turns out we don't even use it.
Steve Reinhardt [Fri, 1 Apr 2016 23:38:15 +0000 (16:38 -0700)]
syscall_emul: factor out flag tables into common file
The openFlagTable and mmapFlagTables for emulated Linux
platforms are basically identical, but are specified
repetitively for every platform. Use a common file
that gets included for each platform so that we only
have one copy, making them more consistent and simplifying
changes (like adding #ifdefs).
In the process, made some minor fixes that slipped through
due to previous inconsistencies, and added more #ifdefs
to try to fix building on alternative hosts.
Andreas Sandberg [Wed, 30 Mar 2016 15:21:27 +0000 (16:21 +0100)]
misc: Don't build region.py as a PySource
The style refactor change (style: Refactor the style checker as a
Python package) moved region.py from src/python/m5/util/ to
util/style/. The SConscript update accidentally got lost in that
commit. This commit removes region.py from src/python/SConscript.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
f69b75bf636dd4a4232af3e10c29f7eaa4d59dc8
Andreas Sandberg [Wed, 30 Mar 2016 14:56:02 +0000 (15:56 +0100)]
arm: Clean up m5ops assembly library
The m5ops assembly library contains a lot of repetitive code. This
changeset adds two macros, FOREACH_M5OP and FOREACH_M5_ANNOTATION, to
m5ops.h that simplify architecture-specific implementations. The ARM
and ARMv8 m5op implementations have been updated to use the new
macros.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>