Timothy Arceri [Wed, 22 Jun 2016 02:41:27 +0000 (12:41 +1000)]
glsl/mesa: stop duplicating tes layout values
We already store this in gl_shader and gl_program here we
remove it from gl_shader_program and just use the values
from gl_shader.
This will allow us to keep the shader cache restore code as
simple as it can be while making it somewhat clearer where these
values originate from.
V2: remove unnecessary NULL check
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral <itoral@igalia.com>
Edward O'Callaghan [Wed, 22 Jun 2016 10:42:30 +0000 (20:42 +1000)]
.mailmap: Fixup my email address
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Christian Gmeiner [Mon, 20 Jun 2016 07:44:22 +0000 (09:44 +0200)]
st/mesa: expose EXT_vertex_array_bgra when supported by backend
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 16 Jun 2016 22:26:54 +0000 (15:26 -0700)]
anv: Use different BOs for different scratch sizes and stages
This solves a race condition where we can end up having different stages
stomp on each other because they're all trying to scratch in the same BO
but they have different views of its layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 16 Jun 2016 21:58:25 +0000 (14:58 -0700)]
genxml: Make ScratchSpaceBasePointer an address instead of an offset
While we're here, we also fixup MEDIA_VFE_STATE and rename the field in
3DSTATE_VS on gen6-7.5 to be consistent with the others.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 16 Jun 2016 21:43:41 +0000 (14:43 -0700)]
anv: Add an allocator for scratch buffers
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 18:37:46 +0000 (11:37 -0700)]
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
The pack header generation scripts can't handle the case where you have
two addresses in the same dword; they just take whatever is the last one.
This meant that the MCS address wasn't properly getting handled. Since we
don't care about append counters, we can just re-arrange the XML for now.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 9 Jun 2016 20:56:16 +0000 (13:56 -0700)]
anv,isl: Lower storage image formats in anv
ISL was being a bit too clever for its own good and lowering the format for
us. This is all well and good *if* we always want to lower it. However,
the GL driver selectively lowers the format depending on whether the
surface is write-only or not.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 10 Jun 2016 17:45:43 +0000 (10:45 -0700)]
isl/state: Allow for full 31-bit buffer texture sizes
Ivy Bridge and above can handle up to 2^31 elements for RAW buffer
surfaces.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 11 Jun 2016 01:28:49 +0000 (18:28 -0700)]
isl/state: Don't use designated initializers for buffer surface state
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 10 Jun 2016 01:48:07 +0000 (18:48 -0700)]
isl/state: Add assertions for buffer surface restrictions
Acked-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 9 Jun 2016 22:08:13 +0000 (15:08 -0700)]
isl/state: Don't set SurfacePitch for gen9 1-D textures
This field is ignored by the hardware in this case and, on very large 1-D
textures, it can end up being larger than the maximum allowed value.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 21:33:40 +0000 (14:33 -0700)]
isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
This matches better what happens on gen8 where the "Tiled Surface" and
"Tile Walke" bits are combined into a single two-bit value. This is also
more consistent with what the GL driver does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 01:22:21 +0000 (18:22 -0700)]
isl/state: Emit no-op mip tail setup on SKL
This hasn't ever been a problem in the past but it is recommended by the
hardware docs.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 01:21:17 +0000 (18:21 -0700)]
isl/state: Only set cube face enables if usage includes CUBE_BIT
It seems safe to set it all the time, but this reduces the diff between
the way i965 does it and what ISL does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sun, 5 Jun 2016 04:22:21 +0000 (21:22 -0700)]
isl/state: Use the layout for computing qpitch rather than dimensions
For depth/stencil 1-D textures on SKL, we want them layed out in the old
format that has been used since gen4. In order for the surface state
fill-out code to handle, this it needs to distinguish based on layout
rather than just dimensionality.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 15:05:45 +0000 (08:05 -0700)]
isl/state: Set the IntegerSurfaceFormat bit on Haswell
This fixes 688 Vulkan CTS tests on Haswell.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 21:40:47 +0000 (14:40 -0700)]
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 17 Jun 2016 23:40:24 +0000 (16:40 -0700)]
isl/state: Don't set RenderTargetViewExtent for texture surfaces
The docs specify that this only matters for render targets and surfaces
used with typed dataport messages. On some platforms (gen4-6) the Depth
field has more bits than RenderTargetViewExtent so we can have textures
with more levels than we can render to.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 22:30:00 +0000 (15:30 -0700)]
isl/state: Set SurfaceArray based on the surface dimension
According to the PRM, you can't set SurfaceArray for 3D or buffer textures.
There doesn't seem to be a good reason not to set it when we can. On the
other hand, if we don't set it we can end up getting strange results for
1-layer array textures such as textureSize() returning the wrong results.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sun, 5 Jun 2016 03:48:55 +0000 (20:48 -0700)]
isl/state: Don't force-disable L2 bypass for everything
We already set the bit in the few cases where it's required by the docs so
there's no need to set it all the time. This has no noticable perf impact
for Dota 2 on Vulkan with the time demo I have.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 3 Jun 2016 02:02:23 +0000 (19:02 -0700)]
isl/state: Refactor the setup of clear colors
This commit switches clear colors to use #if's instead of a C if. This
lets us properly handle SNB where the clear color field doesn't exist.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 3 Jun 2016 02:00:10 +0000 (19:00 -0700)]
isl/state: Refactor the per-gen isl_to_gen_h/valign tables
This moves the #if's around so that halign and valign have different sets
of #if conditions. This also prepares us for SNB because isl_to_gen_halign
is not defined at all on gen6.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 3 Jun 2016 01:40:07 +0000 (18:40 -0700)]
isl/state: Return an extent3d from the halign/valign helper
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 8 Jun 2016 00:01:56 +0000 (17:01 -0700)]
isl/state: Put pitch calculations together
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 23:58:54 +0000 (16:58 -0700)]
isl/state: Put all dimension setup together and towards the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 8 Jun 2016 00:14:39 +0000 (17:14 -0700)]
isl/state: Put surface format setup at the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 23:55:21 +0000 (16:55 -0700)]
isl/state: Remove some unused fields
They're already zero-initialized and we have no plans of doing anything
more interesting with them.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 23:53:19 +0000 (16:53 -0700)]
isl/state: Don't use designated initializers for the surface state
While designated initializers are nice, they also force us to put some
things in the initializer and some things later. Surface state setup is
complicated enough that this really hurts readability in the long run.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 3 Jun 2016 01:43:59 +0000 (18:43 -0700)]
genxml/gen8,9: Prefix the multisample format enum with MSFMT
This is what gen7 does and it's nice to have a prefix
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 10 Jun 2016 21:44:32 +0000 (14:44 -0700)]
i965/blorp: Only set src_z for gen8+ 3D textures
Otherwise, we end up with a bogus value in the third component. On gen6-7
where we always use 2D textures, this can cause problems if the
SurfaceArray bit is set in the SURFACE_STATE.
Acked-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 11 Jun 2016 14:51:30 +0000 (07:51 -0700)]
i965/gen7,8: Set SURFACE_IS_ARRAY for all non-3D texture types
There's no real reason why we shouldn't set this bit. It does affect how
the sampler operates a bit but since you can have a 2D non-array view of a
2D_ARRAY texture that distinction is very weak. Also, this is what ISL
will do and we would like this change to be isolated from using ISL.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 11 Jun 2016 04:11:02 +0000 (21:11 -0700)]
i965/gen4: Subtract 1 from buffer sizes
The PRM states that the values put in Width, Height, and Depth should be
various bits from the value size - 1. We seem to have done this wrong
more-or-less from the start.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 9 Jun 2016 22:52:52 +0000 (15:52 -0700)]
i965: Remove fake W-tiled render target support
This hasn't been used since
1cfb4bc890b8 where we deleted the meta stencil
blit path.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 7 Jun 2016 02:15:39 +0000 (19:15 -0700)]
i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
Previously, we were incrementing length but not actually putting anything
in the Y coordinate. This meant that 1-D TXF operations had a garbage
array index. If the surface is emitted as 1-D non-array, the coordinate
gets discarded and it works fine. If it happens to be bound as an array
surface, it may count as an out-of-bounds array access and you get zero.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 4 Jun 2016 21:32:37 +0000 (14:32 -0700)]
i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 4 Jun 2016 06:25:19 +0000 (23:25 -0700)]
i965/blorp/gen8: Use the correct max level and layer in emit_surface_states
We were adding in the base which is wrong because the values given in the
miptree are relative to zero and not the base layer/level.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 9 Jun 2016 21:57:33 +0000 (14:57 -0700)]
i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be
set to the depth of a 3-D texture when rendering. Unfortunatley, that
field is only 9 bits on Sandy Bridge and prior so we can't actually bind
a 3-D texturing for rendering if it has depth > 512. On Ivy Bridge, this
field was bumpped to 11 bits so we can go all the way up to 2048. On Iron
Lake and prior, we don't support layered rendering and we use OffsetX/Y
hacks to render to particular layers so 2048 is ok there too.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 22 Jun 2016 18:11:29 +0000 (11:11 -0700)]
i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctly
This is basically a direct translation of what we do for gen7.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 22 Jun 2016 04:58:23 +0000 (21:58 -0700)]
i965/gen4: Pull texture formats from the texture object not the miptree
This makes texture views sort-of work. It doesn't add full texture view
support for gen4-5 but it is enough to fix the GL_ARB_copy_image formats
piglit test on Iron Lake.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Thu, 2 Jun 2016 00:32:55 +0000 (17:32 -0700)]
i965: Fix point size with tessellation/geometry shaders in GLES.
Our previous code worked for desktop GL, and ES without geometry or
tessellation shaders. But those features require fancier point size
handling. Fortunately, we can use one rule for all APIs.
Fixes a number of dEQP tests with EXT_tessellation_shader enabled:
dEQP-GLES31.functional.tessellation_geometry_interaction.point_size.*
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Wed, 22 Jun 2016 12:45:04 +0000 (14:45 +0200)]
.mailmap: fix my main address
Timothy Arceri [Tue, 26 Apr 2016 09:52:45 +0000 (19:52 +1000)]
i965: move vs outputs written into a helper
We will reuse this for fs key generation for the on disk shader
cache.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Nicolai Hähnle [Tue, 14 Jun 2016 18:03:53 +0000 (20:03 +0200)]
st/mesa: use a single memcpy in st_ReadPixels when possible
This avoids costly address recomputations, function overhead, and may trigger
large copy optimizations.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Tue, 21 Jun 2016 20:16:17 +0000 (16:16 -0400)]
glsl: only match gl_FragData and not gl_SecondaryFragDataEXT
There's special logic around finding gl_FragData. It latches onto any
array with FRAG_RESULT_DATA0. However gl_SecondaryFragDataEXT[], added
by GL_EXT_blend_func_extended, fits those parameters as well. The real
frag data array should have index 0 though, so we can use that to
distinguish them.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96617
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 19 Jun 2016 01:54:37 +0000 (21:54 -0400)]
nv50,nvc0: fix start_instance in manual push path
The start instance is applied as an offset into the buffer directly,
ignoring the divisor, not as an instance id offset that respects the
divisor.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sun, 19 Jun 2016 04:43:06 +0000 (00:43 -0400)]
translate: fix start_instance parameter in sse version
The generic version gets this right already, but this was using an
incorrect formula in SSE.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Jason Ekstrand [Tue, 21 Jun 2016 22:32:09 +0000 (15:32 -0700)]
anv/cmd: Dirty descriptor sets when a new pipeline is bound
Ever since
c2581a9375ea, the binding table layout has depended on the
pipeline. This means that whenever we change pipelines we also need to
re-emit binding tables for the new layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 21 Jun 2016 22:31:14 +0000 (15:31 -0700)]
anv/cmd: Move emit_descriptor_pointers to genX_cmd_buffer.c
It's tiny and fully generic so there's really no reason for it to be in a
gen7-specific file.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 21 Jun 2016 22:28:15 +0000 (15:28 -0700)]
anv/cmd: Move flush_descriptor_sets to anv_cmd_buffer.c
There's no good reason for recompiling it
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 21 Jun 2016 06:41:11 +0000 (23:41 -0700)]
spirv: Use the system value version of gl_FrontFace
SPIR-V treats it as an input but NIR wants the system value. This
shouldn't have been too much of a surprise given that we have to do the
same conversion in the GLSL IR to NIR pass.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Tue, 14 Jun 2016 06:09:31 +0000 (23:09 -0700)]
i965: Reorganize prog_data->total_scratch code a bit.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Fri, 10 Jun 2016 20:43:29 +0000 (22:43 +0200)]
radeonsi: add a debug flag for unsafe math LLVM optimizations
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 10 Jun 2016 01:03:11 +0000 (03:03 +0200)]
radeonsi: use u_blitter for mipmap generation
This reduces time spend in glGenerateMipmap by a half.
v2: don't decompress the levels to be overwritten
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 10 Jun 2016 01:02:24 +0000 (03:02 +0200)]
gallium/u_blitter: implement mipmap generation
for pipe_context::generate_mipmap
first move some of the blit code from util_blitter_blit_generic
to a separate function, then use it from util_blitter_generate_mipmap
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 8 Jun 2016 11:24:14 +0000 (13:24 +0200)]
st/mesa: cache staging texture for glReadPixels
v2: add ST_DEBUG flag for disabling (suggested by Ilia)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Nicolai Hähnle [Thu, 9 Jun 2016 10:16:26 +0000 (12:16 +0200)]
st/mesa: invalidate readpixels cache
Whenever a draw happens or some other function call might change the result
of future glReadPixels calls, we must invalidate the cache.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 8 Jun 2016 11:22:52 +0000 (13:22 +0200)]
st/mesa: add readpix_cache structure
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 8 Jun 2016 11:01:05 +0000 (13:01 +0200)]
st/mesa: move ReadPixels blit into a separate function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 10 Jun 2016 13:59:58 +0000 (15:59 +0200)]
st/mesa: flush bitmap cache before CopyImageSubData
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 9 Jun 2016 10:22:31 +0000 (12:22 +0200)]
st/mesa: flush bitmap cache before texture functions
As far as I can tell, a sequence of glBitmap followed by texture functions
that refer to a texture bound as the framebuffer is well within what should
be allowed.
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 9 Jun 2016 10:12:34 +0000 (12:12 +0200)]
st/mesa: flush bitmap cache before compute dispatch
In the unlikely case that a program uses glBitmap to render to a framebuffer
whose texture is bound in a compute shader.
Found by inspection.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 20 Jun 2016 07:40:23 +0000 (17:40 +1000)]
i965: get PrimitiveMode from the program rather than the shader struct
This is more consistent with what we do elsewhere and will allow
us to only cache one of the values in the shader cache.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Vedran Miletić [Mon, 20 Jun 2016 23:17:49 +0000 (01:17 +0200)]
clover: Fix build against clang SVN >= r273191
setLangDefaults() now requires PreprocessorOptions as an argument.
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Kenneth Graunke [Wed, 8 Jun 2016 23:09:02 +0000 (16:09 -0700)]
i965: Fix multiplication of immediates on Cherryview/Broxton.
Cherryview and Broxton don't support DW x DW multiplication. We have
piles of code to handle this, but apparently weren't retyping in the
immediate case.
For example,
tests/spec/arb_tessellation_shader/execution/dvec3-vs-tcs-tes
makes the simulator angry about instructions such as:
mul(8) r18<1>:D r10.0<8;8,1>:D 0x00000003:D
Just retype to W or UW. It should be safe on all platforms.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 14 Jun 2016 15:40:49 +0000 (08:40 -0700)]
anv: Add proper support for depth clamping
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 14 Jun 2016 15:15:34 +0000 (08:15 -0700)]
anv/cmd_buffer: Split emit_viewport in two
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 14 Jun 2016 00:09:37 +0000 (17:09 -0700)]
anv/cmd_buffer: Set depth/stencil extent based on the image
It used to be based on the framebuffer which isn't quite right.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 15 Jun 2016 21:30:33 +0000 (14:30 -0700)]
anv/cmd_buffer: Don't crash if push constants are provided for missing stages
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 16 Jun 2016 17:57:39 +0000 (10:57 -0700)]
anv/pipeline: Do invariance propagation on SPIR-V shaders
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 13 Jun 2016 21:41:05 +0000 (14:41 -0700)]
nir/alu_to_scalar: Respect the exact ALU operation qualifier
Just setting builder->exact isn't sufficient because that only applies to
instructions that are built with the builder but instructions created
manually and only inserted using the builder are left alone.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 13 Jun 2016 19:47:19 +0000 (12:47 -0700)]
nir: Add a pass for propagating invariant decorations
This pass is similar to propagate_invariance in the GLSL compiler. The
real "output" of this pass is that any algebraic operations which are
eventually consumed by an invariant variable get marked as "exact".
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 18 Jun 2016 19:30:36 +0000 (12:30 -0700)]
nir/algebraic: Remove imprecise flog2 optimizations
While mathematically correct, these two optimizations result in an
expression with substantially lower precision than the original. For any
positive finite floating-point value, log2(x) is well-defined and finite.
More precisely, it is in the range [-150, 150] so any sum of logarithms
log2(a) + log2(b) is also well-defined and finite as long as a and b are
both positive and finite. However, if a and b are either very small or
very large, their product may get flushed to infinity or zero causing
log2(a * b) to be nowhere close to log2(a) + log2(b).
This imprecision was causing incorrect rendering in Talos Principal because
part of its HDR rendering process involves doing 8 texture operations,
clamping the result to [0, 65000], taking a dot-product with a constant,
and then taking the log2. This is done 6 or 8 times and summed to produce
the final result which is written to a red texture. In cases where you
have a region of the screen that is very dark, it can end up getting a
result value of -inf which is not what is intended.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96425
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
Ian Romanick [Mon, 16 May 2016 19:11:57 +0000 (12:11 -0700)]
i965: Delete redundant extension enables
A nearly identical block already exists in the gen >= 6 block above.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 13 Jun 2016 20:48:47 +0000 (13:48 -0700)]
mesa: Fix incorrect "see also" comments
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Ian Romanick [Mon, 13 Jun 2016 20:45:00 +0000 (13:45 -0700)]
mesa: Silence unused parameter warning
main/pipelineobj.c: In function ‘delete_pipelineobj_cb’:
main/pipelineobj.c:110:30: warning: unused parameter ‘id’ [-Wunused-parameter]
delete_pipelineobj_cb(GLuint id, void *data, void *userData)
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Rob Clark [Tue, 7 Jun 2016 18:32:16 +0000 (14:32 -0400)]
gallium: make image_view const
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Rob Clark [Tue, 7 Jun 2016 18:29:01 +0000 (14:29 -0400)]
gallium: make constant_buffer const
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Rob Clark [Tue, 7 Jun 2016 16:49:37 +0000 (12:49 -0400)]
gallium: make shader_buffers const
Be consistent with the rest of the "set_xyz" state interfaces.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Fri, 17 Jun 2016 18:08:42 +0000 (20:08 +0200)]
radeonsi: use trapezoid distribution for tess on Fiji and Polaris
This yields a small performance improvement in Unigine Heaven.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 17 May 2016 15:12:16 +0000 (10:12 -0500)]
radeonsi/sid: add Fiji+ tesselation distribution mode
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 17 Jun 2016 09:01:30 +0000 (11:01 +0200)]
radeonsi: emit PA_SC_RASTER_CONFIG_1 only once
It is the same for all SEs.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 17 Jun 2016 08:48:53 +0000 (10:48 +0200)]
radeonsi: fix calculation of valid RB mask per SE
The old calculation treated too many RBs as disabled.
Cc: 11.0 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 17 Jun 2016 08:30:44 +0000 (10:30 +0200)]
radeonsi: raise SI_PM4_MAX_DW
The old limit, introduced in commit
afa752d3f03ac6697581ff5d324e8ac0512ef513,
was exceeded by 4 SE configurations which hit si_write_harvested_raster_configs.
Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Sun, 19 Jun 2016 01:56:11 +0000 (03:56 +0200)]
gallivm: don't use integer min/max sse intrinsics with llvm >= 3.9
Apparently, these are deprecated. There's some AutoUpgrade feature which
is supposed to promote these to cmp/select, which apparently doesn't work
with jit code. It is possible it's not actually even meant to work (see
the bug filed against llvm which couldn't provide an answer neither)
but in any case this is meant to be only temporary unless the intrinsics
are really illegal. So, just use the fallback code (which should be cmp/select,
we're actually doing cmp/sext/trunc/select, but in any case llvm 3.9 manages
to optimize this back to pmin/pmax in the end).
This addresses https://llvm.org/bugs/show_bug.cgi?id=28176
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Aaron Watry <awatry@gmail.com>
Ilia Mirkin [Sun, 19 Jun 2016 04:28:36 +0000 (00:28 -0400)]
nvc0: don't make use of push hint if there are no non-const user vbos
This makes the check match up what we do on nv50 as well - there's no
point in switching over the push path if everything's in managed
buffers. This can happen when a shader uses a vertex without an enabled
array - we end up passing it a constant attribute.
This also has the effect of "fixing" some flickering in Talos. I have no
idea why. I've stared at the push logic forwards, backwards, and
sideways. By always forcing the push path (which is slow), the
flickering also goes away, but other rendering is still wrong
(specifically draw 383068 as identified in the bug). However by not
switching over to the push path, draw 383068 is correct.
Note that other flickering remains in Talos, like the red/green
walls/floors. This takes care of the shadow flickering though.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90513
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sat, 18 Jun 2016 19:22:09 +0000 (15:22 -0400)]
gk104/ir: fix tex use generation to be more careful about eliding uses
If we have a loop, instructions before the tex might be added as tex
uses, and those may in fact dominate all other uses of the tex results.
This however doesn't mean that we don't need a texbar after the tex.
Only check if uses dominate each other they are dominated by the tex.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96565
Fixes: 7752bbc44 (gk104/ir: simplify and fool-proof texbar algorithm)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sun, 12 Jun 2016 20:05:31 +0000 (16:05 -0400)]
nv50: add support for GL_EXT_window_rectangles
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 12 Jun 2016 04:46:18 +0000 (00:46 -0400)]
nvc0: add support for GL_EXT_window_rectangles
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sat, 11 Jun 2016 20:52:17 +0000 (16:52 -0400)]
st/mesa: add support for GL_EXT_window_rectangles
Make sure to pass the requisite information in draws, blits, and clears
that work on the context's draw buffer.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Sat, 11 Jun 2016 19:26:45 +0000 (15:26 -0400)]
gallium: add PIPE_CAP_MAX_WINDOW_RECTANGLES to all drivers
This says how many window rectangles are supported by the
implementation, although it may not exceed PIPE_MAX_WINDOW_RECTANGLES.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Ilia Mirkin [Sat, 11 Jun 2016 15:35:01 +0000 (11:35 -0400)]
gallium: add API for setting window rectangles
Window rectangles apply to all framebuffer operations, either in
inclusive or exclusive mode. They may also be specified as part of a
blit operation.
In exclusive mode, any fragment inside any of the specified rectangles
will be discarded.
In inclusive mode, any fragment outside every rectangle will be
discarded.
The no-op state is to have 0 rectangles in exclusive mode.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Fri, 10 Jun 2016 02:50:43 +0000 (22:50 -0400)]
mesa: add GL_EXT_window_rectangles state storage/retrieval functionality
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Ilia Mirkin [Fri, 10 Jun 2016 02:10:10 +0000 (22:10 -0400)]
glapi: add GL_EXT_window_rectangles entrypoints
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Samuel Pitoiset [Wed, 15 Jun 2016 14:14:39 +0000 (16:14 +0200)]
nv50/ir: add missing strings for some recent sysvals
This is pretty useful for debugging purposes and those should
not be omitted.
Fixes: 517a93b3 ("nvc0: add ARB_shader_draw_parameters support")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Bruce Cherniak [Fri, 17 Jun 2016 17:14:54 +0000 (12:14 -0500)]
swr: Update screen->context pointer with multiple contexts.
A pipe pointer in the screen allows for access to current device context
in flush_frontbuffer and resource_destroy. This wasn't tracking current
context in multi-context situations.
v2: More caffeine. Corrected compare, removed unnecessary set of
screen-pipe in create_context, and added a few comments.
Brian Paul [Wed, 15 Jun 2016 16:42:34 +0000 (10:42 -0600)]
scons: put the generated git_sha1.h file in top-level src/ directory
To match what's done in the automake build.
v2: Use git rev-parse to get a 10-character hash ID
Fix Python imports
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Tim Rowley [Thu, 16 Jun 2016 19:56:39 +0000 (14:56 -0500)]
swr: switch from overriding -march to selecting features
Acked-by: Chuck Atkins <chuck.atkins@kitware.com>
Tested-by: Chuck Atkins <chuck.atkins@kitware.com>
Timothy Arceri [Fri, 17 Jun 2016 05:12:38 +0000 (15:12 +1000)]
mesa: remove remaining tabs in api_validate.c
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Samuel Iglesias Gonsálvez [Mon, 13 Jun 2016 06:29:53 +0000 (08:29 +0200)]
i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT
From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region
Restrictions, page 844:
"When source or destination datatype is 64b or operation is integer DWord
multiply, indirect addressing must not be used."
v2:
- Fix it for Broxton too.
v3:
- Simplify code by using subscript() and not creating a new num_components
variable (Kenneth).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>