Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 06:57:42 +0000 (07:57 +0100)]
forgot to mask off data being written within element
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 05:46:27 +0000 (06:46 +0100)]
add debug printfs
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 03:27:32 +0000 (04:27 +0100)]
add max elwidth resolver on add operation
result now respects the element width of the 2 source operands
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 03:16:12 +0000 (04:16 +0100)]
add to_elwidth function, not complete: needs to use source elwidths
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 03:12:39 +0000 (04:12 +0100)]
sign/zero-extend result as well
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 03:09:43 +0000 (04:09 +0100)]
alter operation width based on max bitwidth, and sign/zero-extend
Luke Kenneth Casson Leighton [Fri, 26 Oct 2018 01:43:21 +0000 (02:43 +0100)]
pass in sign-extend argument for use in non-default bitwidth
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 23:57:56 +0000 (00:57 +0100)]
add variable bitwidth on read/write regs
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 09:10:50 +0000 (10:10 +0100)]
break register down in non-default elwidth case
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 08:55:46 +0000 (09:55 +0100)]
add isvec to reg_spec_t, bit of cleanup
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 08:28:33 +0000 (09:28 +0100)]
redirect DO_WRITE_FREG and READ_FREG and others
no longer adding the offset onto the register in sv_insn_t,
now to be done in sv_proc_t WRITE_REG/READ_REG, where the
element width can be examined (finally)
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 07:30:41 +0000 (08:30 +0100)]
overload READ_REG
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 06:34:17 +0000 (07:34 +0100)]
remove offset argument from predicated fn, offset now stored in reg_spec_t
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 06:28:49 +0000 (07:28 +0100)]
make reg_spec_t offset a pointer, sometimes it needs to be NULL
Luke Kenneth Casson Leighton [Thu, 25 Oct 2018 05:36:06 +0000 (06:36 +0100)]
use reg_spec_t which passes reg + offset into sv_proc_t
Luke Kenneth Casson Leighton [Wed, 24 Oct 2018 04:39:20 +0000 (05:39 +0100)]
make common function for getting bitwidth
Luke Kenneth Casson Leighton [Tue, 23 Oct 2018 05:13:53 +0000 (06:13 +0100)]
add type signed identification, add lh/sh to insn ld/store types
Luke Kenneth Casson Leighton [Tue, 23 Oct 2018 05:11:32 +0000 (06:11 +0100)]
add type store categorisation
Luke Kenneth Casson Leighton [Sun, 21 Oct 2018 08:14:21 +0000 (09:14 +0100)]
calculate src bitwidth - very time-consuming, optimise later
Luke Kenneth Casson Leighton [Sun, 21 Oct 2018 07:53:58 +0000 (08:53 +0100)]
move sv_insn_t constructor to c file
Luke Kenneth Casson Leighton [Sat, 20 Oct 2018 09:21:51 +0000 (10:21 +0100)]
shuffle to calculate actual bitwidth
Luke Kenneth Casson Leighton [Sat, 20 Oct 2018 01:13:28 +0000 (02:13 +0100)]
make sv_regbase_t public
Luke Kenneth Casson Leighton [Sat, 20 Oct 2018 01:11:09 +0000 (02:11 +0100)]
add sign-extension bitwidth macros
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 23:56:34 +0000 (00:56 +0100)]
split out sv_reg_t elwidth into separate base class
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 23:51:44 +0000 (00:51 +0100)]
fixed memory corruption due to use of auto on load_uint64, put elwidth back
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 23:51:15 +0000 (00:51 +0100)]
stop using auto in mmu.h macro, use type##_t
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 23:37:59 +0000 (00:37 +0100)]
whoops load_uint64 with auto returned sv_reg_t not uint64_t
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:46:00 +0000 (23:46 +0100)]
const& on more sv_sreg_t usage
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:44:00 +0000 (23:44 +0100)]
const sv_mmu_t functions
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:40:15 +0000 (23:40 +0100)]
stop addr++ in interactive loop
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:25:08 +0000 (23:25 +0100)]
use const& for operators in sv_reg_t
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:18:20 +0000 (23:18 +0100)]
make 2-op rv* const
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 22:11:43 +0000 (23:11 +0100)]
temporarily comment out setting of elwidth
sv_reg_t seems to be being typecast somewhere, probably to a uint64_t,
and accessing the elwidth corrupts memory
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 13:52:15 +0000 (14:52 +0100)]
redirect obtaining registers through a common function, get_intreg
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 13:44:09 +0000 (14:44 +0100)]
redirect through element width, obtain elwidth from CSR reg tables
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 12:20:59 +0000 (13:20 +0100)]
remove more get_data calls
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 12:19:58 +0000 (13:19 +0100)]
remove more get_data calls
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 12:17:51 +0000 (13:17 +0100)]
remove unneeded get_data calls
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 12:17:37 +0000 (13:17 +0100)]
add sv_mmu.h
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 11:22:53 +0000 (12:22 +0100)]
clean up sv_reg_t class
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 10:58:25 +0000 (11:58 +0100)]
use class-based sv_reg_t and sv_sreg_t
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 08:35:12 +0000 (09:35 +0100)]
bring in new version of sv_reg.h
Luke Kenneth Casson Leighton [Fri, 19 Oct 2018 08:33:27 +0000 (09:33 +0100)]
provide sv_reg_t overrides of more functions so that sv_reg_t can be a class
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:53:53 +0000 (23:53 +0100)]
put sv_mmu override class in place
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:43:38 +0000 (23:43 +0100)]
fix debug printfs
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:40:47 +0000 (23:40 +0100)]
srrl srli srai etc
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:38:55 +0000 (23:38 +0100)]
slli
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:38:33 +0000 (23:38 +0100)]
sll
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:38:06 +0000 (23:38 +0100)]
jalr, mul, rem
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:31:58 +0000 (23:31 +0100)]
fmv/mvlq/fsq
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:30:04 +0000 (23:30 +0100)]
div, fcvt
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:28:24 +0000 (23:28 +0100)]
divuw
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:27:24 +0000 (23:27 +0100)]
divu
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:26:40 +0000 (23:26 +0100)]
div
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:24:25 +0000 (23:24 +0100)]
csrs
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:23:06 +0000 (23:23 +0100)]
csrrc
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:22:07 +0000 (23:22 +0100)]
c_srli
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:21:18 +0000 (23:21 +0100)]
c_slli c_srai
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:18:51 +0000 (23:18 +0100)]
c_lui
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:17:49 +0000 (23:17 +0100)]
c_jalr
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:17:04 +0000 (23:17 +0100)]
c_jal
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:16:24 +0000 (23:16 +0100)]
c_beqz
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:15:14 +0000 (23:15 +0100)]
addi4spn
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:14:36 +0000 (23:14 +0100)]
redirect sreg_t casts through function
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:12:00 +0000 (23:12 +0100)]
typedef on sv_reg_t to reg_t (and signed variant)
still working on redirecting everything through a planned class
that can be polymorphic overloaded... eventually
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 22:11:08 +0000 (23:11 +0100)]
use unsigned long shift on sv csr setting
Luke Kenneth Casson Leighton [Thu, 18 Oct 2018 17:14:36 +0000 (18:14 +0100)]
forgot to set clroffset
Luke Kenneth Casson Leighton [Wed, 17 Oct 2018 09:56:30 +0000 (10:56 +0100)]
allow 4 CSR entries to be set at a time, on RV64
Luke Kenneth Casson Leighton [Wed, 17 Oct 2018 00:58:15 +0000 (01:58 +0100)]
minor alteration to CSRRWI SETVL / SETMVL to offset immediate by 1
allows CSRRWI to make maximum use of only 5-bit immediate
Luke Kenneth Casson Leighton [Tue, 16 Oct 2018 22:40:26 +0000 (23:40 +0100)]
shuffle CSR offsets around, offset VL and MVL by one
VL and MVL now span from 1 to XLEN rather than 0 to XLEN-1
also making room for M-Mode and S-Mode CSRs
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 11:56:24 +0000 (12:56 +0100)]
fix compiler warnings on printfs
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 11:55:38 +0000 (12:55 +0100)]
fix annoying printf warning on fp compiles
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 09:26:14 +0000 (10:26 +0100)]
whoops deref null pointer
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 08:58:22 +0000 (09:58 +0100)]
c_beqz sv operational
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 07:56:51 +0000 (08:56 +0100)]
put RVC_SP at back of cintpatterns list
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 06:49:26 +0000 (07:49 +0100)]
add rvc_sp redirection/offset overload
also found weird bug where RVC_FRS1/2 were not being detected,
how it was not found earlier is a mystery, code should not
have compiled!
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 05:52:02 +0000 (06:52 +0100)]
need to check whether SP (reg 2) is used, without redirection
Luke Kenneth Casson Leighton [Mon, 15 Oct 2018 05:43:24 +0000 (06:43 +0100)]
add overload/redirection for WRITE_REG
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 21:29:34 +0000 (22:29 +0100)]
move design to separate document
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 21:29:22 +0000 (22:29 +0100)]
drop all lui from restriction on parallelism
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 12:30:48 +0000 (13:30 +0100)]
disable jal in sv
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:41:04 +0000 (06:41 +0100)]
rv_xxx convert c_xxx
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:31:27 +0000 (06:31 +0100)]
rv_add in lh/sh
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:28:16 +0000 (06:28 +0100)]
rv_add in store
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:26:45 +0000 (06:26 +0100)]
blt and use of rv_add
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:23:38 +0000 (06:23 +0100)]
add rv_ge
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:21:42 +0000 (06:21 +0100)]
add rv_eq and rv_ne
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:20:05 +0000 (06:20 +0100)]
add rv_eq and rv_ne
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:16:54 +0000 (06:16 +0100)]
add rv_gt headers
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:16:03 +0000 (06:16 +0100)]
add rv_sr
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:06:43 +0000 (06:06 +0100)]
add shiftright
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 05:02:59 +0000 (06:02 +0100)]
add shiftleft and lessthan
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:50:24 +0000 (05:50 +0100)]
missed a mul
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:49:05 +0000 (05:49 +0100)]
replace % operator with rv_rem
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:46:37 +0000 (05:46 +0100)]
replace ^ operator with rv_xor
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:45:40 +0000 (05:45 +0100)]
replace | operator with rv_or
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:44:36 +0000 (05:44 +0100)]
replace & operator with rv_and
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:42:39 +0000 (05:42 +0100)]
replace operator * with rv_mul
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:35:03 +0000 (05:35 +0100)]
add rv_div (signed and unsigned) to replace operator /
Luke Kenneth Casson Leighton [Sun, 14 Oct 2018 04:24:18 +0000 (05:24 +0100)]
redirect subtract through rv_sub