yosys.git
5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Thu, 15 Aug 2019 19:19:47 +0000 (12:19 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoffH -> ffFJKG
Eddie Hung [Thu, 15 Aug 2019 19:19:34 +0000 (12:19 -0700)]
ffH -> ffFJKG

5 years agoFixes for reverting SigSpec helper functions
Eddie Hung [Wed, 14 Aug 2019 17:22:33 +0000 (10:22 -0700)]
Fixes for reverting SigSpec helper functions

5 years agoPerform C -> PCIN optimisation after pattern matcher
Eddie Hung [Wed, 14 Aug 2019 00:11:35 +0000 (17:11 -0700)]
Perform C -> PCIN optimisation after pattern matcher

5 years agoRevert changes to RTLIL::SigSpec methods
Eddie Hung [Wed, 14 Aug 2019 00:09:28 +0000 (17:09 -0700)]
Revert changes to RTLIL::SigSpec methods

5 years agoOnly swap ports if $mul and not $__mul
Eddie Hung [Tue, 13 Aug 2019 23:52:15 +0000 (16:52 -0700)]
Only swap ports if $mul and not $__mul

5 years agoAdd assign PCOUT = P to DSP48E1
Eddie Hung [Tue, 13 Aug 2019 19:19:26 +0000 (12:19 -0700)]
Add assign PCOUT = P to DSP48E1

5 years agoRename to XilinxDspPass
Eddie Hung [Tue, 13 Aug 2019 17:23:07 +0000 (10:23 -0700)]
Rename to XilinxDspPass

5 years agoAdd DSP_A_MAXWIDTH_PARTIAL, refactor
Eddie Hung [Tue, 13 Aug 2019 17:21:24 +0000 (10:21 -0700)]
Add DSP_A_MAXWIDTH_PARTIAL, refactor

5 years agoxilinx: Rework labels for faster Verilator testing
David Shah [Tue, 13 Aug 2019 09:29:42 +0000 (10:29 +0100)]
xilinx: Rework labels for faster Verilator testing

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Mon, 12 Aug 2019 18:32:10 +0000 (11:32 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoMerge pull request #1152 from 1138-4EB/feat-docker
Serge Bazanski [Mon, 12 Aug 2019 13:09:25 +0000 (15:09 +0200)]
Merge pull request #1152 from 1138-4EB/feat-docker

Dockerfile

5 years agoMerge pull request #1277 from YosysHQ/eddie/fix_1262
Eddie Hung [Mon, 12 Aug 2019 05:10:17 +0000 (22:10 -0700)]
Merge pull request #1277 from YosysHQ/eddie/fix_1262

opt_expr -fine to now trim LSBs of $alu cells too

5 years agoMerge remote-tracking branch 'origin/master' into eddie/fix_1262
Eddie Hung [Mon, 12 Aug 2019 04:13:40 +0000 (21:13 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/fix_1262

5 years agoMerge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder
Eddie Hung [Sat, 10 Aug 2019 21:18:16 +0000 (14:18 -0700)]
Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder

Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agoWrong way around
Eddie Hung [Sat, 10 Aug 2019 18:55:00 +0000 (11:55 -0700)]
Wrong way around

5 years agoRevert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
David Shah [Sat, 10 Aug 2019 16:14:48 +0000 (17:14 +0100)]
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agocover_list -> cover as per @cliffordwolf
Eddie Hung [Sat, 10 Aug 2019 15:26:41 +0000 (08:26 -0700)]
cover_list -> cover as per @cliffordwolf

5 years agoMerge pull request #1258 from YosysHQ/eddie/cleanup
Clifford Wolf [Sat, 10 Aug 2019 07:52:14 +0000 (09:52 +0200)]
Merge pull request #1258 from YosysHQ/eddie/cleanup

Cleanup a few barnacles across codebase

5 years agoMerge pull request #1261 from YosysHQ/clifford/verific_init
Clifford Wolf [Sat, 10 Aug 2019 07:47:25 +0000 (09:47 +0200)]
Merge pull request #1261 from YosysHQ/clifford/verific_init

Automatically prune init attributes in verific front-end

5 years agoMerge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
Clifford Wolf [Sat, 10 Aug 2019 07:47:10 +0000 (09:47 +0200)]
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell

FIRRTL error on unsupported cell

5 years agoMerge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
Clifford Wolf [Sat, 10 Aug 2019 07:46:46 +0000 (09:46 +0200)]
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc

Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1272 from mmicko/travis_fix
Clifford Wolf [Sat, 10 Aug 2019 07:45:26 +0000 (09:45 +0200)]
Merge pull request #1272 from mmicko/travis_fix

Propagate parameters for Travis build

5 years agoMerge pull request #1274 from YosysHQ/eddie/fix_1271
Clifford Wolf [Sat, 10 Aug 2019 07:45:06 +0000 (09:45 +0200)]
Merge pull request #1274 from YosysHQ/eddie/fix_1271

Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoMerge pull request #1276 from YosysHQ/clifford/fix1273
Clifford Wolf [Sat, 10 Aug 2019 07:38:22 +0000 (09:38 +0200)]
Merge pull request #1276 from YosysHQ/clifford/fix1273

Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib

5 years agoCheck nusers of DSP output, not whole flop
Eddie Hung [Sat, 10 Aug 2019 00:35:13 +0000 (17:35 -0700)]
Check nusers of DSP output, not whole flop

5 years agoImprove ice40_dsp for non-fully-32-bit adders
Eddie Hung [Sat, 10 Aug 2019 00:23:12 +0000 (17:23 -0700)]
Improve ice40_dsp for non-fully-32-bit adders

5 years agoAdd wreduce to synth_ice40 -dsp as well
Eddie Hung [Sat, 10 Aug 2019 00:05:56 +0000 (17:05 -0700)]
Add wreduce to synth_ice40 -dsp as well

5 years agoAnother filter -> if
Eddie Hung [Fri, 9 Aug 2019 23:23:32 +0000 (16:23 -0700)]
Another filter -> if

5 years agoCleanup
Eddie Hung [Fri, 9 Aug 2019 22:47:40 +0000 (15:47 -0700)]
Cleanup

5 years agoPack partial-product adder DSP48E1 packing
Eddie Hung [Fri, 9 Aug 2019 22:19:33 +0000 (15:19 -0700)]
Pack partial-product adder DSP48E1 packing

5 years agoFix check
Eddie Hung [Fri, 9 Aug 2019 21:27:08 +0000 (14:27 -0700)]
Fix check

5 years agoRevert "Fix typo"
Eddie Hung [Fri, 9 Aug 2019 21:14:28 +0000 (14:14 -0700)]
Revert "Fix typo"

This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c.

5 years agoGrammar
Eddie Hung [Fri, 9 Aug 2019 19:43:21 +0000 (12:43 -0700)]
Grammar

5 years agoReformat so it shows up/looks nice when "help $alu" and "help $alu+"
Eddie Hung [Fri, 9 Aug 2019 19:33:39 +0000 (12:33 -0700)]
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

5 years agoSeparate $alu handling
Eddie Hung [Fri, 9 Aug 2019 19:13:32 +0000 (12:13 -0700)]
Separate $alu handling

5 years agoAdd $alu tests
Eddie Hung [Fri, 9 Aug 2019 19:13:17 +0000 (12:13 -0700)]
Add $alu tests

5 years agoopt_expr -fine to trim LSBs of $alu too
Eddie Hung [Fri, 9 Aug 2019 17:32:12 +0000 (10:32 -0700)]
opt_expr -fine to trim LSBs of $alu too

5 years agoAdd alumacc versions of opt_expr tests
Eddie Hung [Fri, 9 Aug 2019 17:30:53 +0000 (10:30 -0700)]
Add alumacc versions of opt_expr tests

5 years agoAdd new $alu test, remove wreduce
Eddie Hung [Fri, 9 Aug 2019 17:22:06 +0000 (10:22 -0700)]
Add new $alu test, remove wreduce

5 years agoDisable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes...
Clifford Wolf [Fri, 9 Aug 2019 17:17:23 +0000 (19:17 +0200)]
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCleanup some more
Eddie Hung [Fri, 9 Aug 2019 17:13:49 +0000 (10:13 -0700)]
Cleanup some more

5 years agoMerge pull request #1267 from whitequark/proc_prune-fix-1243
whitequark [Fri, 9 Aug 2019 17:10:46 +0000 (17:10 +0000)]
Merge pull request #1267 from whitequark/proc_prune-fix-1243

proc_prune: fix handling of exactly identical assigns

5 years agoSimplify opt_expr tests using equiv_opt
Eddie Hung [Fri, 9 Aug 2019 17:08:17 +0000 (10:08 -0700)]
Simplify opt_expr tests using equiv_opt

5 years agoA bit more on where $lcu comes from
Eddie Hung [Fri, 9 Aug 2019 16:50:47 +0000 (09:50 -0700)]
A bit more on where $lcu comes from

5 years agoAdd more comments
Eddie Hung [Fri, 9 Aug 2019 16:48:17 +0000 (09:48 -0700)]
Add more comments

5 years agoAdd __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
Eddie Hung [Fri, 9 Aug 2019 16:17:35 +0000 (09:17 -0700)]
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoABC requires it like this
Miodrag Milanovic [Fri, 9 Aug 2019 06:54:17 +0000 (08:54 +0200)]
ABC requires it like this

5 years agoPropagate parameters for Travis build
Miodrag Milanovic [Fri, 9 Aug 2019 06:06:14 +0000 (08:06 +0200)]
Propagate parameters for Travis build

5 years agoRemove muxY and ffY for now
Eddie Hung [Thu, 8 Aug 2019 23:33:37 +0000 (16:33 -0700)]
Remove muxY and ffY for now

5 years agoRemove signed from ports in +/xilinx/dsp_map.v
Eddie Hung [Thu, 8 Aug 2019 23:33:20 +0000 (16:33 -0700)]
Remove signed from ports in +/xilinx/dsp_map.v

5 years agoRework ice40_dsp to map to SB_MAC16 earlier, and check before packing
Eddie Hung [Thu, 8 Aug 2019 19:56:05 +0000 (12:56 -0700)]
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

5 years agoCombine techmap calls
Eddie Hung [Thu, 8 Aug 2019 17:55:48 +0000 (10:55 -0700)]
Combine techmap calls

5 years agoOnly pack registers if {A,B,P}REG = 0, do not pack $dffe
Eddie Hung [Thu, 8 Aug 2019 17:51:19 +0000 (10:51 -0700)]
Only pack registers if {A,B,P}REG = 0, do not pack $dffe

5 years agoMove xilinx_dsp to before alumacc
Eddie Hung [Thu, 8 Aug 2019 17:45:56 +0000 (10:45 -0700)]
Move xilinx_dsp to before alumacc

5 years agoDisable $dffe
Eddie Hung [Thu, 8 Aug 2019 17:44:49 +0000 (10:44 -0700)]
Disable $dffe

5 years agoINMODE is 5 bits
Eddie Hung [Thu, 8 Aug 2019 17:44:35 +0000 (10:44 -0700)]
INMODE is 5 bits

5 years agoFix copy-pasta typo
Eddie Hung [Thu, 8 Aug 2019 17:44:26 +0000 (10:44 -0700)]
Fix copy-pasta typo

5 years agoAdd a few comments to document $alu and $lcu
Eddie Hung [Thu, 8 Aug 2019 17:05:28 +0000 (10:05 -0700)]
Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1264 from YosysHQ/eddie/fix_1254
Eddie Hung [Thu, 8 Aug 2019 14:58:33 +0000 (07:58 -0700)]
Merge pull request #1264 from YosysHQ/eddie/fix_1254

opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)

5 years agoMerge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Eddie Hung [Thu, 8 Aug 2019 14:58:11 +0000 (07:58 -0700)]
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder

Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER

5 years agoecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx
David Shah [Thu, 8 Aug 2019 14:18:59 +0000 (15:18 +0100)]
ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx

Signed-off-by: David Shah <dave@ds0.me>
5 years agoecp5: Bring up to date with mul2dsp changes
David Shah [Thu, 8 Aug 2019 14:14:09 +0000 (15:14 +0100)]
ecp5: Bring up to date with mul2dsp changes

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
David Shah [Thu, 8 Aug 2019 10:40:09 +0000 (11:40 +0100)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoDSP48E1 sim model: add SIMD tests
David Shah [Thu, 8 Aug 2019 10:39:35 +0000 (11:39 +0100)]
DSP48E1 sim model: add SIMD tests

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 model: test CE inputs
David Shah [Thu, 8 Aug 2019 10:32:43 +0000 (11:32 +0100)]
DSP48E1 model: test CE inputs

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: fix seq tests and add preadder tests
David Shah [Thu, 8 Aug 2019 10:18:37 +0000 (11:18 +0100)]
DSP48E1 sim model: fix seq tests and add preadder tests

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: seq test working
David Shah [Thu, 8 Aug 2019 09:52:04 +0000 (10:52 +0100)]
DSP48E1 sim model: seq test working

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: Comb, no pre-adder, mode working
David Shah [Thu, 8 Aug 2019 09:26:40 +0000 (10:26 +0100)]
DSP48E1 sim model: Comb, no pre-adder, mode working

Signed-off-by: David Shah <dave@ds0.me>
5 years ago[wip] sim model testing
David Shah [Thu, 8 Aug 2019 09:05:11 +0000 (10:05 +0100)]
[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>
5 years ago[wip] sim model testing
David Shah [Thu, 8 Aug 2019 08:31:34 +0000 (09:31 +0100)]
[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>
5 years agoproc_prune: fix handling of exactly identical assigns.
whitequark [Thu, 8 Aug 2019 05:28:01 +0000 (05:28 +0000)]
proc_prune: fix handling of exactly identical assigns.

Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.

5 years agoRemove dump call
Eddie Hung [Thu, 8 Aug 2019 04:36:02 +0000 (21:36 -0700)]
Remove dump call

5 years agoMove tests/various/opt* into tests/opt/
Eddie Hung [Thu, 8 Aug 2019 04:35:48 +0000 (21:35 -0700)]
Move tests/various/opt* into tests/opt/

5 years agoRemove ice40_unlut call, simply do equiv_opt on synth_ice40
Eddie Hung [Thu, 8 Aug 2019 04:33:56 +0000 (21:33 -0700)]
Remove ice40_unlut call, simply do equiv_opt on synth_ice40

5 years agoAdd testcase from removed opt_ff.{v,ys}
Eddie Hung [Thu, 8 Aug 2019 04:31:32 +0000 (21:31 -0700)]
Add testcase from removed opt_ff.{v,ys}

5 years agoRemove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
Eddie Hung [Wed, 7 Aug 2019 23:48:38 +0000 (16:48 -0700)]
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run

5 years agoAllow whitebox modules to be overwritten
Eddie Hung [Wed, 7 Aug 2019 23:40:24 +0000 (16:40 -0700)]
Allow whitebox modules to be overwritten

5 years agoUpdate CHANGELOG
Eddie Hung [Wed, 7 Aug 2019 23:33:46 +0000 (16:33 -0700)]
Update CHANGELOG

5 years agoAdd ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
Eddie Hung [Wed, 7 Aug 2019 23:27:24 +0000 (16:27 -0700)]
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER

5 years agoAdd test
Eddie Hung [Wed, 7 Aug 2019 23:27:07 +0000 (16:27 -0700)]
Add test

5 years agoRemove ice40_unlut
Eddie Hung [Wed, 7 Aug 2019 21:52:56 +0000 (14:52 -0700)]
Remove ice40_unlut

5 years agoWrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
Eddie Hung [Wed, 7 Aug 2019 21:50:59 +0000 (14:50 -0700)]
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

5 years agoFix compile error
Eddie Hung [Wed, 7 Aug 2019 21:31:55 +0000 (14:31 -0700)]
Fix compile error

5 years agoRun "opt_expr -fine" instead of "wreduce" due to #1213
Eddie Hung [Wed, 7 Aug 2019 20:59:07 +0000 (13:59 -0700)]
Run "opt_expr -fine" instead of "wreduce" due to #1213

5 years agoDo not SigSpec::extract() beyond bounds
Eddie Hung [Wed, 7 Aug 2019 20:58:26 +0000 (13:58 -0700)]
Do not SigSpec::extract() beyond bounds

5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Wed, 7 Aug 2019 20:44:08 +0000 (13:44 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoopt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
Eddie Hung [Wed, 7 Aug 2019 20:12:28 +0000 (13:12 -0700)]
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)

5 years agoDo not pack registers if (* keep *)
Eddie Hung [Wed, 7 Aug 2019 19:57:10 +0000 (12:57 -0700)]
Do not pack registers if (* keep *)

5 years agoMerge pull request #1248 from YosysHQ/eddie/abc9_speedup
Eddie Hung [Wed, 7 Aug 2019 19:25:26 +0000 (12:25 -0700)]
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup

abc9: speedup by using using "clean" more efficiently

5 years agosubstr() -> compare()
Eddie Hung [Wed, 7 Aug 2019 19:20:08 +0000 (12:20 -0700)]
substr() -> compare()

5 years agoRTLIL::S{0,1} -> State::S{0,1} for headers
Eddie Hung [Wed, 7 Aug 2019 18:14:03 +0000 (11:14 -0700)]
RTLIL::S{0,1} -> State::S{0,1} for headers

5 years agoRTLIL::S{0,1} -> State::S{0,1}
Eddie Hung [Wed, 7 Aug 2019 18:12:38 +0000 (11:12 -0700)]
RTLIL::S{0,1} -> State::S{0,1}

5 years agoMerge remote-tracking branch 'origin/master' into eddie/cleanup
Eddie Hung [Wed, 7 Aug 2019 18:11:50 +0000 (11:11 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/cleanup

5 years agoRemove std:: namespace
Eddie Hung [Wed, 7 Aug 2019 18:11:14 +0000 (11:11 -0700)]
Remove std:: namespace

5 years ago'make clean' to not remove anything abc
Eddie Hung [Wed, 7 Aug 2019 18:10:18 +0000 (11:10 -0700)]
'make clean' to not remove anything abc

5 years agostoi -> atoi
Eddie Hung [Wed, 7 Aug 2019 18:09:17 +0000 (11:09 -0700)]
stoi -> atoi

5 years agodockerfile: use 'python:3-slim-buster' base image
1138-4EB [Wed, 7 Aug 2019 12:24:09 +0000 (14:24 +0200)]
dockerfile: use 'python:3-slim-buster' base image

5 years agodockerfile: use PREFIX instead of cp
1138-4EB [Wed, 7 Aug 2019 03:37:00 +0000 (05:37 +0200)]
dockerfile: use PREFIX instead of cp

5 years agoMerge branch 'master' into firrtl_err_on_unsupported_cell
Jim Lawson [Wed, 7 Aug 2019 17:14:45 +0000 (10:14 -0700)]
Merge branch 'master' into firrtl_err_on_unsupported_cell

# Conflicts:
# backends/firrtl/firrtl.cc