bugzilla-daemon [Tue, 12 May 2020 12:14:24 +0000 (12:14 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:13:06 +0000 (12:13 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:12:39 +0000 (12:12 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:12:39 +0000 (12:12 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:11:22 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:11:08 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
Luke Kenneth Casson Leighton [Tue, 12 May 2020 10:45:22 +0000 (11:45 +0100)]
[libre-riscv-dev] daily kan-ban update 12may2020
Luke Kenneth Casson Leighton [Tue, 12 May 2020 10:06:52 +0000 (11:06 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Tue, 12 May 2020 10:03:52 +0000 (10:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Tue, 12 May 2020 09:24:33 +0000 (09:24 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Tue, 12 May 2020 09:09:33 +0000 (10:09 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Lauri Kasanen [Tue, 12 May 2020 08:50:42 +0000 (11:50 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:33:52 +0000 (09:33 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:23:52 +0000 (09:23 +0100)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Lauri Kasanen [Tue, 12 May 2020 08:23:14 +0000 (11:23 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:11:04 +0000 (09:11 +0100)]
Re: [libre-riscv-dev] learning from a failed business
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:07:09 +0000 (09:07 +0100)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:56:15 +0000 (08:56 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:50:09 +0000 (08:50 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Jacob Lifshay [Tue, 12 May 2020 07:46:22 +0000 (00:46 -0700)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Jacob Lifshay [Tue, 12 May 2020 07:40:03 +0000 (00:40 -0700)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:36:13 +0000 (08:36 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:31:17 +0000 (08:31 +0100)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Jacob Lifshay [Tue, 12 May 2020 07:24:35 +0000 (00:24 -0700)]
[libre-riscv-dev] little-endian only power cores and spec compliance
Jacob Lifshay [Tue, 12 May 2020 07:06:44 +0000 (00:06 -0700)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Lauri Kasanen [Tue, 12 May 2020 06:44:13 +0000 (09:44 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Jacob Lifshay [Tue, 12 May 2020 06:27:38 +0000 (23:27 -0700)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Lauri Kasanen [Tue, 12 May 2020 06:01:44 +0000 (09:01 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Jacob Lifshay [Tue, 12 May 2020 04:15:53 +0000 (21:15 -0700)]
[libre-riscv-dev] learning from a failed business
Luke Kenneth Casson Leighton [Tue, 12 May 2020 03:29:27 +0000 (04:29 +0100)]
Re: [libre-riscv-dev] Power memory fences and icache handling
Jacob Lifshay [Tue, 12 May 2020 01:42:07 +0000 (18:42 -0700)]
[libre-riscv-dev] Power memory fences and icache handling
Luke Kenneth Casson Leighton [Tue, 12 May 2020 01:25:43 +0000 (02:25 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Tue, 12 May 2020 00:56:22 +0000 (20:56 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Tue, 12 May 2020 00:53:27 +0000 (01:53 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Mon, 11 May 2020 23:02:56 +0000 (19:02 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:53:11 +0000 (23:53 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:34:41 +0000 (23:34 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Mon, 11 May 2020 22:27:49 +0000 (18:27 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Mon, 11 May 2020 22:23:54 +0000 (18:23 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:23:18 +0000 (23:23 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:19:59 +0000 (23:19 +0100)]
[libre-riscv-dev] ppc-dev linux patch support for microwatt!
bugzilla-daemon [Mon, 11 May 2020 21:20:50 +0000 (21:20 +0000)]
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
bugzilla-daemon [Mon, 11 May 2020 21:19:17 +0000 (21:19 +0000)]
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:37:03 +0000 (19:37 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Yehowshua [Mon, 11 May 2020 18:31:05 +0000 (14:31 -0400)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:28:07 +0000 (19:28 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:25:50 +0000 (19:25 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
bugzilla-daemon [Mon, 11 May 2020 18:23:29 +0000 (18:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 18:15:26 +0000 (18:15 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 17:52:59 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
Lauri Kasanen [Mon, 11 May 2020 17:34:21 +0000 (20:34 +0300)]
[libre-riscv-dev] PowerISA 3.1 (Power10) spec released
bugzilla-daemon [Mon, 11 May 2020 16:13:53 +0000 (16:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 16:13:04 +0000 (16:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 16:03:25 +0000 (16:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 15:51:36 +0000 (15:51 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 14:31:39 +0000 (14:31 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Michael Nolan [Mon, 11 May 2020 13:32:40 +0000 (09:32 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Mon, 11 May 2020 13:23:24 +0000 (13:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 12:43:28 +0000 (12:43 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Mon, 11 May 2020 12:28:35 +0000 (12:28 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Mon, 11 May 2020 12:28:05 +0000 (12:28 +0000)]
[libre-riscv-dev] [Bug 307] New: look at installing a kan-ban board on top of bugzilla
Luke Kenneth Casson Leighton [Mon, 11 May 2020 12:26:42 +0000 (13:26 +0100)]
[libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Mon, 11 May 2020 10:30:59 +0000 (10:30 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 01:11:55 +0000 (01:11 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 00:04:15 +0000 (00:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:42:01 +0000 (23:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:15:34 +0000 (23:15 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:11:51 +0000 (23:11 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:06:51 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:03:16 +0000 (23:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 13:46:03 +0000 (13:46 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 13:01:02 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:36:43 +0000 (11:36 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:36:20 +0000 (11:36 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Sun, 10 May 2020 11:34:24 +0000 (11:34 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:33:38 +0000 (11:33 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:33:23 +0000 (11:33 +0000)]
[libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 04:30:53 +0000 (04:30 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 04:25:04 +0000 (04:25 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:42:03 +0000 (21:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:35:01 +0000 (21:35 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:18:30 +0000 (21:18 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Sat, 9 May 2020 19:42:24 +0000 (20:42 +0100)]
Re: [libre-riscv-dev] Handling Interrupts
bugzilla-daemon [Sat, 9 May 2020 19:12:28 +0000 (19:12 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 19:08:05 +0000 (19:08 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 18:23:58 +0000 (18:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Yehowshua [Sat, 9 May 2020 17:23:58 +0000 (13:23 -0400)]
[libre-riscv-dev] Handling Interrupts
Yehowshua [Sat, 9 May 2020 14:39:10 +0000 (10:39 -0400)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Yehowshua [Sat, 9 May 2020 14:33:10 +0000 (10:33 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
bugzilla-daemon [Sat, 9 May 2020 14:06:38 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 14:04:31 +0000 (14:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:48:32 +0000 (13:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:45:26 +0000 (13:45 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:41:48 +0000 (13:41 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:37:42 +0000 (13:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:13:41 +0000 (13:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:08:52 +0000 (14:08 +0100)]
[libre-riscv-dev] insights about the selection of the design and architecture
Luke Kenneth Casson Leighton [Sat, 9 May 2020 11:33:05 +0000 (12:33 +0100)]
[libre-riscv-dev] daily kan-ban update 09may2020
Luke Kenneth Casson Leighton [Sat, 9 May 2020 10:02:13 +0000 (11:02 +0100)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Luke Kenneth Casson Leighton [Sat, 9 May 2020 09:59:13 +0000 (10:59 +0100)]
[libre-riscv-dev] pinmux to generate interfaces (with no pinmux)
projects / libre-riscv-dev.git / log