util: m5ops, optional extra build flags

This increases compilation control for users. Main use case is building
m5ops as part of an image distribution. Specifying a different sysroot
or dynamic linker may be required when the cross toolchain is built as
part of the process.

Change-Id: Icbd3faa92ea6e084fc4a9b2db83129bce73faf21
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38416
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Use the right register type when initializing x86 kvm processes.

Functionally this doesn't matter, since no bitfields are used in the
type and it devolves into just being a uint64_t, but we should use CR8
and not CR4 when initializing the CR8 register.

Change-Id: Ifc7dc9072d552f7010afce9115427c8ed624ebb9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38535
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

x86: Set the effective base of the TSS when initializing a process.

For some segments, there are two base registers. One is the
architecturally visible base, and the other is the effective base used
when actually referencing memory relative to that segment. The process
initialization code was setting the architecturally visible base,
presumably because that's the value used by KVM, but was setting the
effective base to zero.

Change-Id: I06e079f24fa63f0051268437bf00c14578f62612
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38488
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Some small style fixes in arch/x86/process.hh.

Moved two single line functions to be all on one line, and added some
consts.

Change-Id: Iecfa3a9c2bde69ce2f26e9531864a7cb92b0a1df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,sim: Remove special handling for KVM in the clone syscall.

When a gem5 op is triggered using a KVM MMIO exit event, the PC has
already been advanced beyond the offending instruction. Normally when
a system call or gem5 op is triggered, the PC has not advanced because
the instruction hasn't actually finished executing. This means that if
a gem5 op, and by extension a system call in SE mode, want to advance
the PC to the instruction after the gem5 op, they have to check whether
they were triggered from KVM.

To avoid having to special case these sorts of situations (currently
only in the clone system call), we can have the code which dispatches to
gem5 ops from KVM adjust the next PC so that it points to what the
current PC is. That way the PC can be advanced unconditionally, and will
point to the instruction after the one that triggered the call.

To be fully consistent, we would also need to adjust the current PC.
That would be non-trivial since we'd have to figure out where the
current instruction started, and that may not even be possible to
unambiguously determine given x86's instruction structure. Then we would
also need to restore the original PC to avoid confusing KVM.

Change-Id: I9ef90b2df8e27334dedc25c59eb45757f7220eea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38486
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove full system checks from some pseudo insts.

These pseudo insts are less useful outside of full system, but they
should all still work. Removing this check makes it possible to, for
instance, test them in syscall emulation mode, and removes another
difference between the two styles of simulation.

Change-Id: Ia7d29bfc6f7c5c236045d151930fc171a6966799
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38485
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix const copy of addr range in AbstractController

Clang 10 throws the following error:
  loop variable 'addr_range' of type 'const AddrRange' creates a
  copy from type 'const AddrRange' [-Werror,-Wrange-loop-construct]

  note: use reference type 'const AddrRange &' to prevent copying

Issue introduced by c7fabb979c09864ab47ae848381d6797b45a4cc6.

Change-Id: I43e8d613eb5069d5ce9cb12ddec18cba0a3847f6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38495
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Align the Substream naming in Request

Change-Id: Iac6a18d8872c7df4ade8ecf8914fa807cc3584e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38457
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Change assert to use flag test functions in Request

Change-Id: Id999d39959557196877be9b6469be332391c7dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38456
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add missing flag test functions to Request

Change-Id: I800c45c855332a2dd1ec5f31b135db62181e5204
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38455
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Update stats for LTAGE bpred

Updated stats in ltage.hh and ltage.cc to use new style stats.

Change-Id: I5f676381fce6f3a0b6abc6044577540e561dcd7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36335
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Number of TLBs equal to number of CUs

The n_cu variable in GPUTLBConifig.py did not take
the number of CUs into consideration and instead
calculated the number of TLBs using cu_per_sa,
sa_per_complex, num_gpu_complexes. Thus changing
the number of cus (n_cus) and none of the other flags
resulted in a  segmentation fault since the required
TLBs were not being instantiated

Change-Id: I569a4e6dc7db9b7a81aeede5ac68aacc0f400a5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32035
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm,kvm: missed rename of MISCREG_HYP in kvm/armv8_cpu.cc

A recent checkin changed the names of some of the MISCREGs.
One of them was missed and wont compile. This fixes to the new name.

Change-Id: I746f9dea44bc50819a0d30f62dcc3a46380f80c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38358
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Update stats for tage_sc_l to new style stats

Updated tage_sc_l.hh and tage_sc_l.cc to use new style stats.

Change-Id: If172c95bb728c7c3748269469781212ef1da6f32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36336
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Trivikram Reddy <tvreddy@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a simple junit test for the gem5 ops java wrapper.

If possible, this gets built into the jar which also holds the wrapper.
It can be run on its own through its own main function, or through the
junit mechanism directly.

Change-Id: Iaec7f6deb26bbad75da027c71edca50ef25697cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28181
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

util: Rework some checks in the m5 util scons to use Configure().

This is the official scons way to check for things on the system. This
adds two custom checks, one for java packages and one for pkg-config
packages. This change also adds a check for the org.junit java package
which is/will be used for a test for the java wrapper.

Change-Id: I59ca559f257a4c671e9b72a50b5635b5eb61ee69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28180
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

base-stats: Print the name of stats sharing the same name

Having stats of the same name within the same group result in an error.
This commit adds the name to the error message to make it easier to find
the Stats::Group caused the error.

Change-Id: I4010d5d949d1c943d2dd1e2fca0aafcbf62e3ee1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38337
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: term, remove install target

Installing the term utility within the host filesystem is an unlikely
scenario. Most times, the utility will be used in place or trivially
copied to a local directory within the PATH.

Furthermore, the install target hardcoded a privileged installation,
which is a non-standard and insecure technique.

Change-Id: I1592a304017c6b24a9421aa353229fb5a5baae43
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38415
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,arch-gcn3,arch-x86: Changed X86 testlib tests to GCN3_X86

In an effort to get better test coverage, we've changed all X86 tests to
use GCN3_X86. This will, as a minimum, ensure that GCN3 is regularly
compiled. GCN3_X86 is a superset of X86 and all X86 tests should pass on
GCN3_X86.

Change-Id: I2684edfc4e48c3e311a400231293a9e04c701130
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38279
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Standardized used of the ISA constants tags

Change-Id: I4a3966168a1d159bf4ac4cc3148e9c7a43c880e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38278
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Removing cloudbuild_presubmit.yaml

This is not used. It can be removed.

Change-Id: I2e25a5407ca70a18b4e619f4e65b69b98c873511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38375
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: MinorCPU not updating cycle counter value

By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.

For more info check the following email thread in gem5-users:

https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html

Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util: More doc for the Gerrit bot, add padding time to query age

The following changes were made:
- Improve the wording of comments in the Python files and of the
documentation in the README file.
- Add 10 seconds to the query age so that the bot wouldn't miss
any new changes that could be missed due to time difference between
the Gerrit server and the bot.

Change-Id: Ic75f9572653a248230a8b4b0bd360a8d22efd371
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38155
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: able to define resource stalls handlers

Input ports can specify a custom handler that is called
on resource stalls. The handler should return 'true' to
indicate the stall was handled and new messages from that
queue can be processed on that cycle. When it returns
'false' or no handler is defined, a resource stall is
generated.

Handlers are defined using the 'rsc_stall_handler' (for
resource stalls) and the 'prot_stall_handler' (for
protocol stalls) parameters. For example:

in_port(mandatory_in, RubyRequest, mandatoryQueue,
        rsc_stall_handler=mandatory_in_stall_handler) {
    ...
}

bool mandatory_in_stall_handler() {
    // Do something here to handle the stall !
    return true;
    // or return false if we don't want to do anything
}

Note: this patch required a change to the generate()
functions interface in the SLICC compiler, so we
could propagate a reference to the in_port to the
appropriate generate() functions. The updated interface
allows passing and forwarding of keyword arguments.

Change-Id: I3481d130d5eb411e6760a54d098d3da5de511c86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31265
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,tests: use Sequencer port connect methods

This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.

Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
and scripts in which the obj connected to the RubySequencer is not a
BaseCPU (e.g. the tests scripts) were not changed as they require a
non-standard port wireup.

Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31418
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: functions for connecting sequencer ports

Added functions for connecting the sequencer and cpu ports.
Using these functions instead of wiring up the ports directly allow
protocols to provide specialized sequencer implementations. For
instance, connecting the cpu icache_port and dcache_port to
different sequencer ports or to different sequencers.

A follow-up patch will update the configurations to use these
functions.

Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Convert RISCV to use local reg index storage.

This was mostly straightforward, except that the micro and macro op
classes need to be seperated for AMO classes so that the reg_idx_arr_decl
will have the right sizes.

Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36881
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make running m5 util unit tests opt-in.

These tests don't run reliably right now for a few reasons, including
problems with QEMU, and apparently inaccurate information from g++-s
--print-sysroot option.

This may be revisited in the future if those problems can be sorted out.
For now, avoid tripping up new people who won't know to (or how to) work
around those sorts of errors.

Change-Id: Ide42e6c6b27159ff146b8495ae568d1fd377f4f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28179
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Break out the dispatch tables in the m5 util call types.

These dispatch tables will be useful in the java and lua wrappers as
well, since those should also support the alternative call methods.

Change-Id: Ib3be510c99b04960eb2efbc732aebe3165882bee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28178
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Automatically load the java .so in the gem5 ops wrapper.

The java wrapper which provides access to the gem5 ops is implemented
using JNI in a .so file which needs to be loaded before the class can be
used. Rather than expecting the caller to do that, we can use a static
block in the class definition. We know that will be called at the right
time, and it's one less detail (arguably an implementation detail) that
the caller won't have to worry about.

Change-Id: I2b4b18ebb12030ea6f4e6463c6cd512afed74cfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28177
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Reorganize the java wrapper for gem5 ops.

Rather than use a top level package of jni which is generic, switch to a
top level package of "gem5". With that prefix, call the actual class
Ops, which is capitalized according to Java tradition and also
unambiguous given its package name.

Also move the java class definition and c JNI implementation into a java
subdir to keep it all together. The java related output will now be in
out/java for the same reason.

Change-Id: Ia0468d2edbcffe87a62022898f867ae391adc94c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28176
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add the "sum" method to the java and lua m5 util wrappers.

Change-Id: Id55dec87af3e0fc89da6c5471a2aa02443063108
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

cpu-o3: Fixed halt assertion failure

Halting the O3 CPU would cause an assertion failure because
instructions were not finished being squashed in the ROB.

Change-Id: I8b8c375d0e520861af3657249de987de2451b6f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37676
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Link m5_mmap into the JNI shared library for the m5 util.

Change-Id: I6849a547e9150417a09f7a0efc73ebf032e44f3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28174
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Rename the aarch64 m5 util version to arm64.

Change-Id: I0ab0c4af0b24a4934b059d934fce237eeab839da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27757
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>

util: Add a --verbose flag to the m5 util's scons.

Like gem5's own verbose scons flag, when this isn't provided, the output
is very brief and just shows what is being built and by what type of
process. When it is provided, the full command lines are printed.

This is less fancy than the version gem5 has, but I didn't want to
duplicate all that code. We should find a way to share that and other
functionality between different sets of scons scripts.

Change-Id: Id9973b57a1270ec8b364efd2aa67d49b0fb82a9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27756
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a --no-test-xml option to the m5 util's scons.

This forces the test XML output files to be omitted from the build. This
lets you run scons build/ to build everything without running any tests,
and can be used to verify that everything builds correctly even if the
tests don't run/pass.

Change-Id: I280ffe4e76b2249912f9a51a414f4058a3643229
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27755
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

util: m5term, fix LDFLAGS, standard make variables

Enables build systems to provide necessary flags to build m5term.
Useful specially if a different linker is intended to be used.

Change-Id: If7f867cc0965d6ad4627b5421e00a99cc3d64989
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38256
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Pass TERM through to commands in the m5 util's scons.

This enables color output from commands since they can detect that the
terminal supports it.

Change-Id: I4bbf400dccb8c6bfe92459a9db812e06e5a69b5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27754
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>

util: Add a --debug-build option to the m5 util scons.

This enables debug info with -g, and disables optimization with -O0.

Change-Id: I788585c379f048d373c54dc04e7c460914d6912e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27753
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a README file for the m5 utility.

This is a fairly comprehensive document which describes how to use the
m5 utility, the various libraries/modules, and the various included
tests.

Change-Id: I63b5c0a50852a57e6d1b2779090308994e5d0f81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38215
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Teach the m5 utility's scons how to run unit tests.

This may be directly in the case of native tests, or through a user
level QEMU binary for non-native tests. scons is smart enough to expect
to be able to run native tests always, and non-native tests only if a
qemu binary has been found.

To tell scons to run tests in a particular category, you can use a
command of this form:

scons build/[category]/test/

where category is either an "abi" like sparc or x86, or "native" for
tests which don't do anything target specific and so can be run on the
host.

There will be two directories under .../tests, "bin" and "result". "bin"
is where the test binaries themselves will be built, and "result" is for
the results of running those binaries.

Change-Id: I6450ab4a97169f8a01292d946bfac18008b0430c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27752
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Fix setting prefetch bit

Commit https://gem5-review.googlesource.com/c/public/gem5/+/35699
had a copy-paste error: when setting the prefetch bit it must
become true.

Change-Id: Ib0abc5141dd65d3c739dc01948a72eb5451884e8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38176
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu, sim: Remove unused System::totalNumInst

This counter gets augmented for every executed instruction but it
is not used. It is also overlapping with the

BaseCPU::numSimulatedInsts

A client willing to know the number of simulated instruction should rely
on the interface above.

Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25305
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Let the pseudoInst dispatch function handle the return value.

When the result is returned to the caller from the pseudoInst dispatch
function, the default behavior is to not store that value using the
guestABI mechanism. In the x86 definition, I accidentally used this
version but then didn't store the result manually. The fix should simply
be to not return the result to the instruction definition and to let the
guestABI mechanism handle everything normally.

Change-Id: Ib69f266ad6314032622e5d8d69e9ff114c62657a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38195
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update ROCm to 1.6.4 in gcn Dockerfile, install HIP by .deb

Previously, we were using ROCm 1.6.2 as there were issues with some of
the machine learning applications that weren't present on 1.6.2.
However, after re-running them we've found that they, and all other
applications previously tested, run to completion.

Additionally, there have been patches to enable BLIT kernels which made
it so we no longer need to build HIP and MIOpen differently for APU and
DGPU code. This allows us to install HIP directly from the .deb packages
instead of from source. Installing from the .deb packages also avoid the
hipDeviceSynchronize() bug. Finally, this makes it so most GPU programs
can be run as-is without modifications to remove hipMalloc/hipMemcpy
calls as was done previously.

Change-Id: Ic61b09ed200b19f759d891487cde874abd607537
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37675
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Use dict.get syntax for accessing buildEnv keys

37775 removed SmartDict, which is the type buildEnv used to be.
Because of that change, doing buildEnv[key] with a key not in the dict
returns KeyError instead of False. By using buildEnv(key, False), we are
able to return False when the key isn't in the dict.

Change-Id: I4aae29b95b082efb2b021f21d608f9cd1c196379
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38135
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Add exp_cnt tracking for buffer store instructions

exp_cnt (expInstsIssued in the code) is used in the waitcnt instruction
to track that data has been read out of VGPRs in previous global
memory instructions, making it safe to overwrite the VGPRs used in said
global memory instructions.

Previously, exp_cnt wasn't being tracked at all, which lead to the
waitcnt finishing immediately, leading to the memory instruction's VPGRs
getting overwritten by subsequent instructions, causing errors.

This patch makes it so waitcnts waiting on exp_cnt will wait for MUBUF
buffer store instructions to read their VGPRs before completing

Change-Id: Idd2b59511bc086cf316217da27b7a228272b0b0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37555
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Set frequency ranges in OSC device tree nodes.

The existing device tree generation method would use the default
frequency as both the min and max frequency when setting up the OSC
device tree nodes. This would sort of work, except it seems that if
the kernel needed to adjust a frequency, it would fail to do so since
it would assume the new frequency was out of range.

Since the existing property is used to set the initial frequency of
those clocks, and because the default, min and max frequencies are all
mostly independent variables (other than obvious ordering restrictions),
two new properties were added, min_freq and max_freq, which are only
there to fill in the frequency range property in the device tree. If
they aren't set, then the device tree generation method falls back to
the old way of using the default frequency as both min and max.

Change-Id: Ie907bd673f8bcb149e69e45c5b486863149b8a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Convert POWER to use local reg index storage.

Change-Id: Ieea4ade247f89b23266a383b604c17e740d44e3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36882
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Port util to python3

This commit is the result of running 2to3 converter on the util
subdirectory

JIRA: https://gem5.atlassian.net/browse/GEM5-832

Change-Id: I4e7e2d2b1b99f7bcc5fe0f6dc5d25880323616eb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37797
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: make ProbeListener satisfy the rule of five with deleted

Since this class has a custom destructor ~ProbeListener(), it should
also generally have the 4 other methods defined, otherwise calling
those methods lead to subtle failures.

In this specific case, the ProbeManager *const manager; field stores a
pointer back to the ProbeListener object at:

ProbeListener::ProbeListener {
    manager->addListener(name, *this);

which gets unregistered by the destructor:

ProbeListener::~ProbeListener()
    manager->removeListener(name, *this);

and because the default copy does not re-register anything, it leads to
unregistration.

Therefore, a copy constructor would need the manager to support multiple
identical listeners, or at least refcount them, which would be overkill.

The two move operations would be more feasible, as we could make them
unregister the old ProbeListener address and then re-register the new one,
but that is not very efficient, so we just delete them as well.

A consequence of not implementing the move methods is that it is
impossible to store ProbeListener inside an std::vector. since objects
inside std::vector may need to be moved in memory when the vector resizes,
and therefore need to be movable. The alternative is to use an std::vector
of std::unique_ptr instead.

Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: add official names to all PMU events

Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37976
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add ID_MMFR4{,EL1} system registers

Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34876
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a gerrit bot

This bot utilizes the Gerrit REST API to query for new changes
made to Gerrit within a certain amount of time and performs a set
of tests on the changes.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9d5af31d952bc0cd791f1569e6aac7c270e687e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34737
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Merge "misc: Merge branch hotfix v20.1.0.2 branch into develop" into develop

arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode

Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add SECURE_RD/WR flags to miscRegInfo

The introduction of Secure EL2 in gem5 requires the introduction
of new miscReg flags as there are some EL2 registers which are
accessible from secure mode only

Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37615
Tested-by: kokoro <noreply+kokoro@google.com>

dev: -Wdeprecated-copy not available on all supported compilers

This option has been introduced in:
1) gcc/9.0 [1]
2) clang/10.0.0 [2]

[1]: https://gcc.gnu.org/gcc-9/changes.html
[2]: https://releases.llvm.org/10.0.0/tools/clang/docs/ReleaseNotes.html

Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37795
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister

This register is used since the Linux kernel 5.6 aarch64 boot.

This register indicates CPU capabilities in aarch32 mode, and it has the
same value as the aarch32 ID_ISAR6 miscregister, which is also added.

The capability values of those registers are analogous to those present in
aarch64 accessible ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1, which refer to
aarch64 capabilities however, and were already implemented before this
commit.

The arm architecture document clarifies that reads to this system register
location before it had been defined should return 0, but we were faulting
instead:

> Prior to the introduction of the features described by this register,
this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Added gem5.fast clang compilation to Kokoro

Compilation issues in Clang and in compiling gem5.fast are normally
only caught during gem5's weekly, intensive, compilation checks:
http://jenkins.gem5.org/job/Compiler-Checks. The purpose of this change
is to have smaller checks on every commit, reducing the chance of
uncompilable code being submitted.

Change-Id: Idd8c6795ff73e21b1814281c31fc7ae39f09dcc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37478
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

sim: ScopedCheckpointSection to public for mappingParamIn

In clang, the following error was given:

```
In file included from build/X86/sim/eventq.hh:51:
build/X86/sim/serialize.hh:533:19: error: 'ScopedCheckpointSection' is a protected member of 'Serializable'
    Serializable::ScopedCheckpointSection sec(os, sectionName);
                  ^
build/X86/sim/serialize.hh:175:11: note: declared protected here
    class ScopedCheckpointSection {
          ^
```

The use, at line 533, was introduced in this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/36135

This can be fixed by making ScopedCheckpointSection public.

Change-Id: Ib6ffba18d5e8c37980d4febb548f2405cb45ce8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37915
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache, stats: Stats update for snoop filter

Change-Id: I339bbc4268d5b9501421a2a6a76e5267422c87aa
Signed-off-by: Maryam Babaie <mbabaie@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36355
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Convert MIPS to use local register index storage.

Change-Id: Ib691f3dd666c0877fc53b2f50dbaaf7bb4a6905b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36880
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Convert SPARC to use local register index storage.

Once all ISAs are converted, the base StaticInst class will be able to
drop its local arrays, and will no longer need to know what the global
maximum number of source or destination registers is for a given
instruction.

Most of the convertion was very simple and just involved adding tags to
declare and install the register arrays in all the class definitions.
Since SPARC has a relatively simple ISA definition, there weren't many
places that needed to be updated.

The exception was the BlockMem template, which was declaring the microop
classes within the body of the macroop. That was ok when those
declarations didn't need anything other than the name of their parent,
but now they also need to know how big to declare their arrays based on
their actual implementation.

To facilitate that, and to significantly streamline the definition of
the macroop class, the microop class definitions were moved to their own
template, and only the declaration was left in the parent class.

Change-Id: I09e6b1d1041c6a0aeaee63ce5f9a18cf482b6203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36879
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Convert X86 to use local reg index storage.

Change-Id: I42bd3e08ebcffe25e2f366be82702b3c04225e92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36883
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use the common pseudoInst dispatch function.

Instead of manually calling each of the PseudoInst implementations, this
function will automatically pick up new instructions and greatly
simplifies the ARM ISA files.

Change-Id: I6cb94b3d115f50d681ca855f80f9d7d3df6bc470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27791
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: serialize miscregs as a map

This will prevent checkpoints from breaking on every miscreg addition.

Before this commit, miscregs were stored as an array:

[system.cpu.isa]
miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ...

and after this commit they are stored as a map:

[system.cpu.isa]

[system.cpu.isa.miscRegs]
cpsr=965
spsr=0
spsr_fiq=0
spsr_irq=0
spsr_svc=0
spsr_mon=0
spsr_abt=0
spsr_hyp=0
spsr_und=0
elr_hyp=0
fpsid=0
fpscr=0
mvfr1=17895697

JIRA: https://gem5.atlassian.net/browse/GEM5-661
Change-Id: I49999c7206bd9ac1cfb81297d45c8117ff8ae675
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36116
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING

The motivation for those new methods is to prevent checkpoints from
breaking when new map entries are added.

Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
JIRA: https://gem5.atlassian.net/browse/GEM5-661
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36135
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix cache hits being profiled as cache misses

There are some instances where a cache hit is profiled as a cache
miss. This commit addresses this error.

Change-Id: I7dafa806ef3f1e3717650dc25f8657a0ea741dd1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37835
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Remove SortedDict from python utilities

The SortedDict isn't actually used. A developer willing to
use a sorted dictionary should resort to the collections.OrderedDict
instead

Change-Id: Ia2cc664eb01e59b197218ccf40ff9c680a410fb2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37796
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons, python: Remove SmartDict from python utilities

The SmartDict, used by buildEnv, has been added long time ago for
the following reasons: (checking its documentation)

---
The SmartDict class fixes a couple of issues with using the content
of os.environ or similar dicts of strings as Python variables:

1) Undefined variables should return False rather than raising KeyError.

2) String values of 'False', '0', etc., should evaluate to False
   (not just the empty string).
---

These are valid reasons, but I believe they should be addressed in
a more standardized way by using a common dictionary.

1) We should simply rely on dict.get

if buildEnv.get('KEY', False/None):

2) We should discourage the use of stringified False or 0.
If we are using a dictionary, can't we just pass those values as
booleans?
The SmartDict is basically converting every value into a
string ("Variable") at every access (__getitem__)
The Variable is a string + some "basic" conversion methods
What is the problem of passing every dict value as a string?

The problem is the ambiguity on the boolean conversion.

If a variable is modelling a boolean, we can return true if
the value is 'yes', 'true'... and false if the value is
'no', 'false' etc. We should raise an exception if it is
something different, like a typo (e.g.) 'Fasle'.
But if the variable is not modelling a boolean, we don't know
how to handle that. How should we convert 'mystring' ?

If we decide to treat 'mystring' as True (which is basically
what a str.__bool__ would return) we will break typoes detection,
as 'Fasle' will now be converted to True, rather than raising
an exception.

Change-Id: I960fbfb1ec0f703e1e372dd752ee75f00632acac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37775
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Relax commit message checker to allow fixups

Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37598
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util: Use MAINTAINERS.yaml for valid tags in git hook

There is a mismatch between the tags in MAINTAINERS.yaml and the
valid_tags in the git hook. This means if a user consults the
MAINTAINERS.yaml file to find the appropriate tag, there is a chance of
the commit being rejected due to this mismatch. Now that the maintainers
file is in yaml format, use the util/maint library to parse the valid
tag options. Additional meta tags are added (WIP, RFC) and tags that
were previously valid but not in the MAINTAINERS.yaml file.

Change-Id: I3de8f0b6f8507aa1afd2118bc4373ac0610cce40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37220
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby,misc: Fix a parameter name in a DeprecatedParam message

Change-Id: Ie84a29e779187effea372c6289688f32a1db075d
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36635
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix toBool converter

It was using an undefined variable (result) which was mistakenly left
there after its latest refactor

Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,stats: Update stats style for power_model and thermal_domain

Change-Id: Ie50553c301ff5790b51057dc117568374f0cbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36515
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem,stats: Update stats style for mem/probes and mem/qos

Change-Id: I47a094eb8fc56ef998ec3c971dab68ba39b092e3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36476
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem,stats: Update stats style for FALRU

Change-Id: I67a202eb974a31851fbbce0f15b5377ba726bc1c
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36475
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,stats: Update stats style for CopyEngine and IdeDisk

Change-Id: Ib757b00864bc144b20adef974e3443ddba2945f0
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36436
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,stats: Update stats style of src/dev/net

Change-Id: I06c41a0506415c7a4f2608668b90d328c2789e61
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36435
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm,stats: Update stats style of src/dev/arm

Change-Id: I722e88801bb8ca0f0d75b5a1bf271fa4d4eded17
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36415
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Update stats style for base.hh and base.cc

Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36297
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-simple,stats: Update stats style

Change-Id: I1e9c7c464f1f7b4b354e9a47c7d974c6806b45da
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36295
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for mem_dep_unit.hh

Change-Id: I9bd8e9bc331f5d57c1b6320a87b14e9b94465148
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36215
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for cpu.hh and cpu.cc

Change-Id: If4ddaf6a9a84ea71fa19f5ca6d2e5294ec9a0b23
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style of inst_queue & inst_queue_impl

Change-Id: I95c2e194e757437fb8c3b3f530bce363e24f9a8e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36176
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for iew and iew_impl

Change-Id: Ie213aeb402fee5f015f10c9c03e5b9c02ba1f3fe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36095
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor,stats: Update stats style of MinorCPU

Change-Id: Id14e6816cc82603459bf68461ae40bf2b63080eb
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Replace xrange with range to be python3 compliant

Change-Id: I69ef5d744e2642af95383fbda920464178380757
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37716
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Use BaseMMU in the CortexR52 wrapper

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Make tlm/gem5 packet conversion flexible

We used to have a hard-coded packet2payload and payload2packet in the
tlm_bridge implementation. However, as the conversion is operated on
generic tlm payload, we're not able to handle information stored in any
user defined SystemC extensions.

In this CL, we add a pair of function to register extra conversion steps
between tlm payload and gem5 packet. This decouples the exact conversion
logic and enables SystemC users to register any necessary steps for
their extensions.

Change-Id: I70b3405395fed0f757f0fb7e19136f47d84ac115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37075
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add some format strings to the parser for reg indexes.

There are two new strings, reg_idx_arr_decl which declares the source
and dest register index arrays, and set_reg_idx_arr which installs them
in the base class.

The set_reg_idx_arr code needs to implicitly figure out what type to use
based on the type of the "this" pointer. The name of the containing
class is not *necessarily* the same as class_name, since the generated
code can use that name, something based on that name, or whatever else
it wants. No other format string (other than class_name itself) uses the
class name internally, so we can't count on that working in existing ISA
definitions.

Change-Id: Id995a46896e71a2fcf3103c34a1e1e67e24f88f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36878
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Add an StaticInst accessor for setting register index storage.

Change-Id: I66adccd8851f035b5d61ace9153ae7acc57403ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36877
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor: this is a bug fix for MinorCPU for thread cloning.

Inside the code of cloneFunc(…)  //syscall_emul.hh

    cp->initState();  //line 1483
    p->clone(tc, ctc, cp, flags);  //line 1484
    …
    ctc->clearArchRegs(); //line 1503

    OS::archClone(flags, p, cp, tc, ctc, newStack, tlsPtr); //line 1505
    …

At line 1483, initState() is called and the activateContext() of the
corresponding MinorCPU is eventually called. The actual architecture
clone happens at line 1505 where PC of the new thread could have a
correct value.

In the existing implementation of MinorCPU::activateContext(ThreadID
thread_id), the below line 275 is called
    pipeline->wakeupFetch(thread_id);
to start fetching instruction with current value of PC, which is 0x0,
leading to panic “Page table fault when accessing virtual address 0”.

This is because the OS::archClone() is not yet called. So, the below bug
fix handles the wakeup fetch for a thread for two scenarios:
   ...
    if (!threads[thread_id]->getUseForClone())
    { //the thread is not cloned
        pipeline->wakeupFetch(thread_id);
    } else {//the thread from clone
        if (fetchEventWrapper != NULL)
            delete fetchEventWrapper;
        fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
          {pipeline->wakeupFetch(thread_id);}, "wakeupFetch");
        schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
    }
    ...
If a thread is not cloned, pipeline->wakeupFetch() is called
immediately.
For the cloned thread, the above bug fix delays the execution of
    pipeline->wakeupFetch()
after the OS::archClone is done. ThreadContext::getUseForClone() return
true if a thread is cloned.

A member variable fetchEventWrapper is added to MinorCPU class for
delayed fetch event.

A member variable useForClone and its corresponding get/set methods are
added to ThreadContext class. This approach allows future reuse of this
useForClone variable by other CPU models if needed and also avoid lots
of changes resulted by modifying parameters of activateContext () and
activate() which are defined as override.

Inside the syscall cloneFunc, the useForClone member of a ThreadContext
object is set via its set method right before Process's initState() is
called, shown as below.
    ctc->setUseForClone(true);
    cp->initState();
    p->clone(tc, ctc, cp, flags);

A few previously failed RISC-V ASM tests have been open in tests.py file
after the bug fix works.

JIRA issue: https://gem5.atlassian.net/browse/GEM5-374

Change-Id: Ibffe46522e2617443d29f49df180692c54830f14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37315
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix object scope in the CPUID code.

The original version of the code takes a pointer from a temporary object
which gets destroyed before the pointer is used.

Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37695
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3,misc: Added missing overrides to gpu_thread.hh

Compiling GCN3 with clang will result in errors within this change.

Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37538
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

cpu: Access src and dest reg indexes using a pointer to member.

This will eventually let subclasses provide their own appropriately
sized storage for these indexes. By using a pointer to member instead of
a regular pointer, we ensure that even if the StaticInst is copied/moved
somewhere, it will still find its indexes correctly, without any
additional performance overhead or maintenance.

Unfortunately C++ has decided that arrays with known bounds are not
convertible/compatible with arrays with unknown bounds. I've found at
least two standards proposals in various stages of acceptance which say
that that's dumb and they should change that (because it's dumb and they
should change that), but in the mean time we can get everything to
compile by using the reinterpret_cast hammer. While this is
*technically* undefined behavior, it's basically not and should be
pretty safe.

Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36876
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-gcn3, misc: Added missing override to protocol_tester.hh

Clang will return a missing-override error when compiling X86_GCN4
without this change.

Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37537
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-sparc,misc: Added M5_VAR_USED to SparcProcess var

Compiling sparc/gem5.fast fails without specifying this variable is
used.

Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>