base: create DPRINTF_UNCONDITIONAL

This is similar to DPRINTFN, but it also prints a given flag to allow
communicating to users which flag enabled a given log.

This is useful for logs which are enabled with DTRACE instead of directly
with DPRINTF.

Change-Id: Ife2d2ea88aede1cdcb713f143340a8788a755b01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22005
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: add the --debug-flag to DPRINTF output with FmtFlag

This makes it easier to determine which messages come from which
flags when enabling multiple flags at once.

This commit covers the bulk of the debug messages, which use the DPRINTF*
family of macros. There however macros that use DTRACE to check for
enable, those will be covered in future patches.

Change-Id: I6738b18f08ccfd1e11f2874b426c1827b42e82a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22004
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Make the Tarmac parsed registers case insensitive

This will make parsing more robust, considering the tarmac
format changes between AA32 and AA64.

Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22845
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix immediate decoding for integer shift immediate instructions

The "shamt" in integer shift immediate instructions is an unsigned
immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20]
as an int64_t. This patch fixes the problem by:
- Adding a new parameter "imm_code" for format IOp and use the correct
bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction.
- Use uint64_t instead of default int64_t to assign parameter "imm_type"
of format IOp.

The instructions affected include:
- Shift Left Logical Immediate, slli
- Shift Right Logical Immediate, srli
- Shift Right Arithmetic Immediate, srai
- Shift Left Logical Word Immediate, slliw
- Shift Right Logical Word Immediate, srliw
- Shift Right Arithmetic Word Immediate, sraiw

Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22563
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling for fence and fence.i

The original Gem5 does not give correct disassembly for instruction fence
and fence.i. This patch fixes the problem by adding two bitfields PRED and
SUCC and a new format FenceOp and a template FenceExecute, in which
operands are generated based on PRED and SUCC in the disassembling
function.

Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.

This conditional compilation was unnecessary and makes gem5 more
brittle and harder to understand.

Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Stop serializing ISA values wihch are cached from the system.

These values are not really part of the ISA state and could be
retrieved from the system during execution. Also these values are
already being set in the ISA constructor.

Change-Id: Iea5f9bbb27add4ecebc6391da6c1c1e49e76508f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22543
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: default MIDR for Armv8 ISA processors

Software such as Trusted Firmware-A checks the MIDR register
to identify which core model is present in the platform.
The previous default value referred to a Cortex-A15 Armv7-A
processor, however when AArch64 is enabled, an Armv8 processor
is expected.
This patch assigns the Cortex-A57 MIDR if AArch64 is enabled.

Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform

This is need after commit b4c9996d894118be04cdf4ed793b35a1d5001942
which makes the AddrRange end address non inclusive.

Change-Id: I859b84f6a91107815236b67c4596291c78881fe3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23003
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: log thread activate and suspend with --debug-flags Thread

The original motivation of this is to help debug syscall emulation
deadlocks.

Change-Id: I1c4f611fa2f2e464a30dc92baac89ca819e16a97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21759
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: don't wake up threads that are halted on futex

At Ia6b4d3e6148c64721d810b8f1fffaa208a394b06 the futex wake up started
skipping selecting threads that are already awake, which already prevented
some deadlocks.

However, threads that are Halting or Halted should not be woken up either,
as those represent cores in which processes have already exited.

Before this commit, this could lead an exited core to wake up, which would
then immediately re-execute the exit syscall, and possibly leave one
genuinely sleeping core locked and:

Exiting @ tick 18446744073709551615 because simulate() limit reached

Change-Id: I1531b56d605d47252dc0620bb3e755b7cf84df97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22963
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling for atomic instructions

The original Gem5 does not give correct disassembly for atomic
instructions, which are implemented with one or two micro instructions.
The correct register indices are not decoded until subsequent micro
instruction is processed. This patch fixes the problem by getting the
register indices and other properties (aq and rl) from certain bitfields
of the machine code in the disassembling function.

Change-Id: I2cdaf0b3c48ff266f19ca707a5de48c9050b3897
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22568
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix disassembling of operand list for compressed instructions

In disassembling compressed instructions, the original Gem5 gives needless
operands, such as register or immediate. This patch fixes the problem.
- Existing formats fixed: CIOp, CJOp, CBOp and Jump.
- New formats added: CIAddi4spnOp (for c.addi4spn only) and CompressedROp (with
  templates CBasicDeclare and CBasicExecute)

Change-Id: Ic293836983256a59d3a7aca091c8184b410516a4
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22566
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

arch-riscv: Fix disassembling of immediate for U-type instructions

For U-type instructions auipc and lui, the 20-bit immediate is left-shifted
by 12 bits in decoding. While the original Gem5 gives the left-shifted
value directly in disassembly.
This patch fixes the problem by
- Assign the original 20-bit immediate to internal variable "imm".
- Output "imm" directly in disassembly, as how the original Gem5 does.
- Do the left-shift to "imm" later in the function defining of each
instruction, rather than in decoding.

Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix bug in serialize and unserialize of Interrutps

When serialize and unserialize an variable, the parameters passed to
SERIALIZE_SCALAR() and UNSERIALIZE_SCALAR() must be the same and should be a
general variable name. If not, the expected item would not be found with
UNSERIALIZE_SCALAR() and a fatal error would be introduced.
This patch fix the bug in class Interrupts of RISCV.

Change-Id: I7dd7ab6805651149304959bdf7ee9f3be9d9eaff
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22643
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

scons: Use the new error() and warning() methods.

Also clean up some error messages which were missing capitalization,
etc.

Change-Id: Iaef6b4343a693d30b579e72218cbb7723ebf7d48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22886
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add "warning" and "error" methods.

These methods will make reporting errors less verbose and more
consistent, since they'll handle some formating, setting colors,
prefixing with an appropriate "Warning:" or "Error:" tag, and exiting
in the case of an error.

Change-Id: Iddea5bf342a4fc4b26002d8e98292f9dc57fa8cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22885
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Use HAVE_PROTOC when building protobuf files.

Also wrap PROTOC in {}s which is better form.

Change-Id: I3f80c260593a1d5b7fb5394fe4b71cb774e652ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22884
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Don't use PROTOC for the protoc command and to flag its presence.

Commands that blindly use PROTOC will try to execute "False" which is
very confusing for someone looking at the console output and error
messages. Instead, create a new environment setting HAVE_PROTOC which
is either true or false depending on if the protoc command exists and
passes muster.

Also, if there's an error running protoc, catch that and use it to
mark protoc as unavailable. The previous behavior was to supress errors
and just return an empty string instead, I assume with the expectation
that that would be an invalid version and fail later checks.

Change-Id: I1251b4e7e0e9894cdd3343e59498cc653b648b26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22883
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTests for exec_ecoff.h and exec_aout.h

Change-Id: Iec76ba24a06425caefd28d640c6479720f401c06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test,base: Added GTest for base/loader/image_file_data.cc

image_file_data.cc reads an image file, or an image file compressed with
gzip. Mock image file data, and that data in a gzipped state, has been
included in base/loader/small_image_file.test.hh to aid testing.

Change-Id: I69691b93ca03c34d6bd736cbc5c6503115bd7b3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22743
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove tests making use of Big/LittleEndianOrder Namespace

Unit tests are currently broken.
commit d40f0bc579fb8b10da7181d3a144cd3e9a0a0e59 is removing the
BigEndianOrder and LittleEndianOrder namespace.
Therefore we shouldn't test them and their helpers.

Change-Id: I68a45f264b782334d0a0f725c2c435c27337e757
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22943
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,tests: Expanded GTests for addr_range.hh

These tests assume the "end address" is not included in the range. This
exposed some bugs in addr_range.hh which have been fixed. Where
appropriate code comments in addr_range.hh have been extended to improve
understanding of the class's behavior.

Hard-coded AddrRange values in the project have been updated to take
into account that end address is now exclusive. The python params.py
interface has been updated to conform to this new standard.

Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: gitignore the aarch64 bootloader object files

Change-Id: I0cb494fb82c557cfce553bc925ea89a8220e4c16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22826
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: ignore .gen directory that contains DTS files

Those files are removed by default because they are intermediary,
but it is possible to explicitly build them with an explicit target:

make .gen/armv7_gem5_v1_1cpu.dts

Change-Id: Id86968fbb2f2b95ce71109de5a0cb8039a048a27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22825
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Use dts include instead of cpp in ARM DTBs

Change-Id: I342691a42e84dfe53659a7acb3b8db04e52e3002
Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22824
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Rework boot loader makefile to be more generic

add all, clean and install rules
use variables for CROSS_COMPILE, CC, LD, DESTDIR
use generic rules to produce objects and link

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
[ciro.santilli@arm.com: Also add BUILDDIR and to allow fully
 out-of-tree builds.]
Signed-off-by: Ciro Santilli <ciro.santilli@arm.com>
Change-Id: Id84bc6a8e5dde409b6fb968925ca268376730196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22823
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Added GTests for base/intmath.cc

Testing intmath.hh and intmath.cc. Here is the
list of the functions that are tested.
intmath.isPowerOf2, intmath.power, intmath.floorLog2,
intmath.ceilLog2, intmath.divCeil, intmath.roundUp,
intmath.roundDown. Other functions are not tested,
because they are not currently used and are dead code.

Change-Id: I150ac1b5cead93c6698a8c9e9cec80bd87ef181a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22081
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mahyar Samani <msamani@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests, base: Removed dead code from base/intmath

The below list of functions were dead code and are now
deleted.
intmath.prevPrime, intmath.isPrime, intmath.leastSigBit,
intmath.floorPow2, intmath.ceilPow2, intmath.isHex,
intmath.isOct, intmath.isDec, intmath.hex2Int. The source
file intmath.cc is now effectively useless and deleted.

Change-Id: I28e4350056b8d03e02fecd5c7f7f9c62bc2df7ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22584
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

arch: Get rid of the (Big|Little)EndianGuest namespaces.

These namespaces were used to set up an environment/context where there
was an implicit guest namespace. This is an issue when there may be
multiple guest endiannesses which might be different. In cases where
we don't know what the guest endianness is, we can't rely on it being
an implicit part of our context since that would be ambiguous. In cases
where we do know, for instance in ISA specific code, we can just use
the endianness specific version that's appropriate for that context.

This also (somewhat) removes the assumption that there is a single
endianness that applies for a particular ISA. Practically speaking this
assumption will probably still stand though, since there would likely
be a non-trivial performance penalty to apply a configurable endianness
instead of a fixed one the compiler can optomize/remove.

Change-Id: I2dff338b58726d724f387388efe32d9233885680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make and use endian specific versions of the mem helpers.

Rather than using TheISA to pick an endian conversion function, we can
have a version defined for big and little endian and call the right one
from the ISA code.

Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: R/W interface to AArch32 HCR2 misc reg

This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.

Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.

Members `tc` and `ongoingTranslation` were uninitialized in the constructor for
`QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to
`false` by default, some translation requests from queued prefetchers are not
properly handled and executions are nondeterministic.

Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.

The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a
dynamically-allocated array. Changed to `delete[]` to remove potential undefined
behaviour.

Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix short descriptors cacheability during table walks

This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits.

Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix long descriptors cacheability during table walks

Prior to this patch table walks were always cacheable unless
cacheability was globally disabled by SCTLR.C being 0.  Arm allows to
select the memory attributes of table walks via the TCR registers.

For example the TCR.IRGN0 bits:

Inner cacheability attribute for memory associated with translation
table walks using TTBR0_EL1.

IRGN0   Meaning
0b00    Normal memory, Inner Non-cacheable.
0b01    Normal memory, Inner Write-Back Read-Allocate Write-Allocate
        Cacheable.
0b10    Normal memory, Inner Write-Through Read-Allocate No
        Write-Allocate Cacheable.
0b11    Normal memory, Inner Write-Back Read-Allocate No Write-Allocate
        Cacheable.

Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx
(Outer Shareable domain) since in gem5 we consider everything as
Inner Shareable.

Change-Id: If472c218040029c9d165b056a052f522d48d4a82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for byteswap.hh

In addition to the test, "#include base/logging.hh" was added to the
"byteswap.hh". It is is required to compile the header.

Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32,
ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog,
and ByteswapTest.gtoh. The file byteswap.hh is mostly templates.

Added test for BigEndianGuest and LittleEndianGuest namespaces.

Change-Id: I8870a55594ed439fe9e1fb333384f73261d1b1b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Specify a non-default root folder for regressions

The new testlib library is looking for regressions walking from
a root folder. This by default points to the tests dir.
Since all regressions are supposed to live in the tests/gem5 subdir,
the patch is assigning the gem5 subdir as a root directory.

This will prevent the example garbage to be printed in the ci framework:

Exception thrown while loading
"/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/10.linux-boot/test.py"
Ignoring all tests in this file.
Exception thrown while loading
"/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/80.solaris-boot/test.py"
Ignoring all tests in this file.
[...]

Change-Id: Ia12c6bbeda4ceac71ccd38156ab1e3bb98b05c89
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22726
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Removed ambiguity from base/intmath.hh

The function intmath.leastSigBit is ambiguous given
its name. It does not return the value of the least
significant bit, or the position of the least significant
set bit, but instead 2 to the power of the position of
the least significant set bit. It has thereby been removed
and the function intmath.isPowerOf2 has been refactored to
not require intmath.leastSigBit.

Change-Id: I22479c666cdd059865b8c73b70b5388f98a4584d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22583
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Refactor code to check if gic is GicV2

Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is
only meanful to GicV2.

Test: Boot Android P successfully with the following command:
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt
./configs/example/arm/fs_bigLITTLE.py --dtb
$PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel
$PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img
--kernel-init "/init" --cpu-type fastmodel --machine-type
VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0
--mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000
console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB
root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2
android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5
androidboot.selinux=permissive audit=0 cma=128M"

Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

config: Add fastmodel cluster in fs_bigLITTLE.py

One can create a system with ARM FastModels CPU and GICv3 with
--cpu-type fastmodel --machine-type VExpressFastmodel options.
Currently the FastmodelCluster only supports one CPU.

Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add VExpressFastmodel platform

A VExpress based platform with FastModelGIC as interrupt controller.

Change-Id: I5ef6d04573d271225d7b39c110e93350a290c371
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21359
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Replace most htog and gtoh with htole and letoh.

We already know what endianness to use when with ARM. In places where
a ISA was being supplied through an argument, those were left as htog
or gtoh.

Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: fix routeToHyp for AArch64 in faults

This patch fixes several bugs in Fault classes "routeToHyp" member
function by which mode checking was not taking into account AArch64
execution state. For the particular case of SVC calls from NS EL0, this
prevented a correct routing to EL2 when HCR_EL2.TGE was set.

Change-Id: I5815fe6dcf4501f52bf92f61687ef6d6ef950e52
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22725
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

tests: Added GTests for base/chunk_generator.hh

Change-Id: Ic6ededfc7fed1f91a75e48a0933e61b4670e5af1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21679
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

fastmodel: Implement reading vector registers with readVecReg.

The n other flavors of vector reading functions and all the vector
writing functions are not implemented currently.

Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

tests: Added GTests for base/types.cc

Change-Id: I9515735efdd452a9f8c98f37f4ec2c27120929f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21659
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTests for base/condcodes.hh

The documentation for the "findParity" and "findCarry" functions in
base/condcodes.hh has been enhanced to better explain their behavior.

Change-Id: I9ba3bf68eb56529a3030e965ec21e41d2dacfad6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21639
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Using super in arm_generic whenever possible

This exclude the case where multiple inheritance is used.

Change-Id: Id1a46ca5c6c526a1a29a2cff7b00d7e3b6a79273
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22685
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Using super for calling superclass __init__

Change-Id: I19906db9ce1b9ffb4107b47fe2bc64a8e005e776
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22684
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Remove Noncoherent cache from regressions

Change-Id: I1d499477acec09fd0b36e3b7c2f5eecee737bd93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22683
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix TarmacParser handling of 64bit LD/ST

The TarmacParser was assuming 32 bit accesses only.
This was creating a mismatch when parsing a trace with 64 bit
accesses.

E.g.

In

clk IT (18) 002001f4 f8008441 O EL3h_s : STR      x1,[x2],#8
clk MW8 00201008:000000201008 00000000_40000401

Only the 32 MSBs were checked (00000000)

Change-Id: I51e803b53efe953edcd9378f6c9481c04932331e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21562
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Provide SVE support to the TarmacTracer

Change-Id: I86ff5f49a0c0aa126d53076964f208716e70aacb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21561
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Provide SVE support to the TarmacParser

This patch is providing SVE support to the tarmac parser, so that
it is recognizing Vector & Predicate entries.

Change-Id: I268e621cffa05644d3f1d80170b067aacaa2d5ea
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21560
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Set the number of FloatRegs to zero.

ARM no longer uses the floating point register file and uses the
vector registers instead. This avoids checkpointing a bunch of unused
registers, making it hard to tell where floating point instructions
are keeping their values, etc.

Change-Id: I23145ba750f1dd9ff5b815395e073c410120840d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22524
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTests for base/match.cc

In order to aid testing the method "match.getExpressions()" has been added.

Change-Id: I11acf9bed286ee2809dfa3d05ef573dea85eb786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22503
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix a bug in getCurrentInstCount in the checker CPU.

An earlier change accidentally left out the actualTC-> prefix in the
getCurrentInstCount method which was supposed to delegate the call to
another thread context. Without that, it just called itself and would
infinitely recurse.

This bug was pointed out in email by Robert Henry.

Change-Id: Ibf1fee6b48ff87790309c6d435bd76fa95c6cab9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Replace gtoh and htog with betoh and htobe.

We already know what endianness to use when within power.

Change-Id: Id4ced279d21c56855307a5a8da51654101a13786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22371
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Replace htog and gtoh with htole and letoh.

We already know what endianness to use from within x86.

Change-Id: Ie92568efe8b23fbb7d9edad55fef09c6302cbe62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22370
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Replace gtoh and htog with letoh and htole.

We already know what endianness to use from within MIPS.

Change-Id: Ic4cd295a7a66c4c8ef55ebcf976fe6637567391f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22369
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Replace htog and gtoh with htobe and betoh.

We know what endianness to use when we're implicitly working with
SPARC.

Change-Id: I85eaac1da087a8086b9450b762a52323f2498e2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22368
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Remove boost dependency caused by tlm

This commit replaces the tlm header file, which caused the boost
dependency.

Change-Id: Ie4b1af71202522d8139e9a861144863097188072
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22624
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Plumb the ITB and DTB through the IRIS thread context.

These might be necessary to, for instance, translate virtual addresses.
A custom TLB which uses the IRIS API will be written which can be
substituted in for the normal ARM TLB.

Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Implement inst count events in the IRIS thread contexts.

These use the IRIS stepping API.

Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Simplify AMO code generation templates

This change simplifies the isa template for the atomic memory
operation (AMO). Previously the flow had unecessary if statements that
ended up breaking build using clang, due to variables that could
seemingly be used before they were unitialized.

Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22603
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Use std::array for registers in SimpleThread.

If the number of one of the register types is zero (useful on ARM in
the near future), memset will complain that it's given the length of
the array without multiplying by the size of the array elements. This
is a false positive since the length of the array and the number of
elements are both zero.

To avoid that warning/error and to simplify and update the SimpleThread
class slightly, this change replaces the C style arrays with
std::array.

Change-Id: Ifedd081a1940a578765c4d585e623236008ace67
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22523
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Annotate original address in CMOs

This is needed when a CMO triggers an exception (e.g. DataAbort) In that
case the faulting address should be the one encoded in the instruction
rather than the cacheline address:

According to armarm:
If a memory fault that sets FAR_EL1 is generated from a data cache
maintenance or other DC instruction, FAR_EL1[63:0] holds the address
specified in the register argument of the instruction.

Change-Id: I6d0dadbef6e70db57438b01a76c5def3bdd2d974
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22443
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Reset Ruby Sequencer Outstanding Requests stats

Change-Id: I14b106e0eb7abd9c14badeedf35d6d1c9f198f98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22446
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: optional instantiation of GICv3 ITS

GICv3 ITS is an optional component of GICv3. The previous behaviour
was for a stub ITS to be created by default, which resulted in a crash
for use cases where a GICv3 with no ITS is required.
This patch removes the instantiation of the ITS by default and adds
checks for its presence both in initialization and device tree
generation code.

Change-Id: Id424924c8c1152d512aaa2837de4aa60329ec234
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22423
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Modify compressor to appease newer compilers

The type of the local unique_ptr variable was different from the return type.

In C++11 because of such difference, a copy-ellision would not be possible,
and that required the use of a std::move.

In C++14 the restriction of same types being required was removed, so
std::move would not be needed anymore.

With the addition of the -Wredundant-move warning in newer compilers, having
the std::move on the return became an issue, breaking compilation.

Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Implement a perfect compressor

Implement a perfect compressor that always manages to compresses data
exactly to its maximum allowed compression ratio. This allows tracking
a compression upper bound.

Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Make BDI a multi compressor

BDI is a compressor containing multiple sub-compressors.

Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Implement a multi compressor

Implement a compressor that contains multiple sub-compressors and
choses the one that provides the best compression results for each
compression.

Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Implement BDI sub-compressors

Implement sub-compressors of BDI as public compressors so that
they can be used separately.

Change-Id: I710e35f39f4abb82fd02fd33b1b86a3f214c12cb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21157
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Implement a repeated values compressor

The repeated values compressor can only compress data composed solely
repeated instances of the same value.

Change-Id: If2c4f47ad4af492d202ec2017e30ba52ee67e307
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21156
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Implement a zero compressor

The zero compressor can only compress data composed solely of zero
bits.

Change-Id: I8b359c03776a8748abd144a178bda944b5a1b766
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21155
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Implement FPC-D cache compression

Implementation of Frequent Pattern Compression with limited Dictionary
support (FPC-D) cache compressor, as described in "Opportunistic
Compression for Direct-Mapped DRAM Caches", by Alameldeen et al.

Change-Id: I26cc1646f95400b6a006f89754f6b2952f5b4aeb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21154
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

arch,cpu: Move endianness conversion of inst bytes into the ISA.

It doesn't matter if the bytes are converted before or after they're
fed into the decoder. The ISA already knows what endianness to use
implicitly, and this frees the CPU which doesn't from having to worry
about it.

Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Delete the packet accessors which use guest endianness.

These accessors create an extra dependency on the guest OS, and can be
avoided. Now that all their uses have been removed, they aren't needed
any more.

Change-Id: I466c07fef99bce2d7964c07a7ac3dd398691378b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13465
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.

FLDCW_P and FNSTCW_P should use rip to compute address.

Change-Id: Ide7327e243d42bdd8791e43773385b2a79d45418
Signed-off-by: Zhengrong Wang <seanzw@ucla.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22483
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: add squashfs make to m5-exit

An ARM squashfs rootfs that runs m5 exit can be generated for example
with:

make ARCH=arm_A64 CROSS_COMPILE=aarch64-linux-gnu- squashfs

The existing Makefile.x86 was not used as a basis because we would
like to provide a setup that allows users to use their own compilers
if they wish, without requiring dockcross.

Change-Id: I19c54cf0575b405f191f45aaf1e4a05c3f2e69ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22223
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: generic method for getting an ArmSystem

This patch provides a generic method for casting a System object
into an ArmSystem object. This is specially useful in dev-arm,
since devices by default obtain a generic System reference which
needs to be casted to use ArmSystem-specific functionality.

Change-Id: Ib100002413cb48cd93772dcf38f13be65badd1d3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22426
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add SMMUv3 to VExpress_GEM5_V*

The VExpress_GEM5_V* Platforms will now optionally make use of the
SMMUv3.
In order to attach a devices to it, a user must simply use the
attachSmmu method, making sure the device it is not part of the
_on_chip_devices().

Change-Id: Ib819eb50d43dba1f5e5d1a1f7159ac4fbaccff6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21559
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

config: Add --kernel-cmd option in fs_bigLITTLE.py

Allow users to specify their custom Linux kernel command.

Change-Id: I1e88523c918369ea5dd86c088eca82471663e76a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20900
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Add --mem-size option in fs_bigLITTLE.py

Allow users to specify system memory size.

Change-Id: I1e0c099dc08d04f71b406d8cc86850f68b6048cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20899
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Add CortexA76x[234] models.

These use the parameterization added in earlier commits.

Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Enable auto bridging and use it to simplify CortexA76x1.

This lets us avoid having to set up bridges for all the different
interrupt signals coming out of the CPU. When we have more cores, like
in the x2, x3, and x4 versions of the CPU, we won't have to have a
set of bridges for each set of signals, and can connect them all to
external ports using array notation, keeping everything simple,
concise, and maintainable.

Change-Id: I1a5f707073868516e93c106dc17d105409de668a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21504
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Templatize the xn versions of the CortexA76.

This will make it a lot easier and more succinct to define the x2-x4
versions of that CPU.

Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,tests: add page boundary access test

The O3 model supports unaligned accesses across page boundaries.
This changeset provides a stress test for the feature.

Other benchmarks exercise it, but their coverage is spotty. This
test does nothing else except poke bytes which straddle page
boundaries.

Change-Id: Ic20c2862bcb7af7be091030c12916ba499db10c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22303
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix missing header in associative set

Add missing intmath header to AssociativeSet, so that isPowerOf2 can
be used.

error: there are no arguments to 'isPowerOf2' that depend on a template
parameter, so a declaration of 'isPowerOf2' must be available

Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fixed pipeline squashes caused by aliased requests

This patch was created by Bihn Pham during his internship at AMD.

This patch fixes a very significant performance bug when using the O3
CPU model and Ruby. The issue was Ruby returned false when it received
a request to the same address that already has an outstanding request or
when the memory is blocked. As a result, O3 unnecessary squashed the
pipeline and re-executed instructions. This fix merges readRequestTable
and writeRequestTable in Sequencer into a single request table that
keeps track of all requests and allows multiple outstanding requests to
the same address. This prevents O3 from squashing the pipeline.

Change-Id: If934d57b4736861e342de0ab18be4feec464273d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add baremetal.py example script

Change-Id: I7a4818836decbf743f6c9b1f2e5361a43fca2d10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21799
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: bugfix for partial faults in x86

The c58cb8c9 changeset broke some code related to checking
consistency model guarantees (found in X86 benchmarks).

This changeset adds some documentation to the code and obviates
the problem.

Change-Id: Ied9c6b0b1d237538efe4beb2f97ef76248ce2746
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22283
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

ext: Fix undefined-behavior bug in bitshift

If a small number or zero is passed in, fp64_exp could be very
negative (-1000 for example). The intent of the line is to evaluate to
zero in these cases, but what it actually did was bitshift right by
1000, which is undefined behavior (according to ubsan) that so happens
to result in 0 on GCC/most architectures. This commit changes the code
to check for cases where the bitshift is larger than the width of the
integer.

Change-Id: I8de4bd8ad170f0321d54689460de449b7f8fb60a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21859
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

alpha: Convert htog and gtoh to htole and letoh.

When within the Alpha arch, we know the guest endianness already.

Change-Id: Iee22a33451a06c6e6a5c7d1e8c71f0b00e98ae3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22367
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Make copyStringArray take an explicit endianness.

Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kern: When dumping dmesg, detect the byte order dynamically.

The dmesg dumper has access to the system object and so has access to
the getGuestByteOrder accessor. Use that instead of TheISA to determine
the byte order.

Change-Id: I4df7b1bcd807aaced1d7dc8d2030123e2d4d1d2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22365
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Use the system and OS to get endianness.

This converts the syscall implementations to either use the
OS::byteOrder constant or, if that's not available, the system's
getGuestByteOrder() accessor, to determine the byte order, instead of
relying on TheISA to provide the correct accessor.

Change-Id: Idf7b02ee8d73990224ceac9a5efaec91a5ebf79f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22364
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make endianness a property of the OS class syscalls can consume.

That way the syscall implementations won't have to find the right
endianness to use on their own, typically by referring to TheISA.

Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Make the virtio devices track endianness explicitly.

These classes now track what endianness they're supposed to use
explicitly, initially set by the getGuestByteOrder accessor on the
system object. In the future, if the endianness depends on the
version of the VirtIO spec as the comment suggest, it will be easier
to dynamically set the endianness in the various structures based on
the version being used,

Since there isn't anything special about the virt IO versions of these
converters other than their types, and since the endianness conversion
infrastructure can be taught how to convert new types, the code was
switched over to using the standard htog and gtoh but with the
explicit byte order provided.

This also gets rid of the final use of TheISA in the dev directory.

Change-Id: I9345e3295eb27fc5eb87e8ce0d8d424ad1e75d2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22273
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>