Gabe Black [Fri, 2 Nov 2018 22:02:47 +0000 (15:02 -0700)]
systemc: Move a function after the class it uses internally.
The class was defined, but only later in the file. By putting the
function definition later, clang stops reporting an error.
Change-Id: Id4dd1ec3f3a06f4d1dc10ef4ff8c545d98a6ae12
Reviewed-on: https://gem5-review.googlesource.com/c/13877
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 2 Nov 2018 22:01:50 +0000 (15:01 -0700)]
systemc: Get rid of an unused private member in sc_clock.
It's not useful, and having it makes clang upset.
Change-Id: I51366fd18a287e186c88f08af5c6ba8692779003
Reviewed-on: https://gem5-review.googlesource.com/c/13876
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 2 Nov 2018 23:48:10 +0000 (16:48 -0700)]
mem-cache: Rename the tag class init function to tagsInit.
Since the tag classes are subclasses of SimObject, they inherit an
init function which does generic initialization at simulation startup
and which doesn't take any parameters. A new function was added which
does take a parameter, and which is just for doing tag specific
initialization as triggered by the base cache. These two names clashed,
and clang complained that the tag local name was hiding the SimObject
name (which it was).
Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0
Reviewed-on: https://gem5-review.googlesource.com/c/13875
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Mon, 15 Oct 2018 09:48:32 +0000 (11:48 +0200)]
mem: Use Packet writing functions instead of memcpy
Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.
This also fixes a bug in MemCheckerMonitor, which was using
the incorrect type for the packet pointer.
Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13695
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Fri, 26 Oct 2018 14:40:51 +0000 (16:40 +0200)]
mem-cache: Fix double block invalidation
Block was being invalidated twice when not a tempBlock.
Make explicit that the else case is only to be applied
when handling the tempBlock, as otherwise the Tags
should be taking care of the invalidation.
Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Anouk Van Laer [Wed, 24 Oct 2018 08:49:53 +0000 (09:49 +0100)]
arch, arm: Return s1Req upon fault in s2Lookup
When a s2Lookup object is created, a new request is created, based
upon the original, stage 1 request sent out by the CPU. When a fault
occurs during the second stage of translation, this new request is
returned. This can lead to issues with the O3 CPU. The O3 fetch stage
will not acknowledge the fault as it is a different request than the
one it sent out and does not contain a contextID. This commit
rectifies this.
Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13782
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Anouk Van Laer [Fri, 19 Oct 2018 10:19:08 +0000 (11:19 +0100)]
arch, arm: Effect of AT instructions on descriptor handling
Some address translation instructions will stop translation after
the 1st stage and intercept the IPA, even in the presence of
stage 2 (eg AT S1E1). However, in the case of a TLB miss, the
table descriptors still need to be translated from IPA to PA to
avoid fetching the wrong addresses. This commit splits whether
IPA->PA translation is required for the VA and/or for the table
descriptors.
Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Thu, 11 Oct 2018 00:43:29 +0000 (17:43 -0700)]
util: Add some examples for using systemc code within gem5.
These examples have comments inside them that explain what they do.
There's also a README file which explains how to use the examples
generally, and at a high level what each one does.
Change-Id: I223963dc1c190289986b2ee5705910dbcad4a4c9
Reviewed-on: https://gem5-review.googlesource.com/c/13376
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 11 Oct 2018 00:28:09 +0000 (17:28 -0700)]
util: Move the existing systemc example into a subdirectory.
This example is for how to embed gem5 within systemc and make it use
the systemc event queue. This used to be the only method of using
gem5 and systemc together, but now that there are other options, it's
ambiguous to have it as the only thing in the util/systemc directory.
This change moves it into a gem5_within_systemc subdirectory which
clearly shows what type of integration that example corresponds with.
Change-Id: I426d68ccb618397d820bef492cbb1ff8ef4a979b
Reviewed-on: https://gem5-review.googlesource.com/c/13375
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Ciro Santilli [Wed, 26 Sep 2018 16:11:07 +0000 (17:11 +0100)]
syscall_emul: fix openat when directory does not end in "/"
Before this commit, the following code:
dir_fd = open(".", O_DIRECTORY);
file_fd = openat(dir_fd, "ble", O_CREAT, S_IRUSR | S_IWUSR);
would create a file called ".ble" in the current working directory,
instead of the correct "ble".
Change-Id: I1525a088d49744e29b760387afabef9f1ac98646
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13005
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Ciro Santilli [Wed, 26 Sep 2018 13:43:25 +0000 (14:43 +0100)]
syscall_emul: implement arm openat
This is especially important because the Ubuntu 18.04 packaged
arm-linux-gnueabihf-gcc uses the system call on the program initialization,
which leads all programs to fail with:
fatal: syscall openat (#322) unimplemented.
Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13004
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Yuetsu Kodama [Mon, 29 Oct 2018 12:44:25 +0000 (21:44 +0900)]
arch-arm: FIXUP for the add PRFM PST instruction commit
Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd
Reviewed-on: https://gem5-review.googlesource.com/c/13815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 4 Oct 2018 15:09:03 +0000 (16:09 +0100)]
mem-ruby: Fix MOESI_CMP_directory in ports order
To avoid deadlocks ruby objects typically prioritize the handling of
responses to all other events. The order in which in_port statements
are written determine the order in which they are handled. This patch
fixes the order of in_order statements for the L2 cache in the
MOESI_CMP_directory.
Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13595
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
yuetsu.kodama [Sat, 20 Oct 2018 02:58:54 +0000 (11:58 +0900)]
arch-arm: We add PRFM PST instruction for arm
Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.
Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp>
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Thu, 25 Oct 2018 09:39:50 +0000 (10:39 +0100)]
arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or
15) is implementation defined; this makes it trappable by having
HCR_EL2.TIDCP = 1.
Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13780
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 24 Oct 2018 15:21:41 +0000 (16:21 +0100)]
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.
Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 24 Oct 2018 12:34:25 +0000 (13:34 +0100)]
arch-arm: Refactor AArch64 MSR/MRS trapping
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping
helpers in arch/arm/utility and in the isa code into a MiscRegOp64
class.
This class is the Base class for a generic AArch64 instruction which is
making use of system registers (MiscReg), like MSR,MRS,SYS. The common
denominator or those instruction is the chance that the system register
access is trapped to an upper Exception level. MiscRegOp64 is providing
that feature.
What do we gain? Other "pseudo" instructions, like access to
implementation defined registers can inherit from this class to make use
of the trapping functionalities even if there is no data movement
between GPRs and system register.
Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13778
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 24 Oct 2018 09:32:20 +0000 (10:32 +0100)]
arch-arm: Trap to EL2 only if not in Secure State
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure
state since at the current implementation (Armv8.0) there is no Secure
EL2.
Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13777
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Tue, 23 Oct 2018 12:33:12 +0000 (13:33 +0100)]
arch-arm: Fix HVC trapping beahviour
This patch is fixing HVC trapping behaviour, reusing the pseudocode
implementation provided in the arm arm.
Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13776
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Tue, 23 Oct 2018 15:23:27 +0000 (16:23 +0100)]
arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the
CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR,
are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.
Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13775
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Wed, 24 Oct 2018 11:08:09 +0000 (12:08 +0100)]
tests: Convert AddrRangeMap unit test to a GTest
Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Andreas Sandberg [Wed, 24 Oct 2018 10:50:03 +0000 (11:50 +0100)]
tests: Convert CircleBuf unit test to a GTest
Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13735
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Daniel R. Carvalho [Fri, 19 Oct 2018 15:58:42 +0000 (17:58 +0200)]
mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base
Move evictBlock(CacheBlk*, PacketList&) to base cache,
as it is both sub-classes implementations are equal.
Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13656
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Ciro Santilli [Thu, 13 Sep 2018 14:11:03 +0000 (15:11 +0100)]
config: add --param to fs.py, se.py and fs_bigLITTLE.py
The option allows to set SimObject params from the CLI.
The existing config scripts have a large number of options that simply set
a single SimObject parameter, and many still are not exposed.
This commit allows users to pass arbitrary parameters from the command
line to prevent the need for this kind of trivial option.
Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Reviewed-on: https://gem5-review.googlesource.com/c/12985
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ciro Santilli [Thu, 13 Sep 2018 13:54:34 +0000 (14:54 +0100)]
python: Add utility function to override config parameters
Add a utility method, SimObject.apply_config that can be used to
implement SimObject param overrides from the command line. This
function provides safe and convenient semantics for CLI assignment:
* The override expression is evaluated in a restricted environment. The
only global variables are the child objects and params from the root
object.
* Only params can be overridden. For example, calling methods or setting
attributes on SimObjects isn't possible.
* Vectors use non-standard list semantics which enable something similar
to glob expansion on the shell. For example, setting:
root.system.cpu[0:2].numThreads = 2
will override numThreads for cpu 0 and 1 and:
root.system.cpus[0,2].numThreads = 2
sets it for cpus 0 and 2.
The intention is that the helper method is called to override default
values before calling m5.instantiate.
Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799
Reviewed-on: https://gem5-review.googlesource.com/c/12984
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ciro Santilli [Thu, 11 Oct 2018 00:00:00 +0000 (00:00 +0000)]
arm: treat aarch64 hints as NOPs instead of panic
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13476
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ciro Santilli [Wed, 19 Sep 2018 14:50:46 +0000 (15:50 +0100)]
arm: update hint instruction decoding to match ARMv8.5
This fixes:
- unallocated hints that have since been allocated
- unallocated and unimplemented hint instructions being treated as
Unknown instead of the correct NOP
- missing encoding for DBG on A32
Unallocated and unimplemented hints give a warning if executed.
The most important fix was for the CSDB Spectre mitigation
instruction, which was added recently and previously unallocated and
treated as Unknown.
The Linux kernel v4.18 ARMv7 uses CSDB it and boot would
fail with "undefined instruction" since Linux commit
1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613
Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13475
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 18 Oct 2018 09:56:33 +0000 (10:56 +0100)]
mem-cache: Fix unused variable warning in FALRU:invalidate()
Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13600
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Mon, 10 Oct 2016 13:06:00 +0000 (14:06 +0100)]
mem: Add write coalescing and write-no-allocate to the caches
Enable the cache to detect contiguous writes and hold on to the MSHR
long enough to allow the entire line to be written. If the whole line
is written, the MSHR will be sent out as an invalidation requests, as
it is part of a whole-line write, i.e. no-fetch-on-write.
The cache is also able to switch to a write-no-allocate policy on the
actual completion of the writes, and instead use the tempBlock and
turn the write operation into a writeback.
These policies are all well-known, and described in works such as
Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993.
Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae
Reviewed-on: https://gem5-review.googlesource.com/c/12907
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Mon, 10 Oct 2016 12:48:08 +0000 (13:48 +0100)]
mem: Delay servicing an MSHR after its allocation
An MSHR is allocated and the computed latency determines when the MSHR
will be ready and can be serviced by the cache. This patch adds a
function that allows changing the time that an MSHR is ready and
adjusts the queue such that other MSHRs can be serviced first if they
are ready.
Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff
Reviewed-on: https://gem5-review.googlesource.com/c/12906
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Mon, 10 Oct 2016 13:40:10 +0000 (14:40 +0100)]
mem: Restructure whole-line writes to simplify write merging
This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.
Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Mon, 10 Oct 2016 13:25:42 +0000 (14:25 +0100)]
mem: Determine if an MSHR does a whole-line write
This patch adds support for determining whether the targets in an MSHR
are 1) only writes and 2) whether these writes are effectively a
whole-line write. This patch adds the necessary functions in the MSHR
to allow for write coalescing in the cache.
Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4
Reviewed-on: https://gem5-review.googlesource.com/c/12904
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Gabe Black [Wed, 17 Oct 2018 21:34:08 +0000 (14:34 -0700)]
mem: Mark the guest endianness packet accessors as deprecated.
Change-Id: Iebefeb5b1ce905f2b45b30b7656d6a01d0724584
Reviewed-on: https://gem5-review.googlesource.com/c/13575
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 12 Oct 2018 12:15:34 +0000 (05:15 -0700)]
null: Stop specifying an endianness in isa_traits.hh.
The NULL ISA doesn't really have an endianness. Now that the packet
accessors which consumed that endianness are gone, we can get rid of
that setting as well.
Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4
Reviewed-on: https://gem5-review.googlesource.com/c/13466
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 12 Oct 2018 12:11:20 +0000 (05:11 -0700)]
mem: Explicitly specify the endianness in the abstract memory.
The accessors are used for debugging output. If we're using an ISA
where there's an endianness, we use that explicitly, falling back to a
binary dump if the size isn't supported. If not, then we just dump the
data without interpretation regardless of size.
Change-Id: Ib050c4c876ee41f17cfd14ad657150bf6ab1de39
Reviewed-on: https://gem5-review.googlesource.com/c/13464
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 12 Oct 2018 12:09:27 +0000 (05:09 -0700)]
gpu-compute: Explicitly use little endian packet accessors.
The gpu ISA doesn't have a well defined endianness, but it really
should. It seems that the GPU is only used with x86, and in that
context it would be little endian.
Change-Id: I1620906564a77f44553fbf6d788866e017b6054b
Reviewed-on: https://gem5-review.googlesource.com/c/13463
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Gabe Black [Tue, 16 Oct 2018 02:56:53 +0000 (19:56 -0700)]
arch: Include some additional headers in arch/generic/mmapped_ipr.cc.
These had been included transitively before.
Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0
Reviewed-on: https://gem5-review.googlesource.com/c/13538
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 16 Oct 2018 02:54:28 +0000 (19:54 -0700)]
dev: Remove using namespace TheISA in uart8250.cc.
Nothing in that file is in the TheISA namespace, so there's no reason
to use using on it.
Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4
Reviewed-on: https://gem5-review.googlesource.com/c/13537
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 12 Oct 2018 12:06:26 +0000 (05:06 -0700)]
dev: Explicitly specify the endianness for packet accessors.
Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.
For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.
Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 12 Oct 2018 01:02:14 +0000 (18:02 -0700)]
python: Stop conditionally excluding code from pyobject.cc
Now that the Ether* classes are included in all builds, there's no
reason to conditionally compile code in pyobject.cc.
Change-Id: If94602af71774b1f090a3344a633207f4b37d308
Reviewed-on: https://gem5-review.googlesource.com/c/13470
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 12 Oct 2018 01:00:03 +0000 (18:00 -0700)]
dev: Build most of the networking devices in the NULL_ISA build.
The only part of these devices which are incompatible with other ISAs,
with the possible exception of endianness transformation, is that
the dist_iface implementation refers to ThreadContext methods and
that class is heavily tied to the guest ISA. Only those few lines are
excluded in a NULL_ISA build.
Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460
Reviewed-on: https://gem5-review.googlesource.com/c/13469
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 12 Oct 2018 00:57:20 +0000 (17:57 -0700)]
dev: Build the PCI device models even in NULL_ISA builds.
There are some minor ISA dependencies in the PCI device models,
specifically that they use the set<> accessors on the packet objects.
This actually compiles fine because the NULL ISA claims to be little
endian, but really these accessors should be changed to use little
endian all the time since that's what PCI is defined to use, not
the guest endianness.
The other types of accessors, specifically the ones that default to
what the guest wants, should be excluded when building NULL_ISA, and,
pending other dependencies, the NULL_ISA should no longer have an
endianness associated with it.
Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4
Reviewed-on: https://gem5-review.googlesource.com/c/13468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 16 Oct 2018 03:45:45 +0000 (20:45 -0700)]
arch: Get rid of the unused type AnyReg.
This type is defined for all the ISAs but isn't used by anything.
Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Adrien Pesle [Fri, 12 Oct 2018 10:42:33 +0000 (12:42 +0200)]
dev-arm: Don't panic when EOIR a non active PPI
GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.
Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Adrien Pesle [Thu, 11 Oct 2018 14:09:07 +0000 (16:09 +0200)]
dev-arm: Fix Gicv2 distributor group register
For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.
Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Thu, 11 Oct 2018 02:19:36 +0000 (19:19 -0700)]
systemc: Get rid of leftovers from unimplemented warnings past.
These warnings were removed when the functionality they warned about
was implemented, but there were some leftovers like unnecessary
includes and some helper functions which hid gem5 specific headers
from the ext directory.
Change-Id: Ic886ac0f1264687524e3a7b7eaab8836f318a5a2
Reviewed-on: https://gem5-review.googlesource.com/c/13398
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 11 Oct 2018 02:20:49 +0000 (19:20 -0700)]
systemc: Implement Object::simcontext().
Implement it as a nonstandard alias for the also non-standard
sc_get_curr_simcontext.
Change-Id: Ic9a51efa93f687e4b57d622247a5510136fab221
Reviewed-on: https://gem5-review.googlesource.com/c/13397
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 11 Oct 2018 02:03:58 +0000 (19:03 -0700)]
systemc: Stop filtering out warnings about unimplemented features.
These no longer cause any of the tests to break, so there's no reason
to filter them out.
Change-Id: I9c0b25fc42eb3060ac7d6d6a46ded130227c302d
Reviewed-on: https://gem5-review.googlesource.com/c/13396
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 11 Oct 2018 02:03:12 +0000 (19:03 -0700)]
systemc: Warn about using deprecated sc_port constructors.
This gets rid of one of the last instances of a warning about
unimplemented functionality.
Change-Id: I3d8e50ea45554cba969118ce873ed3d2b041ec43
Reviewed-on: https://gem5-review.googlesource.com/c/13395
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 10 Oct 2018 04:07:57 +0000 (21:07 -0700)]
systemc: Add a python config class for sc_modules.
This class doesn't really add anything, but it provides a consistent
base class for sc_modules vs. generic sc_objects.
Change-Id: I3fbd4f6b5d1be0b5419f5cbd304aec61d404a341
Reviewed-on: https://gem5-review.googlesource.com/c/13355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 23:22:47 +0000 (16:22 -0700)]
systemc: Don't include the scheduler in an external header file.
The scheduler is an internal detail and shouldn't be exposed to the
headers in ext. It would transitively include more headers which are
not in ext, making it not self contained.
Change-Id: I8384cde9d19363953ffd0c91e7d8d27f8f79a570
Reviewed-on: https://gem5-review.googlesource.com/c/13336
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 23:21:34 +0000 (16:21 -0700)]
systemc: Add an accessor for getting the current process.
This is to avoid having to expose the scheduler (which tracks the
current process) to header files which should be independent of gem5
and the underlying implementation.
Change-Id: I1b0810ab66c3ce52b5b94236d7df86da66a62472
Reviewed-on: https://gem5-review.googlesource.com/c/13335
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 06:08:27 +0000 (23:08 -0700)]
systemc: Don't re-schedule a process which is already scheduled.
Change-Id: I8e12713c49aad03d0bfb779883adcbfa8fd4b42e
Reviewed-on: https://gem5-review.googlesource.com/c/13334
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 05:39:36 +0000 (22:39 -0700)]
systemc: Fix accounting in the sc_fifo class.
Reads shouldn't free up space until an update happens.
Change-Id: I18e1601c27b44643f103c86f04b1fa2c23baf1e8
Reviewed-on: https://gem5-review.googlesource.com/c/13333
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 05:21:23 +0000 (22:21 -0700)]
systemc: Exclude a test which tests a feature we're not implementing.
Change-Id: Ieaca025786d70c0d851eec9d1eb9f7f01b513cde
Reviewed-on: https://gem5-review.googlesource.com/c/13332
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 9 Oct 2018 02:01:38 +0000 (19:01 -0700)]
systemc: Switch to using predefined messages for datatypes.
Create and use predefined messages for datatypes which match the ones
Accellera uses.
Change-Id: I92dd52f62462b864264217bb81f3ff1dcec020bf
Reviewed-on: https://gem5-review.googlesource.com/c/13331
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 12:23:49 +0000 (05:23 -0700)]
systemc: Switch to using predefined messages for channels.
Create and use predefined messages for channels which match the ones
Accellera uses.
Change-Id: I179214838bbd83604e50225926cdc6b5b1b16923
Reviewed-on: https://gem5-review.googlesource.com/c/13330
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 10:59:56 +0000 (03:59 -0700)]
systemc: Don't depend on the order of static initializers.
STL containers may need to be constructed before they're used. Don't
count on being able to insert into them during a static initializer.
Change-Id: Icb05d5084a470e1ebd976ae6e1954b1a78aabd6a
Reviewed-on: https://gem5-review.googlesource.com/c/13329
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 10:02:56 +0000 (03:02 -0700)]
systemc: Switch to using predefined messages for utils.
Create and use predefined messages for utils which match the ones
Accellera uses.
Change-Id: I932b7206fc16181d01a0d5b7441ce617b30e5365
Reviewed-on: https://gem5-review.googlesource.com/c/13328
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 08:51:25 +0000 (01:51 -0700)]
systemc: Remove a redundant error check.
If the check doesn't abort the port binding in progress, it will be
reported twice.
Change-Id: I691ebd0f1598193f861c6085341dcd2fb05dd210
Reviewed-on: https://gem5-review.googlesource.com/c/13327
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 08:38:41 +0000 (01:38 -0700)]
systemc: Check the maximum port size when finializing bindings.
Change-Id: Ie7d704547bb8523a3c44479a89d2af4fcce6e8b6
Reviewed-on: https://gem5-review.googlesource.com/c/13326
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 08:37:52 +0000 (01:37 -0700)]
systemc: Fix how the maximum size is computed for sc_ports.
Change-Id: I073eb16cbeb892f24ac3860daca056ed2fb09086
Reviewed-on: https://gem5-review.googlesource.com/c/13325
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 08:01:30 +0000 (01:01 -0700)]
systemc: Mark a test as expected to fail.
This test expects to exit with an error.
Change-Id: Id0b1ae4967ad0b8a356c7a04ed5fe9eb2f3c6641
Reviewed-on: https://gem5-review.googlesource.com/c/13324
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 07:42:04 +0000 (00:42 -0700)]
systemc: Switch to using predefined messages for core.
Create and use predefined messages for core which match the ones
Accellera uses.
Change-Id: I05b1398933f753946d5917f39d0f39c7cb45ed9f
Reviewed-on: https://gem5-review.googlesource.com/c/13323
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 07:34:35 +0000 (00:34 -0700)]
systemc: Add a mechanism for pre-registering message type ids.
These ids are the ones the Accellera implementation/tests use. Some of
the tests expect them to be available and usable.
Change-Id: I4e4dc3470c28d4113330a44ccd06ffe7724e75b1
Reviewed-on: https://gem5-review.googlesource.com/c/13322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 03:34:27 +0000 (20:34 -0700)]
systemc: Add a warning about dont_initialize and cthreads.
Change-Id: I7cc3e571a7a63eed383ad7f897342a539318f961
Reviewed-on: https://gem5-review.googlesource.com/c/13321
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 03:21:31 +0000 (20:21 -0700)]
systemc: Make suppress_id work like the test expects.
This is in contrast to how Accellera actually implements it, implying
they would fail their own test.
The specific difference is that suppress_id should only suppress
SC_INFO and SC_WARNING, not all severity levels like the Accellera
implementation will do.
Change-Id: I34f0d2d5912548963433a785cfa6ef88ad818042
Reviewed-on: https://gem5-review.googlesource.com/c/13320
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 03:09:42 +0000 (20:09 -0700)]
systemc: Handle integer based IDs like Accellera does.
This is actually not consistent with how it was handled in 2.0.1 which
is supposedly what this is supposed to be backwards compatible with,
in that in the earlier version on info and warning messages were
suppressed. This is exposed by one of the tests,
utils/sc_report/test01, which suppresses an integer ID and then reports
an error with it. The "golden" output shows the message supressed, but
the actual implementation makes no such distinction.
This implementation duplicates Accelleras for now, but a future change
will make it consistent with the old implementation so the test will
pass.
Change-Id: I8f959321151e2bb60b94000594f30531b80e2684
Reviewed-on: https://gem5-review.googlesource.com/c/13319
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 7 Oct 2018 02:00:56 +0000 (19:00 -0700)]
systemc: Refactor reporting to prep for int based messages.
There's a deprecated reporting mechanism based on integer message ids,
and the reporting mechanism needs to be refactored a bit to make it
easier to support.
Some bookkeeping data structures were moved out to somewhere they
can be accessed by other code, obviating the non-standard get_handler
function.
Change-Id: Id427cd79be9ef0f3275fbac39ff047ab672fb3e0
Reviewed-on: https://gem5-review.googlesource.com/c/13318
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 23:44:32 +0000 (16:44 -0700)]
systemc: Stop passing arguments to sc_main.
These arguments were originally just to make sure arguments could be
successfully passed to sc_main, but serve no intrinsic purpose. There
are some tests which can accept command line arguments to customize
how they run, and having nonsense arguments confuses them and makes
them behave incorrectly.
Change-Id: Ib328edb12e01a97dca778bbf45b10e91dd8c07a6
Reviewed-on: https://gem5-review.googlesource.com/c/13317
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 11:31:04 +0000 (04:31 -0700)]
systemc: When resetting a process, clear suspended ready.
When resetting a process which is ready pending coming out of suspend,
clear that state since the process is about to run in service of the
reset.
Change-Id: Iade3ec4b2f3eadd372cce456dca66850d37ed5fd
Reviewed-on: https://gem5-review.googlesource.com/c/13316
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 11:11:50 +0000 (04:11 -0700)]
systemc: Manually correct the golden output for a test.
The golden reference output for the test was to throw an error which
is clearly not at all related to the test (it was about immediate
self notifications while the test never calls any form of notify())
and which would happen significantly before the end of the test,
negating all the other behaviors and checks which would happen after
that point.
Since it strongly looks like the reference output was updated in error,
and because other very similarly structured tests are expected to run
silently except for printing "Success" at the end (which it does when
run under gem5), this change manually updates the golden reference
output to reflect what appears to be correct.
Change-Id: I9cde81c28774049653d60f1ffd37a2fae875b522
Reviewed-on: https://gem5-review.googlesource.com/c/13315
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 11:11:00 +0000 (04:11 -0700)]
systemc: If a process hasn't started, still signal its reset event.
Change-Id: I9c8026cde455070841139d02955f5c083b9e0645
Reviewed-on: https://gem5-review.googlesource.com/c/13314
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 11:10:39 +0000 (04:10 -0700)]
systemc: Ignore attempts to throw a signal to a method.
Change-Id: I8c2b20525aa46955f4f2df34436b7424e706e410
Reviewed-on: https://gem5-review.googlesource.com/c/13313
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 09:58:02 +0000 (02:58 -0700)]
systemc: Remove a redundant injectException for Thread's throw_it.
For some reason lost to the sands of time, the throw_it function was
virtual for the Thread class, and that class would call the base
class's throw_it, and then also injectException itself. That would
result in the exception being injected into the thread twice which is
incorrect.
Since it's not clear what the original intention of this code was, the
throw_it function is now no longer virtual, and the one useful aspect
of it, a check if the process is already terminated, was moved into the
base class function.
Change-Id: I7fb14baa7728bd1e9206011870b6ccaa9c4e8c64
Reviewed-on: https://gem5-review.googlesource.com/c/13312
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 10:14:48 +0000 (03:14 -0700)]
systemc: Get rid of the unused Process::_procKind.
This seems to be a leftover from an earlier implementation.
Change-Id: I63d7e576fd3c11cf73769c34bbc97a4d3bbbdaeb
Reviewed-on: https://gem5-review.googlesource.com/c/13311
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 07:57:48 +0000 (00:57 -0700)]
systemc: Ignore immediate self notifications.
Change-Id: If5140bd86159e9257eb9e6ccb8301dd6349dacff
Reviewed-on: https://gem5-review.googlesource.com/c/13310
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Oct 2018 07:10:20 +0000 (00:10 -0700)]
systemc: Distinguish internal events from normal sc_events.
The internal events aren't supposed to show up in the namespace or as
children of objects.
Change-Id: Id04b9bfe2e1f8f216390dd989797558eaf33d715
Reviewed-on: https://gem5-review.googlesource.com/c/13309
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 23:55:20 +0000 (16:55 -0700)]
systemc: Mark a test as expected to fail.
Change-Id: Iec3b10b0251a7a343b81540f524427e98031577a
Reviewed-on: https://gem5-review.googlesource.com/c/13308
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 23:45:55 +0000 (16:45 -0700)]
systemc: Use the "catch action" and the handler func outside sc_main.
If an exception escapes sc_main, Accellera catches it and feeds it
into the report handler, telling it to run the catch actions. This
seems like it sets up lots of dangerous scenarios, and also makes a
vital error detecting path more complex and error prone.
On the other hand, it makes one of the tests pass.
Change-Id: I7f9d07e01e63c7abeee903febe2e434041ec49a4
Reviewed-on: https://gem5-review.googlesource.com/c/13307
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 23:45:29 +0000 (16:45 -0700)]
systemc: Change the default "catch action" to SC_DISPLAY.
There is a test which checks what it was and asserts if it's something
else.
Change-Id: I114c0a38c9fa69544416a4d1b555bb87e6246efd
Reviewed-on: https://gem5-review.googlesource.com/c/13306
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 23:24:18 +0000 (16:24 -0700)]
systemc: Add an error check to the deprecated notify_delayed.
This can't override pending notifications like normal notify does.
Change-Id: Ie5f12a97ffdcc3dfca20fa7852f89687ee8bfca3
Reviewed-on: https://gem5-review.googlesource.com/c/13305
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 23:12:11 +0000 (16:12 -0700)]
systemc: Add a range check to the intial value of sc_semaphore.
Change-Id: I4e1ef90b14074e5a2794a4386e411397213b2789
Reviewed-on: https://gem5-review.googlesource.com/c/13304
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 22:55:50 +0000 (15:55 -0700)]
systemc: Add some error checks to sc_clock.
The Accellera version reports an error if the period, high or low
portions of the clock are zero.
Change-Id: I2cbb7c3a1b6abe4d969ef875ebf8754d2d1c489a
Reviewed-on: https://gem5-review.googlesource.com/c/13303
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 22:38:23 +0000 (15:38 -0700)]
systemc: Add an error check to sc_gen_unique_name.
Accellera checks for a null pointer, and a test tries using that input.
Change-Id: I0f098f53de37ebbe481ea46e61fc0a9a404c29db
Reviewed-on: https://gem5-review.googlesource.com/c/13302
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 22:31:50 +0000 (15:31 -0700)]
systemc: Detach child events in the Object destructor.
This way they don't try to detach themselves from a parent object which
no longer exists.
Change-Id: Id4a3f3b2241cf8c67cae9b983bd4c1acbef083e3
Reviewed-on: https://gem5-review.googlesource.com/c/13301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 22:09:31 +0000 (15:09 -0700)]
systemc: Report an error if an sc_event_finder is used on an unbound port.
Rather than assuming the port is bound, check and report an error.
Change-Id: I4af89d104bc6de9932ff044740446833732d01d9
Reviewed-on: https://gem5-review.googlesource.com/c/13300
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 00:46:55 +0000 (17:46 -0700)]
systemc: Implement port binding policies.
Change-Id: I585e34c4a666103af16ff1675701b61122822b55
Reviewed-on: https://gem5-review.googlesource.com/c/13299
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 00:40:36 +0000 (17:40 -0700)]
systemc: Add some deprecated positional binding operators.
These are used in one of the tests, specifically the comma operator. It
didn't cause compilation to fail because of the default meaning of the
comma.
Change-Id: I7ce7fe74f02d4ad6a4ab896a2f0d6bd1ce635c2f
Reviewed-on: https://gem5-review.googlesource.com/c/13298
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Oct 2018 00:45:34 +0000 (17:45 -0700)]
systemc: Keep track of progress when positionally binding.
Positionally binding more than once (like with the deprecated comma or
<< operators) should pick up where it left off the last time instead
of starting again from the beginning.
Change-Id: Ifc33520d6ce40544bd0ad80a5657b1a38a7914e4
Reviewed-on: https://gem5-review.googlesource.com/c/13297
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 23:41:32 +0000 (16:41 -0700)]
systemc: Fill out some error reporting in sc_port.
Rather than just asserting some invariants are true, report errors if
they aren't.
Change-Id: Id361b8a13011e1a75289ddddb6b41c1d09dbf794
Reviewed-on: https://gem5-review.googlesource.com/c/13296
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 22:58:55 +0000 (15:58 -0700)]
systemc: Run delta notifications in reverse insertion order.
This is sort of pointless, except that it matches Accellera's behavior.
Change-Id: Ia63f2de998157aa68ce36fdc2ba39ca7a80fecbe
Reviewed-on: https://gem5-review.googlesource.com/c/13295
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 21:59:28 +0000 (14:59 -0700)]
systemc: Change how signal based resets work.
The previous implementation used the value changed event to track when
signals changed value, but there were a couple problems with this
approach. First, this piggybacked on the sensitivity mechanism in some
ways, but diverged in others. The sensitivity didn't notify a process
when it was satisfied like other sensitivity types would, and it also
ignored whether the process was disabled.
Second, the value_changed_event is notified by a signal instance as a
delta notification, but reset signals are supposed to act immediately.
That means they should happen before all delta notifications, or in
other words all delta notifications should see the reset status of a
given process. That's particularly important in the case of wait(int n)
where setting the reset clears the reset count, and the count is
checked when determining whether or not to wake up a process when its
sensitivity is satisfied, potentially by a delta notification.
Third, by removing the middle man and not trying to repurpose the
sensitivity mechanism, the code gets simpler and easier to understand.
Change-Id: I0d05d11437291d368b060f6a45a207813615f113
Reviewed-on: https://gem5-review.googlesource.com/c/13294
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 02:02:53 +0000 (19:02 -0700)]
systemc: Increment the change stamp value before the timing phase.
It appears that events which are triggered during the timing phase
are considered triggered in the following evaluation phase. The
"triggered()" function on events is non-standard and not really
explained anywhere, but this appears to work in practice.
Change-Id: I2574dc4569bf148c55fbe2a4873d458fc507f2a5
Reviewed-on: https://gem5-review.googlesource.com/c/13293
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 00:37:53 +0000 (17:37 -0700)]
systemc: Add a simple implementation for sc_mempool.
This class is supposed to be a more efficient way to manage small bits
of memory. At least for now, new and delete will do the same job
functionally. Also, the heap manager may be just as efficient as
whatever custom mechanism sc_mempool would use.
Change-Id: I6fdc01a69ca017d94b14a15a196ad29b66ef9858
Reviewed-on: https://gem5-review.googlesource.com/c/13292
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Oct 2018 00:08:15 +0000 (17:08 -0700)]
systemc: Add an sc_gen_unique_name namespace to processes as well.
The standard says that there are namespaces for each module, and
one global namespace. Accellera also has namespaces for each process,
which shows up in the test output.
Change-Id: I4c8c5cecd5fb685d7bab521d9ae131aef23a6ab4
Reviewed-on: https://gem5-review.googlesource.com/c/13291
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 3 Oct 2018 23:24:10 +0000 (16:24 -0700)]
systemc: Add some error checks to the sc_module constructor.
These match error checks which are already in, for instance, the
sc_port constructor.
Change-Id: I8dfb4ce37bf0e59c6fa879f0afda5112af78b40b
Reviewed-on: https://gem5-review.googlesource.com/c/13290
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 3 Oct 2018 23:17:50 +0000 (16:17 -0700)]
systemc: Change how errors are handled in some constructors slightly.
Because SC_REPORT_ERROR usually causes an exception to be thrown, it's
easy to assume it will be the last thing executed in a function. It
might, however, be set up to do nothing, in which case the function
will continue to execute.
This change makes sure sc_prim will be set up properly even if errors
about the time a channel can be set up are ignored.
Also, if an exception is thrown while sc_port is being set up, the
corresponding Port object needs to be cleaned up. Rather than try to
intercept exceptions in the constructor and clean up properly, we'll
just make the allocation of the Port object be the last thing it does.
If the function exits early, then the Port pointer will still be
nullptr and nothing will need to be done.
Change-Id: If8f6f6b7e6830235fee3cd75625240b99e87dfbe
Reviewed-on: https://gem5-review.googlesource.com/c/13289
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 3 Oct 2018 23:16:08 +0000 (16:16 -0700)]
systemc: Add an sc_gem5::Port destructor.
This destructor just removes the port from the list of all ports.
Change-Id: I809b529540c2946d20aeb8d64467d77dc94a7a96
Reviewed-on: https://gem5-review.googlesource.com/c/13288
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 3 Oct 2018 23:14:41 +0000 (16:14 -0700)]
systemc: Change the point where elaboration is considered over.
Make it the end of "before_end_of_elaboration" rather than the end
of "end_of_elaboration". This interpretation fits the behavior expected
by some of the tests.
Change-Id: I3f589147834ab5d5dc8c0e9b4849dd00491c5848
Reviewed-on: https://gem5-review.googlesource.com/c/13287
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>