Andrew Zonenberg [Fri, 11 Aug 2017 23:16:25 +0000 (16:16 -0700)]
Fixed handling of cell ports that aren't wires
Andrew Zonenberg [Fri, 11 Aug 2017 22:07:27 +0000 (15:07 -0700)]
opt_rmports: Fixed incorrect handling of multi-bit nets
Andrew Zonenberg [Fri, 11 Aug 2017 20:46:01 +0000 (13:46 -0700)]
Removed commented out debug code
Andrew Zonenberg [Fri, 11 Aug 2017 20:40:37 +0000 (13:40 -0700)]
Added opt_rmports pass (remove unconnected ports from top-level modules)
Clifford Wolf [Wed, 9 Aug 2017 11:29:52 +0000 (13:29 +0200)]
Add support for set-reset cell variants to opt_rmdff
Clifford Wolf [Wed, 9 Aug 2017 11:28:52 +0000 (13:28 +0200)]
Auto-detect JSON front-end
Clifford Wolf [Sun, 6 Aug 2017 11:27:18 +0000 (13:27 +0200)]
Add handling of constant reset signals to opt_rmdff
Clifford Wolf [Fri, 4 Aug 2017 15:09:08 +0000 (17:09 +0200)]
Add "yosys-smtbmc --smtc-init --smtc-top --noinit"
Clifford Wolf [Fri, 4 Aug 2017 09:24:58 +0000 (11:24 +0200)]
Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"
Clifford Wolf [Sat, 29 Jul 2017 14:21:58 +0000 (16:21 +0200)]
Fix typo in "abc" pass help message
Clifford Wolf [Fri, 28 Jul 2017 22:07:02 +0000 (00:07 +0200)]
Add merging of "past FFs" to verific importer
Clifford Wolf [Fri, 28 Jul 2017 21:11:52 +0000 (23:11 +0200)]
Add consolidation of init attributes to opt_clean, some opt_clean log fixes
Clifford Wolf [Fri, 28 Jul 2017 15:37:09 +0000 (17:37 +0200)]
Add minimal support for PSL in VHDL via Verific
Clifford Wolf [Fri, 28 Jul 2017 13:33:30 +0000 (15:33 +0200)]
Add simple VHDL+PSL example
Clifford Wolf [Fri, 28 Jul 2017 13:32:54 +0000 (15:32 +0200)]
Improve Verific HDL language options
Clifford Wolf [Fri, 28 Jul 2017 09:31:27 +0000 (11:31 +0200)]
Fix handling of non-user-declared Verific netbus
Clifford Wolf [Thu, 27 Jul 2017 12:05:09 +0000 (14:05 +0200)]
Improve Verific SVA importer
Clifford Wolf [Thu, 27 Jul 2017 10:37:16 +0000 (12:37 +0200)]
Add counter.sv SVA test
Clifford Wolf [Thu, 27 Jul 2017 10:17:04 +0000 (12:17 +0200)]
Add log_warning_noprefix() API, Use for Verific warnings and errors
Clifford Wolf [Thu, 27 Jul 2017 09:54:45 +0000 (11:54 +0200)]
Add "verific -import -n" and "verific -import -nosva"
Clifford Wolf [Thu, 27 Jul 2017 09:42:05 +0000 (11:42 +0200)]
Improve SVA tests, add Makefile and scripts
Clifford Wolf [Thu, 27 Jul 2017 09:40:07 +0000 (11:40 +0200)]
Improve Verific SVA import: negedge and $past
Clifford Wolf [Thu, 27 Jul 2017 08:39:39 +0000 (10:39 +0200)]
Improve Verific SVA importer
Clifford Wolf [Wed, 26 Jul 2017 16:28:55 +0000 (18:28 +0200)]
Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
Clifford Wolf [Wed, 26 Jul 2017 16:00:01 +0000 (18:00 +0200)]
Improve Verific bindings (mostly related to SVA)
Clifford Wolf [Tue, 25 Jul 2017 13:13:22 +0000 (15:13 +0200)]
Improve "help verific" message
Clifford Wolf [Tue, 25 Jul 2017 12:53:11 +0000 (14:53 +0200)]
Add "verific -extnets"
Clifford Wolf [Tue, 25 Jul 2017 12:52:34 +0000 (14:52 +0200)]
Add "using std::get" to yosys.h
Clifford Wolf [Tue, 25 Jul 2017 11:33:25 +0000 (13:33 +0200)]
Improve "verific -all" handling
Clifford Wolf [Mon, 24 Jul 2017 11:57:16 +0000 (13:57 +0200)]
Add "verific -import -d <dump_file"
Clifford Wolf [Mon, 24 Jul 2017 09:29:06 +0000 (11:29 +0200)]
Add "verific -import -flatten" and "verific -import -v"
Clifford Wolf [Sat, 22 Jul 2017 14:35:46 +0000 (16:35 +0200)]
Add more SVA test cases for future Verific work
Clifford Wolf [Sat, 22 Jul 2017 14:16:44 +0000 (16:16 +0200)]
Add "verific -import -k"
Clifford Wolf [Sat, 22 Jul 2017 13:08:30 +0000 (15:08 +0200)]
Add error for cell output ports that are connected to constants
Clifford Wolf [Sat, 22 Jul 2017 10:31:08 +0000 (12:31 +0200)]
Add some simple SVA test cases for future Verific work
Clifford Wolf [Sat, 22 Jul 2017 09:58:51 +0000 (11:58 +0200)]
Improve docs for verific bindings, add simply sby example
Clifford Wolf [Fri, 21 Jul 2017 17:32:31 +0000 (19:32 +0200)]
Fix handling of empty cell port assignments (i.e. ignore them)
Clifford Wolf [Fri, 21 Jul 2017 14:21:04 +0000 (16:21 +0200)]
Fix "read_blif -wideports" handling of cells with wide ports
Clifford Wolf [Fri, 21 Jul 2017 12:34:53 +0000 (14:34 +0200)]
Add a paragraph about pre-defined macros to read_verilog help message
Clifford Wolf [Fri, 21 Jul 2017 12:33:29 +0000 (14:33 +0200)]
Add verilator support to testbenches generated by yosys-smtbmc
Clifford Wolf [Tue, 18 Jul 2017 15:38:19 +0000 (17:38 +0200)]
Change intptr_t to uintptr_t in hashlib.h
Clifford Wolf [Tue, 18 Jul 2017 13:21:12 +0000 (15:21 +0200)]
Merge pull request #363 from rqou/master
Miscellaneous build tweaks
Robert Ou [Mon, 17 Jul 2017 21:21:59 +0000 (14:21 -0700)]
makefile: Add the option to use libtermcap
Robert Ou [Mon, 17 Jul 2017 19:36:43 +0000 (12:36 -0700)]
Fix build warnings for win64
Win64 has a 32-bit long. Use intptr_t to work on any data model.
Clifford Wolf [Fri, 14 Jul 2017 09:32:49 +0000 (11:32 +0200)]
Add $alu to list of supported cells for "stat -width"
Clifford Wolf [Wed, 12 Jul 2017 13:57:04 +0000 (15:57 +0200)]
Generate FSM-style testbenches in smtbmc
Clifford Wolf [Tue, 11 Jul 2017 15:45:29 +0000 (17:45 +0200)]
Fix the fixed handling of x-bits in EDIF back-end
Clifford Wolf [Tue, 11 Jul 2017 15:38:19 +0000 (17:38 +0200)]
Fix handling of x-bits in EDIF back-end
Clifford Wolf [Mon, 10 Jul 2017 11:17:38 +0000 (13:17 +0200)]
Add attributes and parameter support to JSON front-end
Clifford Wolf [Mon, 10 Jul 2017 10:09:05 +0000 (12:09 +0200)]
Add techlibs/xilinx/lut2lut.v
Clifford Wolf [Sat, 8 Jul 2017 14:40:40 +0000 (16:40 +0200)]
Add JSON front-end
Clifford Wolf [Fri, 7 Jul 2017 09:52:25 +0000 (11:52 +0200)]
Change s/asserts/assertions/ in yosys-smtbmc log messages
Clifford Wolf [Fri, 7 Jul 2017 00:47:30 +0000 (02:47 +0200)]
Add "yosys-smtbmc --presat"
Clifford Wolf [Wed, 5 Jul 2017 12:23:54 +0000 (14:23 +0200)]
Fix generation of multiple outputs for same AIG node in write_aiger
Clifford Wolf [Wed, 5 Jul 2017 10:13:53 +0000 (12:13 +0200)]
Add write_table command
Clifford Wolf [Tue, 4 Jul 2017 18:01:30 +0000 (20:01 +0200)]
Add Verific Release information to log
Clifford Wolf [Mon, 3 Jul 2017 17:38:30 +0000 (19:38 +0200)]
Fix some c++ clang compiler errors
Clifford Wolf [Mon, 3 Jul 2017 17:35:40 +0000 (19:35 +0200)]
Apply minor coding style changes to coolrunner2 target
Clifford Wolf [Mon, 3 Jul 2017 17:33:36 +0000 (19:33 +0200)]
Merge pull request #352 from rqou/master
Initial Coolrunner-II support
Clifford Wolf [Mon, 3 Jul 2017 17:33:25 +0000 (19:33 +0200)]
Merge pull request #356 from set-soft/clean-test
Added the test outputs to the clean target
Clifford Wolf [Mon, 3 Jul 2017 17:31:59 +0000 (19:31 +0200)]
Merge pull request #355 from set-soft/exclude_TBUF_merge
Excluded $_TBUF_ from opt_merge pass
Salvador E. Tropea [Mon, 3 Jul 2017 16:33:11 +0000 (13:33 -0300)]
Added the test outputs to the clean target
Salvador E. Tropea [Mon, 3 Jul 2017 16:21:20 +0000 (13:21 -0300)]
Excluded $_TBUF_ from opt_merge pass
Clifford Wolf [Mon, 3 Jul 2017 13:37:17 +0000 (15:37 +0200)]
Remove unneeded delays in smtbmc vlogtb
Clifford Wolf [Mon, 3 Jul 2017 12:53:17 +0000 (14:53 +0200)]
Include output ports with constant driver in AIGER output
Clifford Wolf [Sat, 1 Jul 2017 16:19:23 +0000 (18:19 +0200)]
Add "yosys-smtbmc --vlogtb-top"
Clifford Wolf [Sat, 1 Jul 2017 14:05:26 +0000 (16:05 +0200)]
Fix and_or_buffer optimization in opt_expr for signed operators
Clifford Wolf [Sat, 1 Jul 2017 00:13:32 +0000 (02:13 +0200)]
Fix smtbmc vlogtb bug in $anyseq handling
Clifford Wolf [Fri, 30 Jun 2017 16:52:52 +0000 (18:52 +0200)]
Add "design -import"
Clifford Wolf [Fri, 30 Jun 2017 15:57:34 +0000 (17:57 +0200)]
Add chtype command
Clifford Wolf [Fri, 30 Jun 2017 15:44:44 +0000 (17:44 +0200)]
Add $tribuf to opt_merge blacklist
Clifford Wolf [Tue, 27 Jun 2017 17:18:32 +0000 (19:18 +0200)]
Merge pull request #353 from azonenberg/master
greenpak4_counters: Use more human-readable names for inferred counters
Robert Ou [Mon, 26 Jun 2017 06:56:16 +0000 (23:56 -0700)]
coolrunner2: Add a few more primitives
These cannot be inferred yet, but add them to cells_sim.v for now
Robert Ou [Mon, 26 Jun 2017 03:58:45 +0000 (20:58 -0700)]
coolrunner2: Initial mapping of latches
Robert Ou [Mon, 26 Jun 2017 03:16:43 +0000 (20:16 -0700)]
coolrunner2: Initial mapping of DFFs
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
Robert Ou [Sun, 25 Jun 2017 09:56:45 +0000 (02:56 -0700)]
coolrunner2: Remove redundant INVERT_PTC
Robert Ou [Sun, 25 Jun 2017 09:44:03 +0000 (02:44 -0700)]
coolrunner2: Remove debug prints
Robert Ou [Sun, 25 Jun 2017 09:42:36 +0000 (02:42 -0700)]
coolrunner2: Correctly handle $_NOT_ after $sop
Robert Ou [Sun, 25 Jun 2017 09:20:42 +0000 (02:20 -0700)]
coolrunner2: Also construct the XOR cell in the macrocell
Robert Ou [Sat, 24 Jun 2017 15:51:24 +0000 (08:51 -0700)]
coolrunner2: Initial techmapping for $sop
Andrew Zonenberg [Sat, 24 Jun 2017 21:54:07 +0000 (14:54 -0700)]
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
Robert Ou [Sat, 24 Jun 2017 13:59:20 +0000 (06:59 -0700)]
coolrunner2: Initial commit
Clifford Wolf [Tue, 20 Jun 2017 13:32:23 +0000 (15:32 +0200)]
Fix handling of init values in "abc -dff" and "abc -clk"
Clifford Wolf [Tue, 20 Jun 2017 03:26:12 +0000 (05:26 +0200)]
Fix history namespace collision
Clifford Wolf [Tue, 20 Jun 2017 02:41:58 +0000 (04:41 +0200)]
Store command history when terminating with an error
Clifford Wolf [Tue, 20 Jun 2017 02:22:34 +0000 (04:22 +0200)]
Switched abc "clock domain not found" error to log_cmd_error()
Clifford Wolf [Wed, 7 Jun 2017 10:30:24 +0000 (12:30 +0200)]
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
Clifford Wolf [Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)]
Fix handling of Verilog ~& and ~| operators
Clifford Wolf [Wed, 31 May 2017 09:55:37 +0000 (11:55 +0200)]
Update ABC to hg rev
efbf7f13ea9e
Clifford Wolf [Wed, 31 May 2017 09:45:58 +0000 (11:45 +0200)]
Add dff2ff.v techmap file
Clifford Wolf [Tue, 30 May 2017 17:09:11 +0000 (19:09 +0200)]
Fix AIGER back-end for multiple symbols per input/latch/output/property
Clifford Wolf [Sun, 28 May 2017 09:59:05 +0000 (11:59 +0200)]
Add "setundef -anyseq"
Clifford Wolf [Sun, 28 May 2017 09:31:35 +0000 (11:31 +0200)]
Improve write_aiger handling of unconnected nets and constants
Clifford Wolf [Sat, 27 May 2017 09:56:01 +0000 (11:56 +0200)]
Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
Clifford Wolf [Wed, 24 May 2017 09:39:05 +0000 (11:39 +0200)]
Add aliases for common sets of gate types to "abc -g"
Clifford Wolf [Tue, 23 May 2017 16:38:20 +0000 (18:38 +0200)]
Add examples/osu035
Clifford Wolf [Tue, 23 May 2017 16:24:27 +0000 (18:24 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Tue, 23 May 2017 12:07:30 +0000 (14:07 +0200)]
Merge pull request #346 from azonenberg/master
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
Andrew Zonenberg [Tue, 23 May 2017 02:39:55 +0000 (19:39 -0700)]
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
Clifford Wolf [Wed, 17 May 2017 19:07:54 +0000 (21:07 +0200)]
Add workaround for CBMC bug to SimpleC back-end