lima: add layer_stride field to lima_resource struct

Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>

lima: fix stride in texture descriptor

Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>

intel/compiler: Report the number of non-spill/fill SEND messages on vec4 too

This make shader-db's report.py work on Haswell and earlier platforms.
The problem is that the script would detect the "sends" output for
scalar shaders and expect in in vec4 shaders too.  When it didn't find
it, the script would fail with:

    Traceback (most recent call last):
      File "./report.py", line 351, in <module>
        main()
      File "./report.py", line 182, in main
        before_count = before[p][m]
    KeyError: 'sends'

Fixes: f192741ddd8 ("intel/compiler: Report the number of non-spill/fill SEND messages")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: fix couple of compile warnings

Fixes "warning: braces around scalar initializer" warnings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: Fix timeout handling in syncobj wait.

libdrm returns -errno instead of directly the ioctl ret of -1.

Fixes: 1c3cda7d277 "radv: Add syncobj signal/reset/wait to winsys."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nv50/ir: mark STORE destination inputs as used

Observed an issue when looking at the code generatedy by the
image-vertex-attrib-input-output piglit test. Even though the test
itself worked fine (due to TIC 0 being used for the image), this needs
to be fixed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

gm107/ir: fix loading z offset for layered 3d image bindings

Unfortuantely we don't know if a particular load is a real 2d image (as
would be a cube face or 2d array element), or a layer of a 3d image.
Since we pass in the TIC reference, the instruction's type has to match
what's in the TIC (experimentally). In order to properly support
bindless images, this also can't be done by looking at the current
bindings and generating appropriate code.

As a result all plain 2d loads are converted into a pair of 2d/3d loads,
with appropriate predicates to ensure only one of those actually
executes, and the values are all merged in.

This goes somewhat against the current flow, so for GM107 we do the OOB
handling directly in the surface processing logic. Perhaps the other
gens should do something similar, but that is left to another change.

This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS
tests like shader_image_load_store.non-layered_binding without breaking
anything else.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "20.0" <mesa-stable@lists.freedesktop.org>

intel/dev: set default num_eu_per_subslice on gen12

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

docs/new_features: Empty the feature list for the 20.0 cycle

Bump VERSION to 20.0.0-devel

docs/relnotes/new_features.txt: Add note about gen12 support

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/validate/gen12: Add TGL to eu_validate tests.

These reworks were combined into this patch:

 * Matt Turner: i965: Disable NoDDChk/NoDDClr test on Gen12+
 * Francisco Jerez: intel/eu/validate/gen12: Disable
   qword_low_power_no_depctrl eu_validate test.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/dev: Add preliminary device info for Tigerlake

Reworks:
 * adjust 64-bit support, hiz (Jason Ekstrand)
 * sim-id (Lionel Landwerlin)
 * adjust threads, urb size (Rafael Antognolli)
 * adjust urb size (Kenneth Graunke)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/dump_gpu: handle context create extended ioctl

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

radv: Allocate space for temp. semaphore parts.

Calculated the number for allocation and did not
reserve space ....

Fixes: 2117c53b723 "radv: Add temporary datastructure for submissions."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

anv: Add Tile Cache Flush for Unified Cache.

blorp: Add Tile Cache Flush for Unified Cache.

iris: Add Tile Cache Flush for Unified Cache.

intel/genxml: Add gen12 tile cache flush bit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

aco: implement VGPR spilling

VGPR spilling is implemented via MUBUF instructions and scratch memory.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: always set scratch_offset in startpgm

This patch also moves private_segment_buffer and
scratch_offset to Program to easily access it.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: omit linear VGPRs as spill variables

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: ensure that spilled VGPR reloads are done after p_logical_start

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: simplify calculation of target register pressure when spilling

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix new_demand calculation for first instructions

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: don't add interferences between spilled phi operands

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: consider loop_exit blocks like merge blocks, even if they have only one predecessor

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: don't insert the exec mask into set of live-out variables when spilling

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix transitive affinities of spilled variables

Variables spilled on both branch legs need to be assigned to the same spilling slot.
These affinities can be transitive through multiple merge blocks.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix live-range splits of phis

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: remove potential critical edge on loops.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: improve live variable analysis

This patch makes the live variable analysis more precise
w.r.t. killed phi operands and the block's register pressure.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: Lower to CSSA

Converting to 'Conventional SSA Form' ensures correctness w.r.t. spilling of phi nodes.
Previously, it was possible that phi operands have intersecting live-ranges, and thus,
couldn't get spilled to the same spilling slot. For this reason, ACO tried to avoid to
spill phis, even if it was beneficial.
This patch implements a conversion pass which is currently only called if spilling is necessary.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

etnaviv: fix non-pointsprite points on GC7000L

Fixes these deqp tests (and more):
dEQP-GLES2.functional.draw.draw_arrays.points.single_attribute
dEQP-GLES2.functional.draw.draw_arrays.points.multiple_attributes
dEQP-GLES2.functional.draw.draw_arrays.points.default_attribute
dEQP-GLES2.functional.draw.draw_elements.points.single_attribute
dEQP-GLES2.functional.draw.draw_elements.points.multiple_attributes
dEQP-GLES2.functional.draw.draw_elements.points.default_attribute

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: stencil fix

The final version of previous stencil fix patch ended up breaking one-sided
stencil.

Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L):
dEQP-GLES2.functional.fragment_ops.depth_stencil.*

Note: deqp tests require --deqp-gl-config-name=rgba8888d24s8ms0

Fixes: 05da025f ("etnaviv: fix two-sided stencil")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: fix depth bias

Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L):
dEQP-GLES2.functional.polygon_offset.*

Fixes: 6c3c05dc ("etnaviv: fix polygon offset")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

iris: Set MOCS for external surfaces to uncached

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Align fast clear color state buffer to a page.

On gen11 and older, compressed images are tiled and aligned to 4K. On
gen12 this 4K alignment restriction was removed. However, only aligning
the fast clear color buffer to 64B (a cacheline, as it's on the
documentation) is causing some bugs where the fast clear color is not
converted during the fast clear operation. Aligning things to 4K seems
to fix it.

v2: Fix typo case in the comment (Nanley)
v3: Rebase and fix conflicts.
v4: Fix rebase mistake (Nanley).

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv: Align fast clear color state buffer to a page.

On gen11 and older, compressed images are tiled and aligned to 4K. On
gen12 this 4K alignment restriction was removed. However, only aligning
the fast clear color buffer to 64B (a cacheline, as it's on the
documentation) is causing some bugs where the fast clear color is not
converted during the fast clear operation. Aligning things to 4K seems
to fix it.

v2: Assert that image->planes[plane].offset is 4K aligned (Nanley)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

zink: only enable KHR_external_memory_fd if supported

While we're at it, make sure we error out if it's not supported when
required.

This brings us a bit closer to being able to test on SwiftShader, which
doesn't currently support KHR_external_memory_fd.

radv: Start signalling semaphores in WSI acquire.

Winsys semaphores without signal operation get silently ignored.

Not so for syncobjs, so actually signal them.

Fixes: 84d9551b232 "radv: Always enable syncobj when supported for all fences/semaphores."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2030
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

aco: rename README to README.md

Closes: #1974
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>

aco: a couple loop handling fixes for GFX10 hazard pass

It was joining from the wrong blocks and block.kind is a bitmask instead
of an enum.

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

intel/compiler: Add instruction compaction support on Gen12

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/compiler: Make separate src0/src1 index tables

TGL uses different data (and even a different format!) for each source.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/compiler: Inline get_src_index()

TGL will have separate tables for src0 and src1, so the shared function
will no longer make sense.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/compiler: Restructure instruction compaction in preparation for Gen12

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/compiler: Remove unreachable() from brw_reg_type.c

The EU compaction unit test fuzzes the compaction code by flipping bits.
We use a simple skip_bits() function with a list of reserved bits to
ignore, but for more complex cases like invalid combinations of register
file:type, we need either machinery to check validity or for these
functions to simply inform us whether a combination was valid.

enum brw_reg_type a 4-bit field in brw_reg, so rather than expanding it
with an "INVALID" value, just return -1 and let the caller check for
that.

Scott suggested redefining unreachable() within the unit test to
longjmp() which would allow driver code like this to still use it and
allow the test to handle expected failures like this. If that plan works
out, I plan to revert this.

freedreno/a2xx: add missing vertex formats (SSCALE/USCALE/FIXED)

Mostly for vertex formats, but they are supported as texture formats too
(untested however).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>

radeonsi: disable sdma for gfx10

Disable sdma on gfx10 until all timeouts bugs are fixed.

See:
    https://gitlab.freedesktop.org/mesa/mesa/issues/1907
    https://bugs.freedesktop.org/show_bug.cgi?id=111481

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: sdma misc fixes

SDMA IB doesn't need to be padded for SDMA.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: align sdma byte count to dw

If src/dst addresses are dw aligned and size is > 4 then we align
byte count to dw as well.

PAL implementation works like this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: Enable ACO on Navi.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: enable 8K video decode support for HEVC and VP9

HW 8K decode support starts at Renoir

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>

radeon/vcn: Add VP9 8K decode support

Require increase of context buffer size

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>

aco: try to group together VMEM loads of the same resource

v2: remove accidental shaderInt16 change
v2: simplify can_move_down initialization
v2: simplify VMEM_CLAUSE_MAX_GRAB_DIST

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: don't schedule instructions through depending VMEM instructions

Previously, the scheduler tried to move up instructions from below depending
VMEM instructions only to move them down again when scheduling the VMEM
instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: add can_reorder flags to load_ubo and load_constant

These got lost due to some refactoring.
Due to the way our scheduler works currently, for now
we add back the reorder flag for divergent loads only.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: only skip RAR dependencies if the variable is killed somewhere

This patch changes VMEM scheduling in a way that they can only
be moved upwards by previous VMEM instructions but not downwards.
This way, it improves the order of VMEM instructions in relation
to their users.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: restrict scheduling depending on max_waves

Previously, we allowed all shaders to reduce the number of max_waves to as low as 5.
Restricting this on shaders with low register demand, increases the total number of waves
while the VMEM def-use distances hardly change.
This patch also changes the max number of move operations per MEM instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

anv: Avoid emitting UBO surface states that won't be used

This shaves around 4-5% off of a CPU-limited example running with the
Dawn WebGPU implementation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/vec4: Set brw_stage_prog_data::has_ubo_pull

In 0e4a75f917, Ken added a flag brw_stage_prog_data which indicates
whether any UBO pulls ever occur.  Unfortunately, he neglected to set
the bit in the vec4 back-end.  This was fine at the time because the
optimization was intended for iris which does not support gen7 and using
the vec4 back-end on Gen8+ requires an environment variable.  We want to
use this in Vulkan which does support Gen7 so we want the information
from the vec4 back-end as well as scalar.

Fixes: 0e4a75f917 "intel/compiler: Record whether any pull constant..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: fix perftest options

RADV_PERFTEST=outooforder has been removed a while ago. This fixes
dumping the options into hang reports.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: move nomemorycache debug option at the right palce

Fixes: 6571000071d ("radv: add debug option to turn off in memory cache")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix dumping SPIR-V into hang reports

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa: enable ARB_gpu_shader_int64 in compat profile

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: add [Program]Uniform*64ARB display list support

This is required for int64 to be enabled in compat profile.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: Enable VK_KHR_timeline_semaphore.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Add wait-before-submit support for timelines.

This is actually a non-threaded implementation. I'd summarize this
as event-based submission.

When submit happens we walk a tree of submissions that depend on
the syncobj signal operations to be submitted and if those submission
we no other dependencies we start to execute them immediately.

Or, well I still use a list to avoid issues with long chains and
the stacksize when using recursion.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Add timelines with a VK_KHR_timeline_semaphore impl.

This does not fully do wait-before-submit, to be done in a follow
up patch.

For kernels without support for timeline syncobjs, this adds an
implementation of non-shareable timelines using legacy syncobjs.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Add temporary datastructure for submissions.

So we can defer them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Split semaphore into two parts as enum+union.

This is in preparation to adding more types.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Always enable syncobj when supported for all fences/semaphores.

This simplifies code for timeline semaphores by needing to support
less configurations.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Improve fence signalling in QueueSubmit.

Only signalling it once.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Do sparse binding in queue submission.

So we have one place to do queue things if we end up deferring
submissions.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Split out commandbuffer submission.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Clean up unused variable.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Add an early exit in the secure compile if we already have the cache entries.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: Compute hashes in secure process for secure compilation.

To prevent poisoning arbitrary cache entries.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

zink: drop nop descriptor-updates

If there's nothing to be done, let's actually do nothing. Seems like a
good idea.

Reviewed-by: Dave Airlie <airlied@redhat.com>

zink: use bitfield for dirty flagging

Bitfields are a bit more ideomatic than explicit flags, and harder to
get wrong.

Reviewed-by: Dave Airlie <airlied@redhat.com>

zink: use dynamic state for line-width

This will lead to fewer pipelines in the cache, which is assumed to
become our most unavoidable performance bottle-neck down the line.

Reviewed-by: Dave Airlie <airlied@redhat.com>

zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

gitlab-ci: Disable meson-windows job for the time being

It needs a CI runner carrying the mesa-windows tag, but there's none
available currently.

radv: make use of radv_sc_read()

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_sc_read() helper

This is a function with timeout support for reading from the pipe
between processes used for secure compile.

Initially we hardcode the timeout to 5 seconds. We can adjust the
timeout limit in future if needed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: allow select() calls in secure compile

This will be used in the following patch to support timeouts for
reading the pipe between processes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mapi: Improve the x86 tsd stubs performance.

This skips touching %ebx most times and it shows that glGetString performance
increased from 114M/s to 120M/s on my desktop.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>

mapi: Inline call x86_current_tls.

This saves one return and a simple benchmark which calls glGetString
repeatedly on my desktop shows it improves calls per second from 123M
to 141M.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1997
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>

mapi: Clean up entry_patch_public for x86 tls

Remove hard coded 16 and use entry_generate_or_patch to patch
public stubs. The generated code actually is sightly tighter
than before since the "nop" instructions before the final "jmp"
get removed.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>

mapi: split entry_generate_or_patch for x86 tls

The code works exactly the same with before. Just split this function
out so we can reuse it.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>

mapi: Adapted libglvnd x86 tsd changes

The x86 assembly language stub in src/mapi/entry_x86_tsd.h does not
generate PIC (position-independent code). This causes text relocations
which bring troubles on recent versions of FreeBSD, OpenBSD, Android.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108541
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>

spirv: Don't fail if multiple ordering semantics bits are set

Vulkan requires that only one bit for the ordering is set, but old
versions of GLSLang just set all the bits.  This was fixed as part of
https://github.com/KhronosGroup/glslang/commit/c51287d744fb6e7e9ccc09f6f8451e6c64b1dad6
but we can still find older versions (or shaders compiled with it)
around.

So instead of failing, emit a warning and fallback to the effective
result of any combination of multiple bits: AcquireRelease.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2018
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/isl: Allow stencil buffer to support compression on Gen12+

v2: (Nanley Chery)
- Fix commit title
- Fix comment

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Resolve stencil resource prior to copy or used by CPU

v2: Decide aux usage in get_copy_region_aux_settings (Nanley Chery)

v3: Use isl_surf_usage_is_stencil function (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Prepare resources before stencil blit operation

We have to resolve destination surfaces if we are bliting to and from
the same surface.

v2: Revert unrelated change (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Prepare depth resource if clear_depth enable

Avoid preparing depth resource, if we did fast depth clear before.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Prepare stencil resource before clear depth stencil

Let aux surface state tracker track the stencil buffer's aux state while
clearing depth stencil buffer.

v2: Fix condition check (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Resolve stencil buffer lossless compression with WM_HZ_OP packet

Even though stencil buffer compression looks like regular lossless color
compression w/o fast clear support, we have to resolve stencil buffer
with WM_HZ_OP packet.

v2: Check if resource is stencil with helper function (Nanley Chery)

v3: Remove unnecessary included file (Nanley Chery)

v4: (Nanley Chery)
- Avoid stencil buffer aux state transition by improving condition check

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/blorp: Set stencil resolve enable bit

When set, the stencil buffer is filled with the true stencil values and
we have to disable stencil buffer clear enable bit.

v2: 1) Refactor code little bit (Nanley Chery)
    2) Fix assertion (Nanley Chery)

v3: 1) Remove unncessary assignment (Nanley Chery)
    2) Fix GEN_GEN check (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>