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Sebastien Bourdeauducq [Fri, 27 Jan 2012 21:09:03 +0000 (22:09 +0100)]
Add on-chip SRAM
Sebastien Bourdeauducq [Sat, 21 Jan 2012 11:25:22 +0000 (12:25 +0100)]
Use meaningful class names
Sebastien Bourdeauducq [Fri, 20 Jan 2012 22:00:11 +0000 (23:00 +0100)]
Use new verilog.convert API
Sebastien Bourdeauducq [Fri, 13 Jan 2012 16:28:58 +0000 (17:28 +0100)]
Wishbone: omit fixed LSBs
Sebastien Bourdeauducq [Fri, 13 Jan 2012 16:07:46 +0000 (17:07 +0100)]
convtools -> tools
Sebastien Bourdeauducq [Thu, 5 Jan 2012 18:27:45 +0000 (19:27 +0100)]
Convert -> convert
Sebastien Bourdeauducq [Sun, 18 Dec 2011 21:02:05 +0000 (22:02 +0100)]
Use new syntax
Sebastien Bourdeauducq [Sat, 17 Dec 2011 23:29:37 +0000 (00:29 +0100)]
uart: new design using FHDL and bank (TX only, incomplete)
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:54:42 +0000 (15:54 +0100)]
32-device, 8-bit CSR bus
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:22:26 +0000 (15:22 +0100)]
norflash tb: use get_fragment
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:00:18 +0000 (15:00 +0100)]
Multiply system clock
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:00:11 +0000 (15:00 +0100)]
clkfx module
Sebastien Bourdeauducq [Fri, 16 Dec 2011 21:25:26 +0000 (22:25 +0100)]
Proper reset generation
Sebastien Bourdeauducq [Fri, 16 Dec 2011 20:30:22 +0000 (21:30 +0100)]
Support the new FHDL syntax
Sebastien Bourdeauducq [Fri, 16 Dec 2011 15:02:49 +0000 (16:02 +0100)]
Pay a bit more attention to PEP8
Sebastien Bourdeauducq [Tue, 13 Dec 2011 16:33:12 +0000 (17:33 +0100)]
Initial import
projects / litex.git / log