Alberto Gonzalez [Thu, 14 May 2020 17:07:59 +0000 (17:07 +0000)]
smtbmc: Fix return status handling.
Eddie Hung [Thu, 14 May 2020 16:45:54 +0000 (09:45 -0700)]
Merge pull request #2045 from YosysHQ/eddie/fix2042
verilog: error if no direction given for task arguments, default to input in SV mode
Claire Wolf [Thu, 14 May 2020 16:45:13 +0000 (18:45 +0200)]
Merge pull request #2052 from YosysHQ/claire/verific_memfix
Add support for non-power-of-two mem chunks in verific importer
Claire Wolf [Thu, 14 May 2020 16:31:16 +0000 (18:31 +0200)]
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
Claire Wolf [Thu, 14 May 2020 16:06:18 +0000 (18:06 +0200)]
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
ast: swap range regardless of range_left >= 0
Eddie Hung [Thu, 14 May 2020 15:36:36 +0000 (08:36 -0700)]
test: add another testcase as per @nakengelhardt
Claire Wolf [Thu, 14 May 2020 12:38:13 +0000 (14:38 +0200)]
Add support for non-power-of-two mem chunks in verific importer
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Eddie Hung [Thu, 14 May 2020 07:59:38 +0000 (00:59 -0700)]
opt_clean: improve warning message
Eddie Hung [Thu, 14 May 2020 07:26:23 +0000 (00:26 -0700)]
opt_clean: add init test
Eddie Hung [Thu, 14 May 2020 07:24:23 +0000 (00:24 -0700)]
opt_clean: rminit without -purge; also remove if consistent with const..
warn otherwise
Eddie Hung [Thu, 14 May 2020 07:19:58 +0000 (00:19 -0700)]
opt_clean: really make 'clean' identical to 'opt_clean' by rminit too
Eddie Hung [Wed, 13 May 2020 20:33:37 +0000 (13:33 -0700)]
verilog: default to input in sv mode if task/func has no dir ...
otherwise error
Eddie Hung [Wed, 13 May 2020 17:11:45 +0000 (10:11 -0700)]
tests: update/extend task argument tests
Eddie Hung [Tue, 12 May 2020 22:40:48 +0000 (15:40 -0700)]
ice40: fix ICESTORM_LC process sensitivity
Eddie Hung [Tue, 12 May 2020 22:40:13 +0000 (15:40 -0700)]
ice40: fix whitespace
David Shah [Tue, 12 May 2020 20:12:26 +0000 (21:12 +0100)]
ecp5: Add missing SERDES parameters
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Mon, 11 May 2020 20:00:36 +0000 (13:00 -0700)]
verilog: error out when non-ANSI task/func arguments
Eddie Hung [Mon, 11 May 2020 18:05:19 +0000 (11:05 -0700)]
tests: add #2042 testcase
Eddie Hung [Mon, 11 May 2020 17:30:20 +0000 (10:30 -0700)]
Setup tests/verilog properly
Claire Wolf [Fri, 8 May 2020 08:40:25 +0000 (10:40 +0200)]
Merge pull request #2038 from nakengelhardt/no-libdir-flag
Remove yosys libdir from LDFLAGS (and fix a typo)
Claire Wolf [Fri, 8 May 2020 08:13:39 +0000 (10:13 +0200)]
Fix clang compiler warning
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
whitequark [Fri, 8 May 2020 05:30:32 +0000 (05:30 +0000)]
Merge pull request #2022 from Xiretza/fallthroughs
Avoid switch fall-through warnings
Dan Ravensloft [Thu, 16 Apr 2020 11:24:04 +0000 (12:24 +0100)]
intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
N. Engelhardt [Thu, 7 May 2020 17:28:18 +0000 (19:28 +0200)]
Remove yosys libdir from LDFLAGS (and fix a typo)
Claire Wolf [Thu, 7 May 2020 16:11:48 +0000 (18:11 +0200)]
Merge pull request #2005 from YosysHQ/claire/fix1990
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
Eddie Hung [Thu, 7 May 2020 15:07:42 +0000 (08:07 -0700)]
Merge pull request #2034 from YosysHQ/eddie/abc_remote
Makefile: git fetch $(ABCURL) explicitly for local ABC checkout
Xiretza [Thu, 7 May 2020 09:44:38 +0000 (11:44 +0200)]
Reorder cases to avoid fall-through warning
log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
Xiretza [Mon, 4 May 2020 19:12:30 +0000 (21:12 +0200)]
Add YS_FALLTHROUGH macro to mark case fall-through
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
Eddie Hung [Wed, 6 May 2020 23:23:46 +0000 (16:23 -0700)]
Makefile: git fetch all commits from $(ABCURL) repo
Eddie Hung [Wed, 6 May 2020 19:10:28 +0000 (12:10 -0700)]
Merge pull request #2028 from zachjs/master
verilog: allow null gen-if then block
Zachary Snow [Tue, 5 May 2020 00:22:16 +0000 (20:22 -0400)]
verilog: allow null gen-if then block
Eddie Hung [Tue, 5 May 2020 15:01:27 +0000 (08:01 -0700)]
techlibs/common: more robustness when *_WIDTH = 0
Eddie Hung [Tue, 5 May 2020 14:59:40 +0000 (07:59 -0700)]
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
frontend: cleanup to use more ID::*, more dict<> instead of map<>
whitequark [Tue, 5 May 2020 14:03:40 +0000 (14:03 +0000)]
Merge pull request #2012 from whitequark/fix-wasi-abc-build
Fix WASI builds with abc enabled
Eddie Hung [Tue, 5 May 2020 13:49:36 +0000 (06:49 -0700)]
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung [Tue, 5 May 2020 13:49:18 +0000 (06:49 -0700)]
Merge pull request #2024 from YosysHQ/eddie/primitive_src
verilog: set src attribute for primitives
Eddie Hung [Tue, 5 May 2020 13:49:06 +0000 (06:49 -0700)]
Merge pull request #2023 from YosysHQ/eddie/specify_src
verilog: fix specify src attribute
Eddie Hung [Mon, 4 May 2020 19:18:20 +0000 (12:18 -0700)]
ast: swap range regardless of range_left >= 0
Eddie Hung [Mon, 4 May 2020 19:18:02 +0000 (12:18 -0700)]
test: add failing test
Eddie Hung [Mon, 4 May 2020 18:44:00 +0000 (11:44 -0700)]
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung [Mon, 4 May 2020 17:53:06 +0000 (10:53 -0700)]
verilog: fix specify src attribute
Eddie Hung [Mon, 4 May 2020 17:48:37 +0000 (10:48 -0700)]
frontend: cleanup to use more ID::*, more dict<> instead of map<>
Eddie Hung [Mon, 4 May 2020 17:22:05 +0000 (10:22 -0700)]
verilog: set src attribute for primitives
Eddie Hung [Mon, 4 May 2020 17:21:47 +0000 (10:21 -0700)]
tests: add tests for primitives' src
Eddie Hung [Mon, 4 May 2020 15:58:50 +0000 (08:58 -0700)]
Merge pull request #1996 from boqwxp/rtlil_source_locations
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
whitequark [Sun, 3 May 2020 16:19:42 +0000 (16:19 +0000)]
Merge pull request #2000 from whitequark/log_error-trap
kernel: Trap in `log_error()` when a debugger is attached
whitequark [Fri, 24 Apr 2020 19:37:47 +0000 (19:37 +0000)]
kernel: Trap in `log_error()` when a debugger is attached.
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
1. Running Yosys under a debugger is sufficient for the debugger
to catch some fatal errors (segfaults, aborts, STL exceptions)
but not others (`log_error()`, `log_cmd_error()`). This is
neither obvious nor easy to remember.
2. To catch Yosys-specific fatal errors, it is necessary to set
a breakpoint at `logv_error_with_prefix()`, or at least,
`logv_error()`. This is neither obvious nor easy to remember,
and GDB's autocomplete takes many seconds to suggest function
names due to the large amount of symbols in Yosys.
3. If a breakpoint is not set and Yosys encounters with such
a fatal error, the process terminates. When debugging a crash
that takes a long time to reproduce (or a nondeterministic crash)
this can waste a significant amount of time.
To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.
Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.
Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
Claire Wolf [Sun, 3 May 2020 09:56:29 +0000 (11:56 +0200)]
Merge pull request #2014 from YosysHQ/claire/fixoptalu
Fix the other "opt_expr -fine" bug introduced in
213a89558
Eddie Hung [Sat, 2 May 2020 21:22:37 +0000 (14:22 -0700)]
test: add test for #2014
Eddie Hung [Sat, 2 May 2020 21:16:10 +0000 (14:16 -0700)]
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
aiger: fixes for ports that have start_offset != 0
Claire Wolf [Sat, 2 May 2020 19:34:24 +0000 (21:34 +0200)]
Fix the other "opt_expr -fine" bug introduced in
213a89558
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Sat, 2 May 2020 19:34:24 +0000 (21:34 +0200)]
Fix the other "opt_expr -fine" bug introduced in
213a89558
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Eddie Hung [Sat, 2 May 2020 18:19:04 +0000 (11:19 -0700)]
abc9_ops: -reintegrate to be sensitive to start_offset too
Eddie Hung [Sat, 2 May 2020 16:56:10 +0000 (09:56 -0700)]
tests: aiger test for wire->start_offset != 0
Eddie Hung [Sat, 2 May 2020 16:55:34 +0000 (09:55 -0700)]
aiger: fixes for ports that have start_offset != 0
Claire Wolf [Fri, 1 May 2020 15:26:34 +0000 (17:26 +0200)]
Add plusargs for output files in test_autotb output
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Fri, 1 May 2020 15:26:07 +0000 (17:26 +0200)]
Bugfix in partsel.v signed indices test cases
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Fri, 1 May 2020 15:25:33 +0000 (17:25 +0200)]
Fix handling of signed indices in bit slices
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Wed, 29 Apr 2020 12:28:54 +0000 (14:28 +0200)]
Add tests based on the test case from #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Wed, 29 Apr 2020 12:28:04 +0000 (14:28 +0200)]
Add AST_SELFSZ and improve handling of bit slices
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Mon, 27 Apr 2020 15:04:47 +0000 (17:04 +0200)]
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Sat, 2 May 2020 09:20:02 +0000 (11:20 +0200)]
Merge pull request #2010 from YosysHQ/claire/fixopt
Fix "opt_expr -fine" bug introduced in
213a89558
whitequark [Sat, 2 May 2020 00:18:33 +0000 (00:18 +0000)]
Update ABC to include WASI support fixes.
whitequark [Fri, 1 May 2020 23:57:35 +0000 (23:57 +0000)]
Fix WASI builds with abc enabled.
This PR works around #2011.
whitequark [Fri, 1 May 2020 21:28:20 +0000 (21:28 +0000)]
Merge pull request #2001 from whitequark/wasi
Add WASI platform support
Eddie Hung [Fri, 1 May 2020 21:07:33 +0000 (14:07 -0700)]
Add testcase for #2010
Claire Wolf [Fri, 1 May 2020 17:10:26 +0000 (19:10 +0200)]
Fix "opt_expr -fine" bug introduced in
213a89558
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Fri, 1 May 2020 13:35:33 +0000 (15:35 +0200)]
Merge pull request #1997 from whitequark/document-ootb
Explain how to do out-of-tree builds in README
Claire Wolf [Fri, 1 May 2020 12:58:41 +0000 (14:58 +0200)]
Merge pull request #1981 from YosysHQ/claire/fix1837
Clear current_scope when done with RTLIL generation
Alberto Gonzalez [Fri, 24 Apr 2020 08:08:25 +0000 (08:08 +0000)]
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
whitequark [Mon, 11 Nov 2019 09:23:06 +0000 (09:23 +0000)]
Add WASI platform support.
This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
Eddie Hung [Thu, 30 Apr 2020 16:07:02 +0000 (09:07 -0700)]
Merge pull request #1999 from YosysHQ/eddie/verific_enum_again
verific: recover wiretype/enum attr as part of import_attributes()
whitequark [Thu, 30 Apr 2020 15:53:27 +0000 (15:53 +0000)]
Merge pull request #2008 from whitequark/editorconfig-abc
Fix .editorconfig to not break abc
Eddie Hung [Thu, 30 Apr 2020 14:48:47 +0000 (07:48 -0700)]
verific: ignore anonymous enums
whitequark [Thu, 30 Apr 2020 02:22:37 +0000 (02:22 +0000)]
Fix .editorconfig to not break abc.
Eddie Hung [Mon, 27 Apr 2020 22:17:13 +0000 (15:17 -0700)]
verific: support VHDL enums too
Eddie Hung [Mon, 27 Apr 2020 20:48:50 +0000 (13:48 -0700)]
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
Eddie Hung [Mon, 27 Apr 2020 19:08:45 +0000 (12:08 -0700)]
Update CHANGELOG and manual for departure from upstream
Eddie Hung [Thu, 16 Apr 2020 15:01:26 +0000 (08:01 -0700)]
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
Enabling modifications
Eddie Hung [Mon, 27 Apr 2020 18:12:17 +0000 (11:12 -0700)]
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help
bugpoint: improve help text
Eddie Hung [Mon, 27 Apr 2020 15:43:54 +0000 (08:43 -0700)]
verific: recover wiretype/enum attr as part of import_attributes()
whitequark [Sat, 25 Apr 2020 18:30:53 +0000 (18:30 +0000)]
Merge pull request #2002 from YosysHQ/dave/cxxrtl-width
cxxrtl: Round up constant width
David Shah [Sat, 25 Apr 2020 09:42:21 +0000 (10:42 +0100)]
cxxrtl: Round up constant width
Signed-off-by: David Shah <dave@ds0.me>
whitequark [Fri, 24 Apr 2020 18:07:13 +0000 (18:07 +0000)]
README: explain how to do out-of-tree builds.
whitequark [Fri, 24 Apr 2020 23:26:26 +0000 (23:26 +0000)]
Fix out-of-tree builds configured as `SMALL := 1`.
whitequark [Fri, 24 Apr 2020 18:24:10 +0000 (18:24 +0000)]
gowin,ecp5: remove generated files in `make clean`.
whitequark [Fri, 24 Apr 2020 22:44:35 +0000 (22:44 +0000)]
Merge pull request #1998 from whitequark/cxxrtl-fixes
cxxrtl: fix attribute syntax, minor fixes
Eddie Hung [Fri, 24 Apr 2020 20:41:19 +0000 (13:41 -0700)]
bugpoint: improve messaging
Eddie Hung [Fri, 24 Apr 2020 20:26:04 +0000 (13:26 -0700)]
bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells
Eddie Hung [Fri, 24 Apr 2020 18:57:55 +0000 (11:57 -0700)]
Revert "verific: import enum attributes from verific"
This reverts commit
5028e17f7db11f901ce9e423dfe2c6f7e68259cc.
whitequark [Fri, 24 Apr 2020 18:35:53 +0000 (18:35 +0000)]
cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
Eddie Hung [Fri, 24 Apr 2020 18:17:09 +0000 (11:17 -0700)]
bugpoint: skip ports with (* keep *) on; add header
Claire Wolf [Fri, 24 Apr 2020 12:09:47 +0000 (14:09 +0200)]
Merge pull request #1995 from YosysHQ/eddie/fix_verific_wiretype
verific: do not assert if wire not found; warn instead
Dan Ravensloft [Thu, 23 Apr 2020 21:44:29 +0000 (22:44 +0100)]
intel_alm: cleanup duplication
whitequark [Fri, 24 Apr 2020 05:50:10 +0000 (05:50 +0000)]
cxxrtl: improve printing of narrow memories.
whitequark [Fri, 24 Apr 2020 05:44:39 +0000 (05:44 +0000)]
cxxrtl: fix handling of parametric modules with large parameters.
These have a `$paramod$` prefix, not `$paramod\\`.
Eddie Hung [Thu, 23 Apr 2020 23:28:11 +0000 (16:28 -0700)]
verific: do not assert if wire not found; warn instead
Eddie Hung [Thu, 23 Apr 2020 19:16:55 +0000 (12:16 -0700)]
bugpoint: improve help text
Eddie Hung [Thu, 23 Apr 2020 13:43:30 +0000 (06:43 -0700)]
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs
abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
Claire Wolf [Thu, 23 Apr 2020 09:34:19 +0000 (11:34 +0200)]
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs
qbfsat: Make hole name recovery from source locations more robust.