Cleanup synth_xilinx

Working

Reverse bits in INIT parameter for Xilinx, since MSB is shifted first

Misspell

Revert "Add shregmap -init_msb_first and use in synth_xilinx"

This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.

Merge remote-tracking branch 'origin/master' into xc7srl

Add shregmap -init_msb_first and use in synth_xilinx

Fix cells_map for SRL

Move shregmap until after first techmap

Refactor $__SHREG__ in cells_map.v

Merge pull request #868 from YosysHQ/clifford/fixmem

Various mem2reg-related improvements in handling of memories

Fix a bug in handling quotes in multi-cmd lines in Yosys scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #866 from YosysHQ/clifford/idstuff

Improve determinism of IdString DB for similar scripts

Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve handling of memories used in mem index expressions on LHS of an assignment

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove outdated "blocking assignment to memory" warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve determinism of IdString DB for similar scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #864 from YosysHQ/svalabelfix

Fix handling of cases that look like sva labels, fixes #862

Add ENABLE_GLOB Makefile switch

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of cases that look like sva labels, fixes #862

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix typo in ice40_braminit help msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #859 from smunaut/ice40_braminit

iCE40 BRAM primitives init from file

Fix signed $shift/$shiftx handling in write_smt2

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add $dffsr support to async2sync

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #858 from YosysHQ/clifford/svalabels

Add support for using SVA labels in yosys-smtbmc console output

Merge pull request #861 from YosysHQ/verific_chparam

Add -chparam option to verific command

Also add support for labels on sva module items, fixes #699

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update help message for -chparam

Add -chparam option to verific command

Fix spelling

Merge branch 'master' of github.com:YosysHQ/yosys

Fix handling of task output ports in clocked always blocks, fixes #857

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ice40: Run ice40_braminit pass by default

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

ice40: Add ice40_braminit pass to allow initialization of BRAM from file

This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Merge pull request #856 from kprasadvnsi/master

examples/anlogic/ now also output the SVF file.

Use SVA label in smt export if available

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for SVA labels in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add hack for handling SVA labels via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add link to SF2 / igloo2 macro library guide

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in sf2 cells_sim.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add sf2 techmap rules for more FF types

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Refactor SF2 iobuf insertion, Add clkint insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in SF2 flow and demo

Signed-off-by: Clifford Wolf <clifford@clifford.at>

examples/anlogic/ now also output the SVF file.

Fix spelling in pmgen/README.md

Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #842 from litghost/merge_upstream

Changes required for VPR place and route in synth_xilinx

Merge pull request #850 from daveshah1/ecp5_warn_conflict

ecp5: Demote conflicting FF init values to a warning

Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #851 from kprasadvnsi/master

Added examples/anlogic/

Merge pull request #852 from ucb-bar/firrtlfixes

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails

Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".

Added examples/anlogic/

Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>

Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #848 from YosysHQ/clifford/fix763

Fix error for wire decl in always block, fixes 763

Merge pull request #849 from YosysHQ/clifford/dynports

Only run derive on blackbox modules when ports have dynamic size

Only run derive on blackbox modules when ports have dynamic size

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix $global_clock handling vs autowire

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #847 from YosysHQ/clifford/fix785

Fix $readmem[hb] for mem2reg memories, fixes #785

Fix $readmem[hb] for mem2reg memories, fixes #785

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #843 from YosysHQ/clifford/mem2regconstidx

Use mem2reg on memories that only have constant-index write ports

Merge pull request #845 from YosysHQ/clifford/travisnomacos

Disable macOS builds in Travis

Disable macOS builds in Travis

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Try again for passes/pmgen/ice40_dsp_pm.h rule

Tested on both in-tree and out-of-tree builds

Revert FF models to include IS_x_INVERTED parameters.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Minor improvements in README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Use mem2reg on memories that only have constant-index write ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Modify arguments to match existing style.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Changes required for VPR place and route synth_xilinx.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #841 from mmicko/master

Fix ECP5 cells_sim for iverilog

Fix ECP5 cells_sim for iverilog

Improve "read" error msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #837 from YosysHQ/clifford/fix835

Fix multiple issues in wreduce FF handling, fixes #835

Fix multiple issues in wreduce FF handling, fixes #835

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>

Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"

Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Reduce amount of trailing whitespace in code base

Fix pmgen for in-tree builds

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #794 from daveshah1/ecp5improve

ECP5 Improvements

Merge pull request #827 from ucb-bar/firrtlfixes

Fix FIRRTL to Verilog process instance subfield assignment.

Fix pmgen for out-of-tree build

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove SRL16/32 from cells_xtra

Add SRL16 and SRL32 sim models

Fix SRL16/32 techmap off-by-one

Merge pull request #833 from YosysHQ/clifford/fix831

Fix smt2 code generation for partially initialized memory words, fixe…

Fix smt2 code generation for partially initialized memowy words, fixes #831

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #832 from YosysHQ/supercover

Add "supercover" pass