Clifford Wolf [Sat, 4 May 2019 05:52:51 +0000 (07:52 +0200)]
Add approximate support for SV "var" keyword, fixes #987
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 3 May 2019 22:54:25 +0000 (15:54 -0700)]
More testing
Eddie Hung [Fri, 3 May 2019 22:42:02 +0000 (15:42 -0700)]
Fix spacing
Eddie Hung [Fri, 3 May 2019 22:35:26 +0000 (15:35 -0700)]
Add quick-and-dirty specify tests
Eddie Hung [Fri, 3 May 2019 22:05:57 +0000 (15:05 -0700)]
Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung [Fri, 3 May 2019 21:40:32 +0000 (14:40 -0700)]
Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung [Fri, 3 May 2019 21:03:51 +0000 (14:03 -0700)]
iverilog with simcells.v as well
Clifford Wolf [Fri, 3 May 2019 20:03:43 +0000 (22:03 +0200)]
Add "hierarchy -chparam" support for non-verific top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 14 Mar 2019 15:29:43 +0000 (15:29 +0000)]
log_warning_noprefix -> log_warning as per review
Eddie Hung [Wed, 13 Mar 2019 22:40:00 +0000 (22:40 +0000)]
For hier_tree::Elaborate() also include SV root modules (bind)
Eddie Hung [Wed, 13 Mar 2019 22:05:55 +0000 (22:05 +0000)]
Fix verific_parameters construction, use attribute to mark top netlists
Eddie Hung [Wed, 13 Mar 2019 19:42:18 +0000 (19:42 +0000)]
WIP -chparam support for hierarchy when verific
Eddie Hung [Wed, 13 Mar 2019 00:02:04 +0000 (00:02 +0000)]
verific_import() changes to avoid ElaborateAll()
Clifford Wolf [Fri, 3 May 2019 18:39:50 +0000 (20:39 +0200)]
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
Clifford Wolf [Fri, 3 May 2019 18:34:32 +0000 (20:34 +0200)]
Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
Eddie Hung [Fri, 3 May 2019 16:55:02 +0000 (09:55 -0700)]
Revert "synth_xilinx to call dffinit with -noreinit"
This reverts commit
1f62dc9081feb4852b1848d01951f631853edb38.
Eddie Hung [Fri, 3 May 2019 15:06:16 +0000 (08:06 -0700)]
If init is 1'bx, do not add to dict as per @cliffordwolf
Eddie Hung [Fri, 3 May 2019 15:05:37 +0000 (08:05 -0700)]
Revert "dffinit -noreinit to silently continue when init value is 1'bx"
This reverts commit
aa081f83c791b1d666214776aaf744a80ce6a690.
Clifford Wolf [Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)]
Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
Clifford Wolf [Fri, 3 May 2019 13:25:46 +0000 (15:25 +0200)]
Merge pull request #985 from YosysHQ/clifford/fix981
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
Clifford Wolf [Fri, 3 May 2019 12:40:51 +0000 (14:40 +0200)]
Fix typo in tests/svinterfaces/runone.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 12:37:46 +0000 (14:37 +0200)]
Merge pull request #979 from jakobwenzel/svinterfacesTestcase
fail svinterfaces testcases on yosys error exit
Clifford Wolf [Fri, 3 May 2019 12:24:53 +0000 (14:24 +0200)]
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 07:22:26 +0000 (09:22 +0200)]
Further improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 07:12:10 +0000 (09:12 +0200)]
Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 06:35:45 +0000 (08:35 +0200)]
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 06:25:30 +0000 (08:25 +0200)]
Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 3 May 2019 00:41:20 +0000 (17:41 -0700)]
synth_xilinx to call dffinit with -noreinit
Eddie Hung [Fri, 3 May 2019 00:40:39 +0000 (17:40 -0700)]
dffinit -noreinit to silently continue when init value is 1'bx
Jim Lawson [Thu, 2 May 2019 14:59:07 +0000 (07:59 -0700)]
Merge remote-tracking branch 'upstream/master'
Jakob Wenzel [Thu, 25 Apr 2019 13:12:24 +0000 (15:12 +0200)]
fail svinterfaces testcases on yosys error exit
Clifford Wolf [Thu, 2 May 2019 07:11:07 +0000 (09:11 +0200)]
Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung [Thu, 2 May 2019 01:24:21 +0000 (18:24 -0700)]
Merge pull request #978 from ucb-bar/fmtfirrtl
Re-indent firrtl.cc:struct memory - no functional change.
Eddie Hung [Thu, 2 May 2019 01:23:21 +0000 (18:23 -0700)]
Back to passing all xc7srl tests!
Eddie Hung [Thu, 2 May 2019 01:09:38 +0000 (18:09 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung [Wed, 1 May 2019 23:26:43 +0000 (16:26 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys
Jim Lawson [Wed, 1 May 2019 23:21:13 +0000 (16:21 -0700)]
Re-indent firrtl.cc:struct memory - no functional change.
Jim Lawson [Wed, 1 May 2019 23:13:11 +0000 (16:13 -0700)]
Merge remote-tracking branch 'upstream/master'
Clifford Wolf [Wed, 1 May 2019 22:04:12 +0000 (00:04 +0200)]
Merge branch 'clifford/fix883'
Clifford Wolf [Wed, 1 May 2019 22:03:31 +0000 (00:03 +0200)]
Add missing enable_undef to "sat -tempinduct-def", fixes #883
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 21:47:16 +0000 (23:47 +0200)]
Merge pull request #977 from ucb-bar/fixfirrtlmem
Fix #938 - Crash occurs in case when use write_firrtl command
Jim Lawson [Wed, 1 May 2019 20:16:01 +0000 (13:16 -0700)]
Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
Clifford Wolf [Wed, 1 May 2019 13:06:46 +0000 (15:06 +0200)]
Fix floating point exception in qwp, fixes #923
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 08:01:54 +0000 (10:01 +0200)]
Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 07:57:26 +0000 (09:57 +0200)]
Fix width detection of memory access with bit slice, fixes #974
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 07:32:07 +0000 (09:32 +0200)]
Add additional test cases for for-loops
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 07:29:34 +0000 (09:29 +0200)]
Silently resolve completely unused cell-vs-const driver-driver conflicts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 1 May 2019 07:01:47 +0000 (09:01 +0200)]
Re-enable "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 20:20:45 +0000 (22:20 +0200)]
Fix segfault in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jim Lawson [Tue, 30 Apr 2019 20:19:27 +0000 (13:19 -0700)]
Merge remote-tracking branch 'upstream/master'
Clifford Wolf [Tue, 30 Apr 2019 18:22:50 +0000 (20:22 +0200)]
Disabled "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 16:09:44 +0000 (18:09 +0200)]
Merge pull request #972 from YosysHQ/clifford/fix968
Add final loop variable assignment when unrolling for-loops
Clifford Wolf [Tue, 30 Apr 2019 16:08:41 +0000 (18:08 +0200)]
Merge pull request #966 from YosysHQ/clifford/fix956
Drive dangling wires with init attr with their init value
Clifford Wolf [Tue, 30 Apr 2019 16:07:19 +0000 (18:07 +0200)]
Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
Refactor synth_xilinx to auto-generate doc
Clifford Wolf [Tue, 30 Apr 2019 15:00:34 +0000 (17:00 +0200)]
Merge branch 'master' into eddie/refactor_synth_xilinx
Clifford Wolf [Tue, 30 Apr 2019 13:48:42 +0000 (15:48 +0200)]
Merge pull request #973 from christian-krieg/feature/python_bindings
Feature/python bindings cleanup
Clifford Wolf [Tue, 30 Apr 2019 13:35:36 +0000 (15:35 +0200)]
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 13:19:04 +0000 (15:19 +0200)]
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 13:03:32 +0000 (15:03 +0200)]
Add final loop variable assignment when unrolling for-loops, fixes #968
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 12:46:12 +0000 (14:46 +0200)]
Add handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Benedikt Tutzer [Tue, 30 Apr 2019 11:22:33 +0000 (13:22 +0200)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
Benedikt Tutzer [Tue, 30 Apr 2019 11:19:04 +0000 (13:19 +0200)]
Cleaned up root directory
Clifford Wolf [Tue, 30 Apr 2019 09:25:15 +0000 (11:25 +0200)]
Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 08:51:51 +0000 (10:51 +0200)]
pmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 06:10:37 +0000 (08:10 +0200)]
Run "peepopt" in generic "synth" pass and "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 06:04:22 +0000 (08:04 +0200)]
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Apr 2019 05:59:39 +0000 (07:59 +0200)]
Progress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 29 Apr 2019 11:54:26 +0000 (13:54 +0200)]
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
Add -undef option to equiv_opt, passed to equiv_induct
Clifford Wolf [Mon, 29 Apr 2019 11:48:52 +0000 (13:48 +0200)]
Merge pull request #967 from olegendo/depfile_esc_spaces
escape spaces with backslash when writing dep file
Clifford Wolf [Mon, 29 Apr 2019 11:38:56 +0000 (13:38 +0200)]
Add "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 29 Apr 2019 11:02:05 +0000 (13:02 +0200)]
Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Oleg Endo [Mon, 29 Apr 2019 10:20:33 +0000 (19:20 +0900)]
fix codestyle formatting
Clifford Wolf [Fri, 26 Apr 2019 14:38:36 +0000 (16:38 +0200)]
Support multiple pmg files (right now just concatenated together)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Oleg Endo [Mon, 29 Apr 2019 07:13:34 +0000 (16:13 +0900)]
escape spaces with backslash when writing dep file
filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
Clifford Wolf [Mon, 29 Apr 2019 06:38:38 +0000 (08:38 +0200)]
Drive dangling wires with init attr with their init value, fixes #956
Eddie Hung [Sun, 28 Apr 2019 20:04:34 +0000 (13:04 -0700)]
Copy with 1'bx padding in $shiftx
Eddie Hung [Sun, 28 Apr 2019 19:51:00 +0000 (12:51 -0700)]
WIP
Eddie Hung [Sun, 28 Apr 2019 19:36:04 +0000 (12:36 -0700)]
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung [Fri, 26 Apr 2019 23:53:16 +0000 (16:53 -0700)]
Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung [Fri, 26 Apr 2019 22:35:34 +0000 (15:35 -0700)]
Where did this check come from!?!
Eddie Hung [Fri, 26 Apr 2019 21:32:18 +0000 (14:32 -0700)]
Refactor synth_xilinx to auto-generate doc
Eddie Hung [Fri, 26 Apr 2019 21:31:59 +0000 (14:31 -0700)]
Cleanup ice40
Eddie Hung [Fri, 26 Apr 2019 18:14:33 +0000 (11:14 -0700)]
Add -undef option to equiv_opt, passed to equiv_induct
Eddie Hung [Thu, 25 Apr 2019 23:46:13 +0000 (16:46 -0700)]
Misspelling
Clifford Wolf [Tue, 23 Apr 2019 21:01:38 +0000 (23:01 +0200)]
Add specify support to README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 23 Apr 2019 20:57:10 +0000 (22:57 +0200)]
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 23 Apr 2019 20:18:04 +0000 (22:18 +0200)]
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 23 Apr 2019 13:46:40 +0000 (15:46 +0200)]
Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 08:03:18 +0000 (10:03 +0200)]
Preserve $specify[23] cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:59:49 +0000 (09:59 +0200)]
Allow $specify[23] cells in blackbox modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:52:47 +0000 (09:52 +0200)]
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:49:55 +0000 (09:49 +0200)]
Add $specify2/$specify3 support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:35:14 +0000 (09:35 +0200)]
Add support for $assert/$assume/$cover to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:29:59 +0000 (09:29 +0200)]
Add CellTypes support for $specify2 and $specify3
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:26:20 +0000 (09:26 +0200)]
Add InternalCellChecker support for $specify2 and $specify3
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 00:33:12 +0000 (02:33 +0200)]
Checking and fixing specify cells in genRTLIL
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 21 Apr 2019 20:58:51 +0000 (22:58 +0200)]
Un-break default specify parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 21 Apr 2019 19:58:57 +0000 (21:58 +0200)]
Add specify parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 21 Apr 2019 14:10:41 +0000 (16:10 +0200)]
Add $specify2 and $specify3 cells to simlib
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 23 Apr 2019 17:59:39 +0000 (19:59 +0200)]
Merge pull request #957 from YosysHQ/oai4fix
Fixes for OAI4 cell implementation