Dam Sunwoo [Mon, 22 Apr 2013 17:20:31 +0000 (13:20 -0400)]
cpu: generate SimPoint basic block vector profiles
This patch is based on http://reviews.m5sim.org/r/1474/ originally written by
Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout
folder) based on start and end addresses of basic blocks.
Some comments to the original patch are addressed and hooks are added to create
and resume from checkpoints based on instruction counts dictated by external
SimPoint analysis tools.
SimPoint creation/resuming options will be implemented as a separate patch.
Chris Emmons [Mon, 22 Apr 2013 17:20:31 +0000 (13:20 -0400)]
ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.
Newer core tiles / daughterboards for the Versatile Express platform have an
HDLCD controller that supports HD-quality output. This patch adds an
implementation of the controller.
Andreas Sandberg [Mon, 22 Apr 2013 17:20:31 +0000 (13:20 -0400)]
sim: Add helper functions that add PCEvents with custom arguments
This changeset adds support for forwarding arguments to the PC
event constructors to following methods:
addKernelFuncEvent
addFuncEvent
Additionally, this changeset adds the following helper method to the
System base class:
addFuncEventOrPanic - Hook a PCEvent to a symbol, panic on failure.
addKernelFuncEventOrPanic - Hook a PCEvent to a kernel symbol, panic
on failure.
System implementations have been updated to use the new functionality
where appropriate.
Ali Saidi [Mon, 22 Apr 2013 17:20:31 +0000 (13:20 -0400)]
cpu: fix a switching issue with the o3 cpu.
This change fixes the switcheroo test that broke earlier this month. The code
that was checking for the pipeline being blocked wasn't checking for a pending
translation, only for a icache access.
Andreas Hansson [Fri, 19 Apr 2013 13:04:42 +0000 (09:04 -0400)]
stats: Update stats for ldr_ret_uop (changeset
35198406dd72)
This patch merely bumps the stats to match the changes introduced in
changeset
35198406dd72.
Nilay Vaish [Wed, 17 Apr 2013 21:09:37 +0000 (16:09 -0500)]
base: load weak symbols from object file
Without loading weak symbols into gem5, some function names and the given PC
cannot correspond correctly, because the binding attributes of unction names
in an ELF file are not only STB_GLOBAL or STB_LOCAL, but also STB_WEAK. This
patch adds a function for loading weak symbols.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nathanael Premillieu [Wed, 17 Apr 2013 21:07:10 +0000 (16:07 -0500)]
arm: set ldr_ret_uop as conditional or unconditional control
This patch adds a missing flag to the ldr_ret_uop microop instruction.
The flag is added when the instruction is used, not directly in the
constructor of the instruction.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>"
Nilay Vaish [Wed, 17 Apr 2013 21:06:58 +0000 (16:06 -0500)]
ruby: moesi cmp directory: add copyright notice
Nilay Vaish [Wed, 17 Apr 2013 21:06:24 +0000 (16:06 -0500)]
config: ruby network test: remove piobus check
Andreas Hansson [Wed, 17 Apr 2013 12:17:03 +0000 (08:17 -0400)]
dev: Fix a bug in the use of seekp/seekg
This patch fixes two instances of incorrect use of the seekp/seekg
stream member functions. These two functions return a stream reference
(*this), and should not be compared to an integer value.
Andreas Hansson [Tue, 16 Apr 2013 10:26:49 +0000 (06:26 -0400)]
stats: Bump the vortex stats to match latest behaviour
This patch bumps the stats for the failing vortex o3 regression.
Joel Hestness [Tue, 9 Apr 2013 21:41:12 +0000 (16:41 -0500)]
stats: Bump Ruby stats for new changesets
The new changeset that can reorder Ruby profilers will cause the ruby.stats
files to reordered statistics (the point of the patch). Update the references
to ensure that these changes are reflected in regressions.
Joel Hestness [Tue, 9 Apr 2013 21:25:30 +0000 (16:25 -0500)]
Configs: Fix handling of maxtick and take_checkpoints
In Simulation.py, calls to m5.simulate(num_ticks) will run the simulated system
for num_ticks after the current tick. Fix calls to m5.simulate in
scriptCheckpoints() and benchCheckpoints() to appropriately handle the maxticks
variable.
Joel Hestness [Tue, 9 Apr 2013 21:25:30 +0000 (16:25 -0500)]
Ruby: Fix RubyPort evict packet memory leak
When using the o3 or inorder CPUs with many Ruby protocols, the caches may
need to forward invalidations to the CPUs. The RubyPort was instantiating a
packet to be sent to the CPUs to signal the eviction, but the packets were
not being freed by the CPUs. Consistent with the classic memory model, stack
allocate the packet and heap allocate the request so on
ruby_eviction_callback() completion, the packet deconstructor is called, and
deletes the request (*Note: stack allocating the request causes double
deletion, since it will be deleted in the packet destructor). This results in
the least memory allocations without memory errors.
Joel Hestness [Tue, 9 Apr 2013 21:25:29 +0000 (16:25 -0500)]
Ruby: Delete packet requests during warmup
When warming up caches in Ruby, the CacheRecorder sends fetch requests into
Ruby Sequencers with packet types that require responses. Since responses are
never generated for these CacheRecorder requests, the requests are not deleted
in the packet destructor called from the Ruby hit callback. Free the request.
Joel Hestness [Tue, 9 Apr 2013 21:25:29 +0000 (16:25 -0500)]
Ruby: Add field to slicc machine for generic type
This allows you to have (i.e.) an L2 cache that is not named "L2Cache"
but is still a GenericMachineType_L2Cache. This is particularly
helpful if the protocol has multiple L2 controllers.
Joel Hestness [Tue, 9 Apr 2013 21:25:29 +0000 (16:25 -0500)]
Ruby: Order profilers based on version
When Ruby stats are printed for events and transitions, they include stats
for all of the controllers of the same type, but they are not necessarily
printed in order of the controller ID "version", because of the way the
profilers were added to the profiler vector. This patch fixes the push order
problem so that the stats are printed in ascending order 0->(# controllers),
so statistics parsers may correctly assume the controller to which the stats
belong.
Jason Power [Tue, 9 Apr 2013 21:15:06 +0000 (16:15 -0500)]
Ruby: More descriptive message buffer connection fatal
When connecting message buffers between Ruby controllers, it is
easy to mistakenly connect multiple controllers to the same message
buffer. This patch prints a more descriptive fatal message than the
previous assert statement in order to facilitate easier debugging.
Jason Power [Tue, 9 Apr 2013 21:12:42 +0000 (16:12 -0500)]
Ruby: Fix typo in Slicc if-statement AST error
The error in the SLICC code was hidden by the python error in SLICC parser
before this patch
Joel Hestness [Mon, 8 Apr 2013 01:31:15 +0000 (20:31 -0500)]
Ruby System, Cache Recorder: Use delete [] for trace vars
The cache trace variables are array allocated uint8_t* in the RubySystem and
the Ruby CacheRecorder, but the code used delete to free the memory, resulting
in Valgrind memory errors. Change these deletes to delete [] to get rid of the
errors.
Anthony Gutierrez [Tue, 2 Apr 2013 16:46:49 +0000 (12:46 -0400)]
rcs scripts: remove bbench.rcS
this run script shouldn't be used; bbench-ics.rcS or bbench-gb.rcS
should be used instead.
Nilay Vaish [Fri, 29 Mar 2013 19:05:36 +0000 (14:05 -0500)]
regressions: updates due to changes to o3 cpu, x86 memory map
Nilay Vaish [Fri, 29 Mar 2013 19:05:26 +0000 (14:05 -0500)]
o3cpu: commit: changes interrupt handling
Currently the commit stage keeps a local copy of the interrupt object.
Since the interrupt is usually handled several cycles after the commit
stage becomes aware of it, it is possible that the local copy of the
interrupt object may not be the interrupt that is actually handled.
It is possible that another interrupt occurred in the
interval between interrupt detection and interrupt handling.
This patch creates a copy of the interrupt just before the interrupt
is handled. The local copy is ignored.
Nilay Vaish [Thu, 28 Mar 2013 14:34:23 +0000 (09:34 -0500)]
x86: changes to apic, keyboard
It is possible that operating system wants to shutdown the
lapic timer by writing timer's initial count to 0. This patch
adds a check that the timer event is only scheduled if the
count is 0.
The patch also converts few of the panics related to the keyboard
to warnings since we are any way not interested in simulating the
keyboard.
Nilay Vaish [Thu, 28 Mar 2013 14:34:15 +0000 (09:34 -0500)]
x86: create space in bios memory map
As of now, we mark the top 1MB of memory space as unusable. Part of
it is actually usable and is required to be marked so by some of the
newer versions of linux kernel. This patch marks the top 639KB as usable.
This value was chosen by looking at QEMU's output for bios memory map.
Nilay Vaish [Thu, 28 Mar 2013 14:32:01 +0000 (09:32 -0500)]
regressions: update eio stats due to cache latency fix
Nilay Vaish [Wed, 27 Mar 2013 23:36:21 +0000 (18:36 -0500)]
regressions: update due to cache latency fix
Mitch Hayenga [Wed, 27 Mar 2013 23:36:09 +0000 (18:36 -0500)]
mem: Fix cache latency bug
Fixes a latency calculation bug for accesses during a cache line fill.
Under a cache miss, before the line is filled, accesses to the cache are
associated with a MSHR and marked as targets. Once the line fill completes,
MSHR target packets pay an additional latency of
"responseLatency + busSerializationLatency". However, the "whenReady"
field of the cache line is only set to an additional delay of
"busSerializationLatency". This lacks the responseLatency component of
the fill. It is possible for accesses that occur on the cycle of
(or briefly after) the line fill to respond without properly paying the
responseLatency. This also creates the situation where two accesses to the
same address may be serviced in an order opposite of how they were received
by the cache. For stores to the same address, this means that although the
cache performs the stores in the order they were received, acknowledgements
may be sent in a different order.
Adding the responseLatency component to the whenReady field preserves the
penalty that should be paid and prevents these ordering issues.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Steve Reinhardt [Wed, 27 Mar 2013 17:03:02 +0000 (10:03 -0700)]
scons: don't die on warnings in swig-generated code
There's not much to do about it other than disable the offending
warning anyway, so it's not worth terminating the build over.
Also suppress uninitialized variable warnings on gcc (happens
at least with gcc 4.4 and swig 1.3.40).
Andreas Hansson [Tue, 26 Mar 2013 18:49:58 +0000 (14:49 -0400)]
util: Add a utility script for decoding packet traces
This patch adds a simple Python script that reads the protobuf-encoded
packet traces (not gzipped), and prints them to an ASCII trace file.
The script can also be used as a template for other packet output
formats.
Andreas Hansson [Tue, 26 Mar 2013 18:49:55 +0000 (14:49 -0400)]
util: Add a utility script for encoding packet traces
This patch adds a simple Python script that reads a simple ASCII trace
format and encodes it as protobuf output compatible with the traffic
generator.
The script can also be used as a template for other packet input
formats that should be converted to the gem5 packet protobuf format.
Andreas Hansson [Tue, 26 Mar 2013 18:47:03 +0000 (14:47 -0400)]
stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
Rene de Jong [Tue, 26 Mar 2013 18:46:51 +0000 (14:46 -0400)]
mem: Cancel cache retry event when blocking port
This patch solves the corner case scenario where the sendRetryEvent could be
scheduled twice, when an io device stresses the IOcache in the system. This
should not be possible in the cache system.
Andreas Hansson [Tue, 26 Mar 2013 18:46:49 +0000 (14:46 -0400)]
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Andreas Hansson [Tue, 26 Mar 2013 18:46:47 +0000 (14:46 -0400)]
mem: Separate waiting for the bus and waiting for a peer
This patch splits the retryList into a list of ports that are waiting
for the bus itself to become available, and a map that tracks the
ports where forwarding failed due to a peer not accepting the
packet. Thus, when a retry reaches the bus, it can be sent to the
appropriate port that initiated that transaction.
As a consequence of this patch, only ports that are really ready to go
will get a retry, thus reducing the amount of redundant failed
attempts. This patch also makes it easier to reason about the order of
servicing requests as the ports waiting for the bus are now clearly
FIFO and much easier to change if desired.
Andreas Hansson [Tue, 26 Mar 2013 18:46:46 +0000 (14:46 -0400)]
mem: Introduce a variable for the retrying port
This patch introduces a variable to keep track of the retrying port
instead of relying on it being the front of the retryList.
Besides the improvement in readability, this patch is a step towards
separating out the two cases where a port is waiting for the bus to be
free, and where the forwarding did not succeed and the bus is waiting
for a retry to pass on to the original initiator of the transaction.
The changes made are currently such that the regressions are not
affected. This is ensured by always prioritizing the currently
retrying port and putting it back at the front of the retry list.
Andreas Hansson [Tue, 26 Mar 2013 18:46:45 +0000 (14:46 -0400)]
mem: Add a generic id field to the packet trace
This patch adds an optional generic 64-bit identifier field to the
packet trace. This can be used to store the sequential number of the
instruction that gave rise to the packet, thread id, master id,
"sub"-master within a larger module etc. As the field is optional it
has a marginal cost if not used.
Andreas Hansson [Tue, 26 Mar 2013 18:46:44 +0000 (14:46 -0400)]
mem: Add optional request flags to the packet trace
This patch adds an optional flags field to the packet trace to encode
the request flags that contain information about whether the request
is (un)cacheable, instruction fetch, preftech etc.
Andreas Hansson [Tue, 26 Mar 2013 18:46:42 +0000 (14:46 -0400)]
cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.
Andreas Sandberg [Mon, 25 Mar 2013 12:20:15 +0000 (13:20 +0100)]
x86: Revert [
02321b16685f] which breaks m5ops on x86
Changeset
02321b16685f added m5_writefile to m5op_x86.S a second time,
which causes a compilation error on when compiling for x86. This
changeset reverts that changeset and fixes the error.
Nilay Vaish [Fri, 22 Mar 2013 22:31:24 +0000 (17:31 -0500)]
config: return exit event instead of cause
changeset:
a4739b6f799d made some changes that where an exit event
should have been returned in place of exit cause. This patch corrects
the error.
Nilay Vaish [Fri, 22 Mar 2013 22:21:25 +0000 (17:21 -0500)]
regressions: updates to config.ini for ruby tests
Nilay Vaish [Fri, 22 Mar 2013 22:21:23 +0000 (17:21 -0500)]
ruby: slicc: set sender, receiver clock objs for optional queue
Nilay Vaish [Fri, 22 Mar 2013 22:21:22 +0000 (17:21 -0500)]
ruby: message buffer: correct previous errors
A recent set of patches added support for multiple clock domains to ruby.
I had made some errors while writing those patches. The sender was using
the receiver side clock while enqueuing a message in the buffer. Those
errors became visible while creating (or restoring from) checkpoints. The
errors also become visible when a multi eventq scenario occurs.
Nilay Vaish [Fri, 22 Mar 2013 20:53:27 +0000 (15:53 -0500)]
ruby: message buffer: remove _ptr from some variables
The names were getting too long.
Nilay Vaish [Fri, 22 Mar 2013 20:53:26 +0000 (15:53 -0500)]
ruby: message buffer node: used Tick in place of Cycles
The message buffer node used to keep time in terms of Cycles. Since the
sender and the receiver can have different clock periods, storing node
time in cycles requires some conversion. Instead store the time directly
in Ticks.
Nilay Vaish [Fri, 22 Mar 2013 20:53:26 +0000 (15:53 -0500)]
ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.
There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.
Nilay Vaish [Fri, 22 Mar 2013 20:53:25 +0000 (15:53 -0500)]
ruby: remove unsued profile functions
Nilay Vaish [Fri, 22 Mar 2013 20:53:25 +0000 (15:53 -0500)]
ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.
Nilay Vaish [Fri, 22 Mar 2013 20:53:24 +0000 (15:53 -0500)]
slicc: remove check if the L1Cache has a sequencer
Nilay Vaish [Fri, 22 Mar 2013 20:53:24 +0000 (15:53 -0500)]
ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.
Nilay Vaish [Fri, 22 Mar 2013 20:53:23 +0000 (15:53 -0500)]
ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.
Nilay Vaish [Fri, 22 Mar 2013 20:53:23 +0000 (15:53 -0500)]
ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.
Nilay Vaish [Fri, 22 Mar 2013 20:53:22 +0000 (15:53 -0500)]
ruby: network: move routers from topology to network
Andreas Hansson [Wed, 20 Mar 2013 10:41:23 +0000 (06:41 -0400)]
cpu: Avoid including inorder TLBUnit to avoid gcc LTO bug
This patch comments out the inclusion of the inorder TLBUnit which is
only used in the 9-stage pipeline. With the TLBUnit present, gcc >=
4.6 in combination with LTO ends up throwing away the definition of
the TLBUnit destructor, and consequently fail to link. See
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53808 for more details
about the bug, and http://gcc.gnu.org/ml/gcc/2012-06/msg00397.html for
the discussion thread that also touches on similar issues seen with
clang.
Andreas Sandberg [Mon, 18 Mar 2013 10:24:56 +0000 (11:24 +0100)]
scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'
tcmalloc_minimal doesn't support the heap checker on Debian, while
tcmalloc does. Instead of always linking with tcmalloc_minimal, if it
exists, we first check for tcmalloc and then use tcmalloc_minimal as a
fallback.
Andreas Sandberg [Mon, 18 Mar 2013 09:57:26 +0000 (10:57 +0100)]
scons: Avoid malloc/free compiler optimization when using tcmalloc
According to the tcmalloc readme, the recommended way of compiling
applications that make use of tcmalloc is to disable compiler
optimizations that make assumptions about malloc and friends. This
changeset adds the necessary compiler flags for both gcc and clang.
From the tcmalloc readme:
"NOTE: When compiling with programs with gcc, that you plan to link
with libtcmalloc, it's safest to pass in the flags
-fno-builtin-malloc -fno-builtin-calloc
-fno-builtin-realloc -fno-builtin-free
when compiling."
Andreas Sandberg [Mon, 18 Mar 2013 09:44:34 +0000 (10:44 +0100)]
scons: Don't explicitly add tcmalloc_minimal to LIBS
SCons automatically adds a library to LIBS if conf.CheckLib succeeds,
so there is no need to explicitly add the library.
Andreas Sandberg [Mon, 18 Mar 2013 09:22:21 +0000 (10:22 +0100)]
scons: Include flags required to link statically with Python
Python requires the flags in LINKFORSHARED to be added the linker
flags when linking with a statically with Python. Failing to do so can
lead to errors from the Python's dynamic module loader at start up.
--HG--
extra : rebase_source :
e7a8daf72f4ede7ee5a4a5398a0b12e978a919b9
Andreas Hansson [Mon, 18 Mar 2013 09:22:45 +0000 (05:22 -0400)]
mem: Fix missing delete of packet in DRAM access
This patch fixes a memory leak caused by not deleting packets that
require no response.
Nilay Vaish [Fri, 15 Mar 2013 21:28:08 +0000 (16:28 -0500)]
ruby: set: corrects csprintf() call introduced by
7d95b650c9b6
Andreas Sandberg [Thu, 14 Mar 2013 15:08:55 +0000 (16:08 +0100)]
scons: Check for known buggy version of SWIG (2.0.9)
SWIG version 2.0.9 uses fully qualified module names despite of the
importing module being in the same package as the imported
module. This has the unfortunate consequence of causing the following
error when importing m5.internal.event:
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "src/python/importer.py", line 75, in load_module
exec code in mod.__dict__
File "src/python/m5/__init__.py", line 35, in <module>
import internal
File "src/python/importer.py", line 75, in load_module
exec code in mod.__dict__
File "src/python/m5/internal/__init__.py", line 32, in <module>
import event
File "src/python/importer.py", line 75, in load_module
exec code in mod.__dict__
File "build/X86/python/swig/event.py", line 107, in <module>
class Event(m5.internal.serialize.Serializable):
AttributeError: 'module' object has no attribute 'internal'
When 'event' is loaded, it triggers 'serialize' to be loaded. However,
it seems like the dictionary of 'm5' isn't updated until after
__init__.py terminates, which means that 'event' never sees the
'internal' attribute on 'm5'. Older versions of SWIG didn't include
the fully qualified module name if the modules were in the same
package.
Andreas Sandberg [Tue, 12 Mar 2013 17:41:29 +0000 (18:41 +0100)]
cpu: Fix state transition bug in the traffic generator
The traffic generator used to incorrectly determine the next state in
when state 0 had a non-zero probability. Due to the way the next
transition was determined, state 0 could never be entered other than
as an initial state. This changeset updates the transitition() method
to correctly handle such cases and cases where the transition matrix
is a 1x1 matrix.
Nilay Vaish [Mon, 11 Mar 2013 22:45:09 +0000 (17:45 -0500)]
regressions: x86: stats updates due to new x87 insts
Nilay Vaish [Mon, 11 Mar 2013 18:15:46 +0000 (13:15 -0500)]
x86: implement some of the x87 instructions
This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.
Andreas Hansson [Thu, 7 Mar 2013 10:55:03 +0000 (05:55 -0500)]
base: Fix address range granularity calculations
This patch fixes a bug in the address range granularity
calculations. Previously it incorrectly used the high bit to establish
the size of the regions created, when it should really be looking at
the low bit.
Andreas Hansson [Thu, 7 Mar 2013 10:55:02 +0000 (05:55 -0500)]
ruby: Fix gcc 4.8 maybe-uninitialized compilation error
This patch fixes the one-and-only gcc 4.8 compilation error, being a
warning about "maybe uninitialized" in Orion.
Andreas Hansson [Thu, 7 Mar 2013 10:55:01 +0000 (05:55 -0500)]
x86: Make the table walker reset the packet delay
This patch fixes an issue related to the table walker recycling
packets that still have a bus delay that is not accounted for. For
now, we simply ignore the values and reset them to zero.
Nilay Vaish [Thu, 7 Mar 2013 03:57:10 +0000 (21:57 -0600)]
regressions: stats updates due to no physmem in ruby
Nilay Vaish [Thu, 7 Mar 2013 03:53:57 +0000 (21:53 -0600)]
ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
Nilay Vaish [Thu, 7 Mar 2013 03:53:16 +0000 (21:53 -0600)]
ruby: garnet: fixed: implement functional access
Ali Saidi [Tue, 5 Mar 2013 04:33:47 +0000 (23:33 -0500)]
stats: update patches for branch predictor and fetch updates.
Ali Saidi [Tue, 5 Mar 2013 04:33:47 +0000 (23:33 -0500)]
cpu: fix a switching issue with the o3 cpu.
This change fixes the switcheroo test that broke earlier this month. The code
that was checking for the pipeline being blocked wasn't checking for a pending
translation, only for a icache access.
Ali Saidi [Tue, 5 Mar 2013 04:33:47 +0000 (23:33 -0500)]
ARM: fix some cases where instructions that write to fp reg 15 are accidently branches.
ruby: fixes functional writes to RubyRequest
The functional write code was assuming that all writes are block sized,
which may not be true for Ruby Requests. This bug can lead to a buffer
overflow.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sun, 3 Mar 2013 00:04:51 +0000 (18:04 -0600)]
sim: remove duplicate check on stack size
Andreas Hansson [Fri, 1 Mar 2013 18:20:33 +0000 (13:20 -0500)]
mem: Add check if SimpleDRAM nextReqEvent is scheduled
This check covers a case where a retry is called from the SimpleDRAM
causing a new request to appear before the DRAM itself schedules a
nextReqEvent. By adding this check, the event is not scheduled twice.
Andreas Hansson [Fri, 1 Mar 2013 18:20:32 +0000 (13:20 -0500)]
mem: Add a method to build multi-channel DRAM configurations
This patch adds a class method that allows easy creation of
channel-interleaved multi-channel DRAM configurations. It is enabled
by a class method to allow customisation of the class independent of
the channel configuration. For example, the user can create a MyDDR
subclass of e.g. SimpleDDR3, and then create a four-channel
configuration of the subclass by calling MyDDR.makeMultiChannel(4,
mem_start, mem_size).
Andreas Hansson [Fri, 1 Mar 2013 18:20:30 +0000 (13:20 -0500)]
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Andreas Hansson [Fri, 1 Mar 2013 18:20:24 +0000 (13:20 -0500)]
mem: SimpleDRAM variable naming and whitespace fixes
This patch fixes a number of small cosmetic issues in the SimpleDRAM
module. The most important change is to move the accounting of
received packets to after the check is made if the packet should be
retried or not. Thus, packets are only counted if they are actually
accepted.
Andreas Hansson [Fri, 1 Mar 2013 18:20:22 +0000 (13:20 -0500)]
mem: Add support for multi-channel DRAM configurations
This patch adds support for multi-channel instances of the DRAM
controller model by stripping away the channel bits in the address
decoding. The patch relies on the availiability of address
interleaving and, at this time, it is up to the user to configure the
interleaving appropriately. At the moment it is assumed that the
channel interleaving bits are immediately following the column bits
(smallest sensible interleaving). Convenience methods for building
multi-channel configurations will be added later.
Andreas Hansson [Fri, 1 Mar 2013 18:20:21 +0000 (13:20 -0500)]
mem: Merge interleaved ranges when creating backing store
This patch adds merging of interleaved ranges before creating the
backing stores. The backing stores are always a contigous chunk of the
address space, and with this patch it is possible to have interleaved
memories in the system.
Andreas Hansson [Fri, 1 Mar 2013 18:20:19 +0000 (13:20 -0500)]
mem: Merge ranges in bus before passing them on
This patch adds basic merging of address ranges to the bus, such that
interleaved ranges are merged together before being passed on by the
bus. As such, the bus aggregates the address ranges of the connected
slave ports and then passes on the merged ranges through its master
ports. The bus thus hides the complexity of the interleaved ranges and
only exposes contigous ranges to the surrounding system.
As part of this patch, the bus ranges are also cached for any future
queries.
ruby: mesi coherence protocol: invalidate lock
The MESI CMP directory coherence protocol, while transitioning from SM to IM,
did not invalidate the lock that it might have taken on a cache line. This
patch adds an action for doing so.
The problem was found by Dibakar, but I was not happy with his proposed
solution. So I implemented a different solution.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Ali Saidi [Wed, 20 Feb 2013 13:18:22 +0000 (08:18 -0500)]
config: Fix --prog-interval command line option
Nilay Vaish [Wed, 20 Feb 2013 04:58:51 +0000 (22:58 -0600)]
slicc: remove unused variable message_buffer_names
Nilay Vaish [Wed, 20 Feb 2013 04:58:50 +0000 (22:58 -0600)]
ruby: remove unused variable m_print_config in class Topology
Andreas Hansson [Tue, 19 Feb 2013 17:57:47 +0000 (12:57 -0500)]
mem: Fix sender state bug and delay popping
This patch fixes a newly introduced bug where the sender state was
popped before checking that it should be. Amazingly all regressions
pass, but Linux fails to boot on the detailed CPU with caches enabled.
Ali Saidi [Tue, 19 Feb 2013 14:53:07 +0000 (09:53 -0500)]
stats: more zizzer stats fun
Andreas Hansson [Tue, 19 Feb 2013 10:56:08 +0000 (05:56 -0500)]
scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
Andreas Hansson [Tue, 19 Feb 2013 10:56:07 +0000 (05:56 -0500)]
scons: Unify the flags shared by gcc and clang
This patch restructures and unifies the flags used by gcc and clang as
they are largely the same. The common parts are now dealt with in a
shared block of code, and the few bits and pieces that are
specifically affecting either gcc or clang are done separately.
Andreas Hansson [Tue, 19 Feb 2013 10:56:07 +0000 (05:56 -0500)]
scons: Add warning delete with non-virtual destructor
This patch enables a warning for deleting derived classes that do not
have a virtual destructor. The patch merely adds additional checks,
and there are currently no cases that had to be fixed.
Andreas Hansson [Tue, 19 Feb 2013 10:56:07 +0000 (05:56 -0500)]
scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
Andreas Hansson [Tue, 19 Feb 2013 10:56:07 +0000 (05:56 -0500)]
scons: Add warning for overloaded virtual functions
Fix the ISA startup warnings
Andreas Hansson [Tue, 19 Feb 2013 10:56:06 +0000 (05:56 -0500)]
scons: Add warning for overloaded virtual functions
A derived function with a different signature than a base class
function will result in the base class function of the same name being
hidden. The parameter list and return type for the member function in
the derived class must match those of the member function in the base
class, otherwise the function in the derived class will hide the
function in the base class and no polymorphic behaviour will occur.
This patch addresses these warnings by ensuring a unique function name
to avoid (unintentionally) hiding any functions.
Andreas Hansson [Tue, 19 Feb 2013 10:56:06 +0000 (05:56 -0500)]
scons: Add warning for missing field initializers
This patch adds a warning for missing field initializers for both gcc
and clang, and addresses the warnings that were generated.
Andreas Hansson [Tue, 19 Feb 2013 10:56:06 +0000 (05:56 -0500)]
scons: Fix up numerous warnings about name shadowing
This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
Andreas Hansson [Tue, 19 Feb 2013 10:56:06 +0000 (05:56 -0500)]
mem: Enforce strict use of busFirst- and busLastWordTime
This patch adds a check to ensure that the delay incurred by
the bus is not simply disregarded, but accounted for by someone. At
this point, all the modules do is to zero it out, and no additional
time is spent. This highlights where the bus timing is simply dropped
instead of being paid for.
As a follow up, the locations identified in this patch should add this
additional time to the packets in one way or another. For now it
simply acts as a sanity check and highlights where the delay is simply
ignored.
Since no time is added, all regressions remain the same.
Andreas Hansson [Tue, 19 Feb 2013 10:56:06 +0000 (05:56 -0500)]
mem: Change accessor function names to match the port interface
This patch changes the names of the cache accessor functions to be in
line with those used by the ports. This is done to avoid confusion and
get closer to a one-to-one correspondence between the interface of the
memory object (the cache in this case) and the port itself.
The member function timingAccess has been split into a snoop/non-snoop
part to avoid branching on the isResponse() of the packet.