Marek Olšák [Sat, 2 Nov 2019 01:49:51 +0000 (21:49 -0400)]
st/mesa: rename delete_basic_variant -> delete_common_variant
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Eric Engestrom [Sun, 17 Nov 2019 23:56:49 +0000 (23:56 +0000)]
anv: add missing "fall-through" annotation
CoverityID:
1455884
Fixes: c1c346f1667375e9330a ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sat, 16 Nov 2019 17:51:27 +0000 (17:51 +0000)]
egl: use EGL_CAST() macro in eglmesaext.h
Allows eglmesaext.h to be used in C++ code.
This aligns this file with the rest of EGL.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sun, 17 Nov 2019 09:51:52 +0000 (09:51 +0000)]
vulkan: delete typo'd header
Two files exist in that directory:
- vulkan_xlib_randr.h
- vulkan_xlib_xrandr.h
Both were imported in
205c271562db8cb2effc ("vulkan: Update the XML and
headers to 1.1.70") with identical contents (ie. the
VK_EXT_acquire_xlib_display extension), but the former was never
included anywhere and can't be found upstream [1], while the latter is
included in vulkan.h and found upstream.
[1] https://github.com/KhronosGroup/Vulkan-Headers/tree/master/include/vulkan
Fixes: 205c271562db8cb2effc ("vulkan: Update the XML and headers to 1.1.70")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 17 Nov 2019 11:22:01 +0000 (11:22 +0000)]
CL: sync C++ headers with Khronos
https://github.com/KhronosGroup/OpenCL-CLHPP at commit
cf9fc1035e8298c7ce65ee33066a660fd9892ebb
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Eric Engestrom [Sun, 17 Nov 2019 11:28:53 +0000 (11:28 +0000)]
CL: sync C headers with Khronos
https://github.com/KhronosGroup/OpenCL-Headers at commit
0d5f18c6e7196863bc1557a693f1509adfcee056
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Rafael Antognolli [Wed, 13 Nov 2019 22:30:57 +0000 (14:30 -0800)]
intel: Add workaround for stencil state.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Jonathan Marek [Mon, 18 Nov 2019 23:42:12 +0000 (18:42 -0500)]
turnip: fix sRGB GMEM clear
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jonathan Marek [Mon, 18 Nov 2019 23:41:23 +0000 (18:41 -0500)]
turnip: implement CmdClearColorImage/CmdClearDepthStencilImage
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Rhys Perry [Thu, 14 Nov 2019 17:57:02 +0000 (17:57 +0000)]
radv/aco: enable VK_KHR_shader_subgroup_extended_types
We could enable it on GFX10 if LLVM wasn't used as a fallback for
unsupported stages. Note that the CTS only tests it if
VK_KHR_shader_float16_int8 is enabled, even though it's not a
requirement.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Rhys Perry [Mon, 11 Nov 2019 19:48:54 +0000 (19:48 +0000)]
aco: implement 64-bit integer reductions
The multiplication reduction is larger than it could be, but it should be
easier to implement this way.
No failures with dEQP-VK.subgroups.*int64* except those caused by LLVM
being used for other stages.
v2: don't call setFixed() for v_add carry-out, since setHint sets physReg
v3: add and use emit_vadd32() helper
v4: use num_opcodes instead of last_opcode
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v3)
Rhys Perry [Mon, 11 Nov 2019 17:37:43 +0000 (17:37 +0000)]
aco: refactor reduction lowering helpers
Should make 64-bit integer reductions easier to implement.
v4: use num_opcodes instead of last_opcode
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v3)
Samuel Pitoiset [Fri, 8 Nov 2019 11:45:03 +0000 (12:45 +0100)]
radv: advertise VK_KHR_shader_subgroup_extended_types on GFX8-GFX9
This extension allows to use subgroup operations with 8 and 16-bits
Untested on GFX6-GFX7, and most of subgroup operations are broken
on GFX10, so don't enable it for now. Not enabled on ACO because
it's still doesn't support 8-bits/16-bits.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 14:57:02 +0000 (15:57 +0100)]
ac: add 16-bit float support to ac_build_alu_op()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 16:12:39 +0000 (17:12 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_optimization_barrier()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 16:12:15 +0000 (17:12 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_wwm()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 15:35:45 +0000 (16:35 +0100)]
ac: add 8-bit and 16-bit supports to get_reduction_identity()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 13:51:40 +0000 (14:51 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_swizzle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 13:27:15 +0000 (14:27 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_dpp()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 13:15:59 +0000 (14:15 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_set_inactive()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 12:00:50 +0000 (13:00 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_readlane()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 11:44:39 +0000 (12:44 +0100)]
ac: add 8-bit and 16-bit supports to ac_build_shuffle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Nov 2019 13:12:58 +0000 (14:12 +0100)]
ac: remove useless cast in ac_build_set_inactive()
The return type is always the src type (32 or 64 bits).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 11 Nov 2019 09:15:01 +0000 (10:15 +0100)]
spirv: fix lowering of OpGroupNonUniformAllEqual
It should rely on the source type, not on the return type which
is always a boolean anyways, so vote_feq was never selected. For
OpSubgroupAllEqualKHR it's always an integer comparison.
This fixes some VK_KHR_shader_subgroup_extended_types tests with RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tomeu Vizoso [Mon, 18 Nov 2019 10:17:39 +0000 (11:17 +0100)]
gitlab-ci: Remove limit on kernel logging
We don't seem to fault any more when running dEQP GLES2, and we don't
scrape serial output any more anyway so no problems should be caused by
that.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Pierre-Eric Pelloux-Prayer [Thu, 7 Nov 2019 14:06:24 +0000 (15:06 +0100)]
mesa: fix warning in 32 bits build
Fixes: febedee4f6c ("mesa: add EXT_dsa glGetVertexArray* 4 functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 30 Oct 2019 14:11:22 +0000 (15:11 +0100)]
mesa: enable EXT_direct_state_access
Always enabled; this doesn't require any driver work, it's just
core mesa bits.
quick_gl.txt is also updated because previously piglit ext_dsa
tests were skipped.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Thu, 7 Nov 2019 13:25:19 +0000 (14:25 +0100)]
mesa: add ARB_sparse_buffer NamedBufferPageCommitmentEXT function
The spec is unclear on how to handle the buffer argument so we reuse
the logic from the EXT_direct_state_access spec.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Thu, 7 Nov 2019 12:47:17 +0000 (13:47 +0100)]
mesa: add ARB_vertex_attrib_binding glVertexArray* functions
We can't simply alias ARB_direct_state_access functions because
those fail if the vao has never been bound before.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Thu, 7 Nov 2019 09:55:23 +0000 (10:55 +0100)]
mesa: extend vertex_array_attrib_format to support EXT_dsa
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 6 Nov 2019 14:42:10 +0000 (15:42 +0100)]
mesa: implement ARB_texture_storage_multisample + EXT_dsa functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 6 Nov 2019 13:04:55 +0000 (14:04 +0100)]
mesa: add ARB_texture_buffer_range glTextureBufferRangeEXT function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 6 Nov 2019 11:16:30 +0000 (12:16 +0100)]
mesa: add ARB_instanced_arrays EXT_dsa function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 6 Nov 2019 09:57:53 +0000 (10:57 +0100)]
mesa: add ARB_gpu_shader_fp64 selector-less functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 5 Nov 2019 14:37:12 +0000 (15:37 +0100)]
mesa: add ARB_clear_buffer_object named functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 5 Nov 2019 14:04:52 +0000 (15:04 +0100)]
mesa: add ARB_vertex_attrib_64bit VertexArrayVertexAttribLOffsetEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 5 Nov 2019 13:47:53 +0000 (14:47 +0100)]
mesa: add ARB_framebuffer_no_attachments named functions
The wording in ARB_framebuffer_no_attachments and EXT_direct_state_access
is different.
In the former framebuffer names must have been generated using glGenFramebuffers
before using the named functions.
In the latter framebuffer names have no such constraints, so we can't use
the _mesa_lookup_framebuffer_dsa function.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 6 Nov 2019 09:30:13 +0000 (10:30 +0100)]
mesa: update features.txt to reflect EXT_dsa status
All features from the EXT_dsa spec are implemented.
Interactions with other specs:
- GL_AMD_gpu_shader_int64: not needed, since it's not enabled in
compatibility profile.
- GL_ARB_bindless_texture is DONE
"INVALID_OPERATION is generated when calling various functions
to modify the state of a texture object from which handles have
been extracted"
- GL_ARB_buffer_storage/GL_EXT_buffer_storage is DONE (NamedBufferStorageEXT function)
- GL_ARB_texture_storage is DONE (3 TextureStorage*DEXT functions)
- GL_ARB_vertex_attrib_binding is DONE (6 VertexArray* functions)
- GL_EXT_external_buffer is not supported by Mesa
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Alyssa Rosenzweig [Wed, 6 Nov 2019 19:55:41 +0000 (14:55 -0500)]
panfrost: Set PIPE_COMPUTE_CAP_ADDRESS_BITS to 64
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 16:18:42 +0000 (11:18 -0500)]
panfrost: Disable tiling for GLOBAL resources
It doesn't make sense to have nonlinear layouts for a buffer that can be
accessed as direct memory for a compute kernel. Turn that off so things
work as expected.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 16:19:20 +0000 (11:19 -0500)]
panfrost: Pass kernel inputs as uniforms
We can take the OpenCL kernel inputs and interpret them as uniforms by
simply reusing the Gallium callback.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 14:37:51 +0000 (09:37 -0500)]
panfrost: Stub out clover callbacks
We don't implement these yet but let's not crash.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Miguel Casas-Sanchez [Tue, 19 Nov 2019 02:21:12 +0000 (02:21 +0000)]
i965: Ensure that all
2101010 image imports can pass framebuffer completeness.
Chrome OS would like to import and render to any supported format that has
a corresponding display plane format, and this prevents throwing
framebuffer incomplete for FBOs using these textures.
See: crbug.com/949260
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dave Airlie [Mon, 18 Nov 2019 22:19:34 +0000 (08:19 +1000)]
nir/serialize: fix serializing functions with no implementations.
Store a flag stating if there was an implmentation, and use
fxn->impl as a temporary flag between deserializsation stages.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Mon, 18 Nov 2019 22:16:22 +0000 (08:16 +1000)]
nir/serialize: pack function has name and entry point into flags.
Suggested by Jason.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Mon, 18 Nov 2019 22:52:02 +0000 (16:52 -0600)]
iris: Re-enable param compaction
In
d1c4e64a69e, we added a parameter to tell the back-end compiler to
ignore the param array and just push however many constants you ask it
to push. I enabled it for iris because this is really what iris wants
but it seems to have caused a number of regressions. Revert to the old
behavior for now.
Fixes: d1c4e64a69e "intel/compiler: Add a flag to avoid compacting..."
Marek Olšák [Mon, 18 Nov 2019 20:50:31 +0000 (15:50 -0500)]
mesa: enable glthread for 7 Days To Die
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Iván Briano [Wed, 23 Oct 2019 16:18:03 +0000 (09:18 -0700)]
intel/compiler: Don't change hstride if not needed
Alignment requirements may have changed the horizontal stride already,
so don't set it if not required to avoid breaking said requirements.
Fixes several tests such as
dEQP-VK.subgroups.vote.graphics.subgroupallequal_int8_t
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jonathan Marek [Wed, 13 Nov 2019 22:02:43 +0000 (17:02 -0500)]
turnip: add x11 wsi
Copied from radv
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jonathan Marek [Wed, 13 Nov 2019 21:50:36 +0000 (16:50 -0500)]
turnip: add display wsi
Copied from radv (minus the fence change)
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jason Ekstrand [Thu, 14 Nov 2019 18:12:50 +0000 (12:12 -0600)]
nir: Validate that variables are in the right lists
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jonathan Marek [Tue, 2 Jul 2019 21:05:27 +0000 (17:05 -0400)]
etnaviv: blt: set TS dirty after clear
RS engine does this already, it is missing for BLT engine. This fixes
cases where a clear isn't immediately at the start of the frame.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Jonathan Marek [Fri, 9 Aug 2019 20:27:47 +0000 (16:27 -0400)]
etnaviv: separate PE and RS formats, use only RS only for tiling
There are PE formats not supported by RS, so we can't have a single
to translate both.
Use RS only for same formats until we have a translate_rs_format and test
the possible different format blits.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Jonathan Marek [Fri, 9 Aug 2019 14:41:22 +0000 (10:41 -0400)]
etnaviv: blt: use only for tiling, and add missing formats
* Removes the incorrect usage of translate_rs_format
* Disables use of BLT engine for different src/dst format
We only really need the BLT engine for tiling/detiling right now, but it
would be nice to support as many blit cases as possible to avoid using PE
for that.
To deal with different formats we need to:
* Have a translate_blt_format which has all supported formats
* Fix the swizzle translation from gallium (current version was wrong)
* Set the src/dst sRGB bits as needed
* Find which type conversions the BLT engine can actually do
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Brian Paul [Wed, 9 Oct 2019 18:05:16 +0000 (12:05 -0600)]
Call shmget() with permission 0600 instead of 0777
A security advisory (TALOS-2019-0857/CVE-2019-5068) found that
creating shared memory regions with permission mode 0777 could allow
any user to access that memory. Several Mesa drivers use shared-
memory XImages to implement back buffers for improved performance.
This path changes the shmget() calls to use 0600 (user r/w).
Tested with legacy Xlib driver and llvmpipe.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 8 Nov 2019 04:05:21 +0000 (22:05 -0600)]
anv: Emit a NULL vertex for zero base_vertex/instance
If both are zero (the common case), we can emit a null vertex buffer
rather than emitting a vertex buffer with zeros in it. The packing of
the VERTEX_BUFFER_STATE is faster because no relocation is emitted and
we can avoid creating the vertex buffer which means one less
anv_state_stream_alloc.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 7 Nov 2019 20:02:09 +0000 (14:02 -0600)]
anv: Use an anv_state for the next binding table
This is a bit more natural because we're already getting an anv_state
most places in the pipeline. The important part here, however, is that
we're no longer calling anv_block_pool_map on every alloc_binding_table
call. While it's probably pretty cheap, it is potentially a linear walk
over the list of BOs and it was showing up in profiles.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 7 Nov 2019 17:28:47 +0000 (11:28 -0600)]
anv: More carefully dirty state in BindPipeline
Instead of blindly dirtying descriptors and push constants the moment we
see a pipeline change, check to see if it actually changes the bind
layout or push constant layout. This doubles the runtime performance of
one CPU-limited example running with the Dawn WebGPU implementation when
running on my laptop.
NOTE: This effectively reverts
beca63c6c07. While it was a nice
optimization, it was based on prog_data and we can't do that anymore
once we start allowing the same binding table to be used with multiple
different pipelines.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 7 Nov 2019 17:44:08 +0000 (11:44 -0600)]
anv: More carefully dirty state in BindDescriptorSets
Instead of dirtying all graphics or all compute based on binding point,
we're now much more careful. We first check to see if the actual
descriptor set changed and then only dirty the stages used by that
descriptor set. For dynamic offsets, we keep a bitfield per-stage of
which offsets are actually used in that stage and we only dirty push
constants and descriptors if that stage has dynamic offsets AND those
offsets actually change.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 7 Nov 2019 20:39:28 +0000 (14:39 -0600)]
anv: Use a switch statement for binding table setup
It theoretically could be more efficient but the real point here is that
it's no longer really a matter of dealing with special cases and then
the "real" thing. The way we're handling binding tables, it's more of a
multi-step process and a switch is more natural.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 7 Nov 2019 23:16:14 +0000 (17:16 -0600)]
anv: Rework push constant handling
This substantially reworks both the state setup side of push constant
handling and the pipeline compile side. The fundamental change here is
that we're no longer respecting the prog_data::param array and instead
are just instructing the back-end compiler to leave the array alone.
This makes the state setup side substantially simpler because we can now
just memcpy the whole block of push constants and don't have to
upload one DWORD at a time.
This also means that we can compute the full push constant layout
up-front and just trust the back-end compiler to not mess with it.
Maybe one day we'll decide that the back-end compiler can do useful
things there again but for now, this is functionally no different from
what we had before this commit and makes the NIR handling cleaner.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Nov 2019 16:59:15 +0000 (10:59 -0600)]
anv: Re-arrange push constant data a bit
This moves the compute stuff into a anv_push_constants::cs sub-struct.
It also moves dynamic offsets into the push constants. This means we
have to duplicate the data per-stage but that doesn't seem like the end
of the world and one day we may wish to make dynamic offsets per-stage
anyway.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 31 Oct 2019 20:57:52 +0000 (15:57 -0500)]
intel/compiler: Add a flag to avoid compacting push constants
In vec4, we can just not run the pass. In fs, things are a bit more
deeply intertwined.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 8 Nov 2019 15:42:30 +0000 (09:42 -0600)]
anv: Pre-compute push ranges for graphics pipelines
It turns off that emitting push constants is one of the hottest paths in
the driver and ANY work we do there costs us. By pre-computing things a
bit ahead of time, we shave 5% off the runtime of a CPU-limited example
running with the Dawn WebGPU implementation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 8 Nov 2019 15:33:07 +0000 (09:33 -0600)]
anv: Stop bounds-checking pushed UBOs
The bounds checking is actually less safe than just pushing the data.
If the bounds checking actually ever kicks in and it's not on the last
UBO push range, then the shrinking will cause all subsequent ranges to
be pushed to the wrong place in the GRF. One of the behaviors we
definitely don't want is for OOB UBO access to result in completely
unrelated UBOs returning garbage values. It's safer to just push the
UBOs as-requested. If we're really concerned about robustness, we can
emit shader code to do bounds checking which should be stupid cheap (a
CMP followed by SEL).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Nov 2019 20:13:44 +0000 (14:13 -0600)]
anv: Delete dead shader constant pushing code
As of
2d78e55a8c5481, nir_intrinsic_load_constant with a constant offset
is constant-folded so we should never end up with any that trigger
brw_nir_analyze_ubo_ranges.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 31 Oct 2019 19:09:39 +0000 (14:09 -0500)]
anv: Flatten descriptor bindings in anv_nir_apply_pipeline_layout
This lets us stop tracking the pipeline layout. It also means less
indirection on a very hot path. As an extra bonus, we can make some of
our data structures smaller. No measurable CPU overhead improvement.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 31 Oct 2019 21:57:29 +0000 (16:57 -0500)]
anv: Input attachments are always single-plane
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 31 Oct 2019 15:25:48 +0000 (10:25 -0500)]
genxml: Mark everything in genX_pack.h always_inline
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Nov 2019 17:19:00 +0000 (11:19 -0600)]
anv/pipeline: Assume layout != NULL
In the early days of the driver we allowed layout to be VK_NULL_HANDLE
and used that for some internal pipelines when we wanted to be lazy.
Vulkan doesn't actually allow NULL layouts, however, so there's no
reason to have this check.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Italo Nicola [Fri, 8 Nov 2019 14:29:59 +0000 (11:29 -0300)]
intel/compiler: remove old comment
This comment was correct some time ago, but since commit
d3c10ad42729c1fe74a7f7c67465bd2, it isn't true anymore.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Alyssa Rosenzweig [Mon, 18 Nov 2019 13:02:58 +0000 (08:02 -0500)]
pan/midgard: Use shader stage in mir_op_computes_derivative
A 'normal' texture op may be emitted in a vertex shader on T720 but it
still doesn't take any derivatives.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Danylo Piliaiev [Thu, 14 Nov 2019 13:36:27 +0000 (15:36 +0200)]
i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround
Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting
3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in
SuperTuxCart and Tropico 6 which was seen only on Haswell.
The reason for this is unknown and fix was found empirically.
The closest mention in PRM is that it should improve performance.
From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS):
"When the BLEND_STATE pointer changes but not the CC_STATE pointer,
driver needs to force a CC_STATE pointer change to improve
blend performance in pixel backend."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834
Fixes: eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Wed, 13 Nov 2019 07:58:37 +0000 (08:58 +0100)]
radv: implement VK_AMD_device_coherent_memory
This extension adds the device coherent and device uncached memory
types. It's known to be slower than non-device coherent memory but
it might be useful for debugging.
This is only exposed for chips that support L2 uncached.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Nov 2019 16:17:21 +0000 (17:17 +0100)]
ac: add radeon_info::has_l2_uncached
For chips that have uncached device memory (ie. MTYPE_UC).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Pierre-Eric Pelloux-Prayer [Tue, 29 Oct 2019 14:58:04 +0000 (15:58 +0100)]
radeonsi: enable mesa_glthread for GfxBench
It improves offscreen tests performance.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Alyssa Rosenzweig [Fri, 15 Nov 2019 19:19:34 +0000 (14:19 -0500)]
pan/midgard: Represent ld/st offset unpacked
This simplifies manipulation of the offsets dramatically, fixing some
UBO access related bugs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 15 Nov 2019 20:16:53 +0000 (15:16 -0500)]
pan/midgard: Fix masks/alignment for 64-bit loads
These need to be handled with special care.
Oh, Midgard, you're *extra* special.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 15 Nov 2019 20:16:28 +0000 (15:16 -0500)]
pan/midgard: Expose more typesize helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 15 Nov 2019 19:13:18 +0000 (14:13 -0500)]
pan/midgard: Implement non-aligned UBOs
The field is more fine-grained than we had assumed.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Christian Gmeiner [Sat, 9 Nov 2019 18:27:54 +0000 (19:27 +0100)]
etnaviv: rs: upsampling is not supported
This change makes it possible to support different downsample cases
like 4 -> 2 or 4 -> 1.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Jonathan Marek [Fri, 15 Nov 2019 20:34:09 +0000 (15:34 -0500)]
freedreno/registers: fix a6xx_2d_blit_cntl ROTATE
A change from
b7093882 got overwritten by
610c8c93
Fixes: 610c8c93 ("freedreno/registers: Update with GS, HS and DS registers")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Jonathan Marek [Fri, 15 Nov 2019 17:38:28 +0000 (12:38 -0500)]
freedreno/ir3: disable texture prefetch for 1d array textures
Prefetch only supports the basic 2D texture case, checking is_array is
needed because 1d array textures pass the coord num_components==2 test.
Fixes: 2a0d45ae ("freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetch")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Andreas Baierl [Fri, 25 Oct 2019 14:38:52 +0000 (16:38 +0200)]
lima: Parse VS and PLBU command stream while making a dump
This makes the streams more readable and comparable with the blob's parser
as it parses the VS and PLBU stream and shows the currently known values.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Andreas Baierl [Thu, 17 Oct 2019 10:21:13 +0000 (12:21 +0200)]
lima: Beautify stream dumps
Change the dump, that the output looks more like the output of
mali-syscall-tracker [1].
This is a preparation for a more detailed stream analysis.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
[1]: https://gitlab.freedesktop.org/lima/mali-syscall-tracker
Aaron Watry [Fri, 15 Nov 2019 04:44:02 +0000 (22:44 -0600)]
clover/llvm: fix build after llvm 10 commit
1dfede3122ee
CodeGenFileType moved from ::llvm::TargetMachine in
llvm/Target/TargetMachine.h to ::llvm:: in llvm/Support/CodeGen.h
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Mauro Rossi [Fri, 15 Nov 2019 22:54:52 +0000 (23:54 +0100)]
android: util/format: fix include path list
To avoid following building error:
out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_util_intermediates/format/u_format_table.c:30:10:
fatal error: 'u_format.h' file not found
^~~~~~~~~~~~
1 error generated.
Fixes: 882ca6d ("util: Move gallium's PIPE_FORMAT utils to /util/format/")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Mauro Rossi [Fri, 15 Nov 2019 22:13:49 +0000 (23:13 +0100)]
android: radeonsi: fix build error due to wrong u_format.csv file path
GEN10_FORMAT_TABLE_INPUTS requires correction of u_format.csv file path
in order to avoid following build error:
ninja: error: 'external/mesa/util/format/u_format.csv',
needed by 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/gfx10_format_table.h',
missing and no known rule to make it
Fixes: 882ca6d ("util: Move gallium's PIPE_FORMAT utils to /util/format/")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Eric Anholt [Tue, 17 Sep 2019 19:39:23 +0000 (12:39 -0700)]
mesa/st: Reuse st_choose_matching_format from st_choose_format().
We had this ad-hoc exact size matching for unsized internalformats,
but st_choose_matching_format() can do exactly what we want. This
means, that, for example, we'll now prefer the matching ordering for
565/565_REV if the driver supports both orders. We also pass
Unpack.SwapBytes through from ChooseTextureFormat so that we can hit
the memcpy path for 8888 formats when that flag is set.
Some interesting format choice changes from this (on softpipe):
intf/form/type before after
----------------------------------------------------
RGBA/RGBA/USHORT: R8G8B8A8_UNORM -> RGBA_UNORM16
RGB/RGBA/8888: X8B8G8R8_UNORM -> R8G8B8X8_UNORM
RGB/ABGR/8888_REV: X8B8G8R8_UNORM -> R8G8B8X8_UNORM
RGBA/RGBA/5551: B5G5R5A1_UNORM -> A1B5G5R5_UNORM
RGBA/RGBA/4444: R8G8B8A8_UNORM -> A4B4G4R4_UNORM
RGBA/GL_RGBA/
1010102: R8G8B8A8_UNORM -> A2B10G10R10_UNORM
DEPTH/DEPTH/UINT: Z24X8 -> Z_UNORM32
DEPTH/DEPTH/USHORT: Z24X8 -> Z_UNORM16
v2: Make sure that the baseformat still matches. v1 would pick
MESA_FORMAT_L16_UNORM for RED/LUMINANCE/SHORT, when we clearly
want a red format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Fri, 15 Nov 2019 01:41:27 +0000 (17:41 -0800)]
mesa: Don't put sRGB formats in the array format table.
sRGB vs unorm was the only conflict case being guarded against in this
function. Before the PIPE_FORMAT conversion, we always listed the
unorm before the sRGB in the enums, but PIPE_FORMAT_A8B8G8R8_SRGB
happens to be before _UNORM. We always want the unorm result here.
Fixes: 807a800d8c3e ("mesa: Redefine MESA_FORMAT_* in terms of PIPE_FORMAT_*.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 17 Sep 2019 22:13:30 +0000 (15:13 -0700)]
mesa/st: Simplify st_choose_matching_format().
We now have a nice helper function for finding those memcpy formats,
without needing to go through each entry of the mesa format table to
see if it happens to match.
While looking at sysprof of a softpipe GLES2 CTS run, we were spending
~8% of the CPU on ChooseTextureFormat. With this, roughly the same
region of the testsuite was .4%.
v2: Add Ken's fix for canonicalizing array formats.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 13 Nov 2019 07:12:54 +0000 (23:12 -0800)]
mesa: Handle GL_COLOR_INDEX in _mesa_format_from_format_and_type().
Just return MESA_FORMAT_NONE to avoid triggering unreachable; there's
really no sensible thing to return for this case anyway.
This prevents regressions in the next commit, which makes st/mesa
start using this function to find a reasonable format from GL format
and type enums.
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Tue, 5 Nov 2019 14:06:41 +0000 (09:06 -0500)]
pan/midgard: Use generic constant packing for 8/64-bit
Eventually, we will want to combine constants across types, but for now
let's not break the world.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 13:50:29 +0000 (08:50 -0500)]
pan/midgard: Pack 64-bit swizzles
64-bit ops have their own funky swizzles. Let's pack them, both for
native 64-bit sources as well as extended 32-bit sources.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 03:21:47 +0000 (22:21 -0500)]
pan/midgard: Fix mir_round_bytemask_down for !32b
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 03:21:20 +0000 (22:21 -0500)]
pan/midgard: Implement i2i64 and u2u64
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 5 Nov 2019 03:20:59 +0000 (22:20 -0500)]
pan/midgard: Expand 64-bit writemasks
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Marek Olšák [Wed, 13 Nov 2019 05:21:54 +0000 (00:21 -0500)]
radeonsi/nir: don't lower fma, instead, fuse fma
We want fma. This decreases compile times by 4% for Borderlands 2.
48505 shaders in 30515 tests
Totals:
SGPRS:
2206584 ->
2204784 (-0.08 %)
VGPRS:
1647892 ->
1648964 (0.07 %)
Spilled SGPRs: 6256 -> 6078 (-2.85 %)
Spilled VGPRs: 72 -> 72 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2240 -> 2240 (0.00 %) dwords per thread
Code Size:
49680804 ->
49837988 (0.32 %) bytes
LDS: 74 -> 74 (0.00 %) blocks
Max Waves: 371387 -> 371352 (-0.01 %)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 13 Nov 2019 04:41:23 +0000 (23:41 -0500)]
radeonsi/nir: call nir_lower_flrp only once per shader
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sat, 9 Nov 2019 01:16:20 +0000 (20:16 -0500)]
radeonsi/nir: remove dead function temps
glxgears has dead temps after lowering color inputs to load intrinsics.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>