mem-ruby: MESI_Three_Level discriminate L0 invalidation reason

The L0 cache can now know whether a line is being invalidated
due to this cache/core's own requirements, e.g. a load from the core
causing a line eviction, or due to another cache/core's requirements,
e.g. a remote cache requesting a present line in exclusive state.

Change-Id: If57bfb92b6c8f575ca47d984606be7c859dcff9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24259
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-ruby: MESI_Three_Level fix L1 MRU absence

The L1 cache is updating the MRU tag after acessing a cache line.
This patch updates MRU for cases when the L0 cache loads/stores
a line from/to the L1 cache.

Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-ruby: MESI_Three_Level fix L1 in_port ranks

The L1 cache contains three in_port networks with ranks 0-2-3.
This is a benign typo, however, this patch corrects the ranks to
0-1-2 for clarity.

Change-Id: Id9bb63dae310af0f962345a114b0ccb8bddcf696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24257
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch,sim: Merge Process::syscall and Process::getDesc.

When handling a system call, external code would call Process::syscall
which would extract the syscall number, that would call the base
class' doSyscall method, that would call into the subclass' getDesc
to get the appropriate descriptor, and then doSyscall would check
that a syscall was found and call into it.

Instead, we can just make the SyscallDescTable optionally check for
missing syscalls (in case we want to check multiple tables), and
make syscall look up the appropriate descriptor and call it. The base
implementation of syscall would then do the only bit of doSyscall that
is no longer being handled, incrementing the numSyscalls stat.

Change-Id: If102c156830ed2997d177dc6937cc85dddadf3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24119
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arch,sim: Drop the syscall number from the syscall func signature.

This value is almost never used, and is now part of the SyscallDesc.

Change-Id: Ia4ffc19774bb2eac8f29134e3765c06a264407b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24118
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Create a common structure to hold syscall tables.

Also add the syscall number into the SyscallDesc class.

The common table structure is basically just a map that extracts its
key value from the SyscallDesc class using a new num() accessor. By
using a map instead of an array (like RISCV was already doing), it's
easy to support gaps of arbitrary size and non-zero offsets of groups
of system calls without lots of filler or additional logic. This
simplified the ARM system call tables in particular which had a lot
of filler entries.

Also, both the 32 and 64 bit ARM syscall tables had entries for a
syscall at 123456 which was the "Angel SWI system call". This value
is actually the immediate constant passed to the SWI system call
instruction and is not interpreted as the system call number in linux.
This constant can be intercepted by hardware or a simulator to, for
instance, implement ARM semihosting.

Also, that constant in combination with the SWI instruction is only
used for semihosting in 32 bit ARM mode, not in 64 bit mode or in
thumb.

Since checking for that system call number was very likely a mistake
from misinterpreting how the semihosting calls work, this change
drops those checks.

Change-Id: I9b2a902d7326791449cf0e1b98e932dcadba54f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the Arguments class.

This class read arguments using the arch specific getArgument function
and then presented the arguments as an array. The problem with that
approach is that it's not possible to tell where different arguments
are without knowing the types of previous arguments, and not all
arguments can be simply represented as a native sized integer.

This class has been phased out and is no longer needed.

Change-Id: Ibb4c529fe8c51fd0ae15ed3b6ea30543ad9c23e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-ruby: MESI_Three_level HTML reference generation fix

The SLICC HTML generator does not work without the 'desc' property of
the STATES and EVENTS found in the protocol state machine source files.
This adds the 'desc' property in MESI_Three_Level to declarations where
it was missing and cleans up the text of some existing ones.

Issue-on: https://gem5.atlassian.net/browse/GEM5-357

Change-Id: I2d0f8e11889554063fed798e724217963d4a74de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24256
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

sparc: Add the AT_RANDOM aux vector to the initial stack.

This is blindly used by at least modern glibc-s

Change-Id: I175ce5f1495e367badf0fab32f5837e3cdfa955a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26824
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

util: Add the ability to build a cross GDB to build_cross_gcc.py.

This is a very simple extension to what's already there.

Change-Id: I07e3711244e0de96b215f16ec05c660b19e462b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26765
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

base: Convert the annotation methods to take actual arguments.

Feed the arguments in from the decoder.

Change-Id: Ie2dcd09320a5de02bb91b8743fc643c446e506e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24114
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arm,kern: Use GuestABI to call printk from the kernel.

Change-Id: I07b0f1c01f5ec8d6761903fa4aa15b9e8ae35069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24113
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arm: Use a non-template indexed version of laneView in aapcs32.

The lane number is constant over its lifetime, but is computed with a
variable i which is not a compile time constant. It therefore can't be
used as a template parameter, and should be marked as const and not
constexpr.

Change-Id: Ie0b950311495831d5224a8fb397cf42d5cf5f25b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26834
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a script to help build cross compilers.

Cross compilers are very useful when working with gem5. The how-to this
script is based on assumed the compiler was targeting linux, so there
isn't any support for compilers targeting other or no OS. That might be
possible to add in the future.

Change-Id: I2cb30ecbdd4c6292146ea64940348c24385046f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26763
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Add --bin-path option to insttest regressions

Change-Id: I229f37782b1c3650dc71ee481823b41f6f67e590
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26483
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch-arm: Fix ArmSystem::_resetAddr evalutation

With:

https://gem5-review.googlesource.com/c/public/gem5/+/26466

The ArmSystem reset address (_resetAddr) is always forced by the
workload:

 _resetAddr = workload->entry

So there is no possibility to manually specify a reset address.

This was not the case before:
The resetAddr was forced only if auto_reset_addr was true or if there
was an associated bootloader to the kernel image. In that case even if
auto_reset_addr was false, the reset address was determined by the
bootloader entry.
This was also not ideal (but it was working)

This patch is cleaning all of this:

If you want to have automatic detection (recommended), you would need to
set auto_reset_addr (now turned to true by default).  This will allow to
keep most fs script untouched.  If you don't want to use automatic
detection, set auto_reset_addr to False and provide your own reset
address.

Change-Id: I5d7a55fd9060b9973c7d5b5542bd199950e1073e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26723
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

dev-arm: SMMUv3, single interconnect attachment

The attachment (port binding) of the SMMUv3 master and control
ports is independent of the connection of device masters to it.

This behaviour is now moved from SMMUv3::connect to
RealView::attachSmmu, as it is a responsibility of the Platform
designer.

This fixes crashes when connecting multiple device masters.

Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26923
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

sim-se: Implement Virtual Memory Area API

Virtual memory areas are used to track regions of memory which may
change over the course of execution, such as heap, stack, and mmap. It
is a high-level mimicry of Linux' memory management. VMAs are intended
to be used to support lazy allocation of physical pages to valid VMAs
as the virtual addresses are touched. Lazy allocation increases speed
of simulation for SE mode processes which, for example, mmap large
files.

The VMAs can also be queried to generate a map of the process' memory
which is used in some libraries such as pthreads.

This changeset only adds APIs for virtual memory areas. These are used
in a subsequent changeset.

Change-Id: Ibbdce5be79a95e3231d2e1c9ee8f397b4503f0fb
Signed-off-by: Brandon Potter <Brandon.Potter@amd.com>
Signed-off-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25365
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add a Request::Flags parameter to the translating port proxies.

These flags will be given to the Request object which is used to do the
translation.

Change-Id: I21755f5f9369311e2f2d5be73ebd4f5865f73265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26623
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,base,cpu,dev,kern,mem,sim: Drop FS from FSTranslatingPortProxy.

This translating proxy can be used in FS, or in SE with a failure
handing case in place.

Change-Id: I2e6421f52529fa833e42f8d3e64d4341c282634f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26551
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu,mem,sim: Reimplement the SE translating proxy using the FS one.

The only functional difference between them was that the SE one might
have optionally fixed up missing translations for demand paging.

This lets us get rid of some code recreating the proxy ports in
setProcessPtr since the SE translating port no longer keeps a copy of
the process object pointer.

Change-Id: Id97df1874f1de138ffd4f2dbb5846dda79d9e4ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26550
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

sparc: Make translateFunctional ignore alignment and use the page tables.

translateFunctional might be used with unaligned addresses which should
be allowed in that context. Also, in SE mode, if the translation isn't
in the TLB itself, then it should be looked up in the SE mode fake page
tables and not in a page table resident in memory.

Change-Id: Ibb39685cfdcd4eb6cb8a0486a1de014a4e452518
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Eliminate vtophys and its switching header file.

This function is no longer used anywhere in gem5.

Small helper functions which had been put alongside vtophys on ARM and
RISCV were also moved into src/arch/arm/remote_gdb.cc and
src/arch/power/pagetable.hh, the only places they were used.

Change-Id: Iba72f6c4b797a35a785a5bb781d602c943541fa7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Make the FSTranslatingPortProxy stop using vtophys.

That was the only place vtophys was still being used. Instead, use the
data TLB to translate functional, and if that fails try the the
instruction TLB.

Change-Id: Ie5e1e1b5d470f010e25482d785f111dc4292db60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26233
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Demote PCEvent subclass pointers to PCEvent pointers.

Nothing is actually accessed through these pointers. This simplifies
their declration, and gives more flexibility when setting up those
events.

Change-Id: If857de5c8df37b6ead7eae53e3c0c6c3103938c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24112
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

riscv: Implement translateFunctional.

Change-Id: Ibe8adea8f66c7de22ee2ab0da54e866cd05fc257
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26547
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,kern: Rename some function events to have better names.

Rename many of the Event classes to have more succinct or
consistent names, and fix various style issues.

Change-Id: Ib322da31d81e7a245a00d21786c2aa417c9f2cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26703
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Use relative path for python3 compliance

Change-Id: Ie18c52982e2083d0fc2723147f2493b39bcb3786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Do not treat addresses < 10 specially

The RSP stub (base/remote_gdb.cc) treats virtual addresses below 0x000A as
meaning "the address used in the previous m-packet".  This leads to nasty
surprises, and is not justified by neither the RSP protocol documentation
nor other existing RSP implementations.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-407

Change-Id: I5fccc10a58d9af856eeee6d45418905c0f47ffab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26605
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

tests: Increased Kokoro's timeout to 5 hours

Change-Id: Ice9fc5f17dfa06f61bc5583ecca15c54742bc254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26843
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removed old scon-based 40.m5threads-test-atomic tests

These have been migrated to be run via testlib.

Change-Id: I186e4048096f718c0de378033924cd23328168d7
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25843
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 40.m5threads-test-atomic scons tests to testlib

At present, the 40.m5threads-test-atomic tests fail as the SPARC binary
(generated from `tests/test-progs/pthread/src/test_atomic.cpp`) is not
present. This has been noted in:
https://gem5.atlassian.net/browse/GEM5-368

Change-Id: I7865826388be46cec06a201712081146a58518f2
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25824
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,arch-alpha: Removing ALPHA ISA from testlib config

Change-Id: Icded5f4aec7bc212a818a97c4de5d7b8f8757121
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26823
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

kern,arch: Refactor SkipFuncEvent to not use skipFunction.

Replace it with a new virtual function.

Change-Id: I9d516d21ab3b1d1d70ea1297f984f868d3e7c3fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24111
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Implement translateFunctional.

This function is based off of vtophys in the full system case, and off
of the page table fill mechanism used in SE mode. It ignores what's
already in the TLB, and also ignores protection mechanisms.

This may need to be reworked in the future if, for instance, pages
still resident in the TLB but not in the page tables need to be
considered, but it should work at least for the time being.

Change-Id: If21701ca36a30805f4199312933a8afc91f20501
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26405
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 80.dram scons-based tests to testlib framework

"configs/dram/low_power_sweep.py" has been modified to keep the
generated "lowp_sweep.cfg" file in "configs/dram". This generated file
is now ignored by git.

Change-Id: I700d04944fee58f8a506c71fd474b84024ec4374
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25923
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in CrossbarSwitch

There is no need to dynamically allocate these variables.

Change-Id: I6efeaffe75f2b4ba706c26d2a12c42c07dc7c7ee
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24983
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use smart pointers in Router's members

Use smart pointers for the pointers managed by Router, and do
static allocation when possible.

Change-Id: I5fad8b2d17ac7950d478d37000ac80a4d2f68b15
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24248
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in Switch

Make pointers non pointers when possible.

Change-Id: I272387c2ac1fd77deef06feb637127e232910e30
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24250
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in NetworkLink

Use static allocation to manage NetworkLink's pointers.

Change-Id: I3ab22b1f912f0119448f9013fd0dfff9bf5a6999
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24252
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in NetworkInterface

Use static allocation for the pointers managed by NetworkInterface.

Change-Id: Ib97d95165337659f92cb8a078020692baae5b5ca
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24247
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in InputUnit

Use static allocation for the pointers managed by InputUnit.

Change-Id: I3eab42c6c08b1a519b9b55de26e820bad2ef03c4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24245
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in OutputUnit

Use static allocation for the pointers created by OutputUnit.

Change-Id: Ica4fd5d4994078764769702311520c9daf8dba72
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24243
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in VirtualChannel

The input buffer does not need to be dynamically allocated.

Change-Id: Ice64f40d2a7e16af325ddb6803e34b3eed2e99db
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24253
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Remove delete of param pointers of SimpleNetwork

All over gem5 the params pointers are not deleted within the classes
that they were created for. Although this is a potential memory leak
as of now, it is probably safer to follow general convention so that
it can be fixed at once in the future.

Change-Id: If96f04058d51513fa8763610880e5524785ee9cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24249
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Remove delete of param pointers of GarnetNetwork

All over gem5 the params pointers are not deleted within the classes
that they were created for. Although this is a potential memory leak
as of now, it is probably safer to follow general convention so that
it can be fixed at once in the future.

Change-Id: I74b662a8e635cdfb4dc1eae732dd114659fab2e9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24246
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add static assert to trie

Trie is based on the condition that they key is an integral. As so,
add a static_assert to guarantee that. Also, added some general info
about tries to the class.

Change-Id: Idc18f6a685db8047cd44b791f427666d3dd2d187
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26784
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Hook up pread64 in 32/64 bit linux, and pwrite64 in 32 bit.

My new computer has a dynamic linker which seems to use the pread64
system call, and since that gets pulled in when running tests, that
needs to be implemented for tests to pass on that machine, making it
possible to detect problems the failure might ohterwise mask.

This is only really necessary for 64 bit linux, but while I'm here I
hooked it up for 32 bit linux as well. I also added pwrite64 for 32 bit
linux since that was only enabled for 64 bit.

Change-Id: I8d2061d30e98a1581c5e30b522b6ba12aea20ecd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26604
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Provide an implementation for the pread64 system call.

This implementation is very similar to the pwrite64 system call, just
with data going the other direction as you'd expect.

Change-Id: I4f8ec9d83bf2339f9c84e31f25309c58e6157304
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26603
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: fix forwarding of --bootloader to fs.py

Since I02919207d6f175854017ae7b603d811da63d618e the fs.py --bootloader
option can be used to select a bootloader explicitly.

Ia3d863db276a023b6a2c7ee7a656d8142ff75589 forgot to pass that parameter
likely due to a rebase issue and it gets searched in M5_PATH.

Change-Id: Ic4cf3ccf041e1c34eac7753424fe842bd34a77f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26724
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Fix regStats for PowerModel and PowerModelState

Every Stats::Group need to call the parent regStats to
make sure that the base Stats::Group::regStats() gets
called

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-319

Change-Id: I931941d8ec5f375f7e51e719d43ae31af095f661
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26643
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Add Python 3 workarounds for long

Python 3 doesn't have a separate long type. Make long an alias for int
where needed to maintain compatibility.

This is aligning with https://gem5-review.googlesource.com/c/15988

Change-Id: I20e52d7f796d143534fa7dabeb6ff0ae8b62fd2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26257
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-x86: Fix imports for Python 3 compatibility

Change-Id: I7e486a6f3d38af54ac1eff431ca40a5af29e3ca7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26256
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Use relative path for python3 compliance

Change-Id: I9a45a7800f1b69037781374df86e29bd5eb0f014
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26255
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: list.sort() sorting by key only in python3

list.sort() no longer accept a comparison function. Use the key argument
instead for key based sorting.

Change-Id: I2af2732628721faee3870af0d53c1267839896da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Fix VExpressFastmodel.py indentation

Convert TAB with four spaces

Change-Id: I7472a01423953c68aed60b37f56fe86eca249fac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26253
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: Convert exec keyword to exec() function

The function syntax was also accepted in 2.x

Change-Id: I3d9bef3ddcd5e98ff589796d21dbfeb9796bff1d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: Bring closure out of p_global_let

The python interpreter might complain when exec() (the function, not the
python2 keyword) is used in a function and the function contains a nested
block.

See: https://www.python.org/dev/peps/pep-0227/

The patch is moving the nested function out of p_global_let.

Change-Id: Idb3a08a8cd42455af1e5ec2c3ec8f8a1438047d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26303
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Make exception handling python3 compliant

Change-Id: I37d0e97e9762e21c7a0ad315cf7684a19119b5b4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Text vs Byte string in python3

Python 3 uses the concepts of two different types:
text and binary strings.
Those cannot be implicilty combined (as it was happening in python2) and
in order to be used together one of them must be converted to the other
type:

* Text can be encoded into Bytes via the encode() method
* Bytes can be decoded to Text using the decode() method

By default encode/decode will assume UTF-8 format

JIRA: https://gem5.atlassian.net/browse/GEM5-345

Change-Id: I1bdf7db17b49cc109239fd5f44791769370853f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26250
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

scons: file removed from python3

Change-Id: I95794fec5cc9c6e72c9ae53f586052be71436c87
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26249
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Views and Iterators instead of Lists in python3

* dict methods dict.keys(), dict.items() and dict.values()
return "views" instead of lists

* The dict.iterkeys(), dict.iteritems() and dict.itervalues()
methods are no longer supported.

* map() and filter() return iterators.

* range() now behaves like xrange() used to behave, except it works with
values of arbitrary size. The latter no longer exists.

* zip() now returns an iterator.

Change-Id: Id480018239db88d7f5d60588c93719056de4a0c0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26248
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix setupBootloader for VExpressFastmodel

Previous fix setupBootloader for VExpress_GEM5_V2 didn't include
VExpressFastmodel. Fix it.

Change-Id: Ia720978848660be63bb788ffaf84b60a5b1b5db5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26684
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix Arch detection in FS if there is not bootloader

In case a workload is run with no bootloader we still want to be able
to provide the simulation with the correct arch version.
Without this patch every baremetal simulation will default to AArch64, which
is the default value of ArmFsWorkload.

Change-Id: I0f766167d8983cafc1fd30d054862339eb21f73f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26606
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix fast-forward when using the backing store.

While the up-to-date data may reside in any agent of Ruby's memory
hierarchy, there's an optional backing store in Ruby that provides
a 'correct' view of the physical memory. When it is enabled by the
user, every Ruby memory access will update this global memory view
as well upon finishing.

The issue is that Ruby's atomic access, used in fast-forward, does
not currently access the backing store, leading to data
incorrectness. More specifically, at the very beginning stage of the
simulation, a loader loads the program into the backing store using
functional accesses. Then the program starts execution with
fast-forward enabled, using atomic accesses for faster simulation. But
because atomic access only accesses the real memory hierarchy, the CPU
fetches incorrect instructions.

The fix is simple. Just make Ruby's atomic access update the backing
store as well as the real physical memory.

Change-Id: I2541d923e18ea488d383097ca7abd4124e47e59b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26343
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Eliminate the MustBeOne ARM specific request flag.

This flag makes constructing a generic Request object for ARM
impossible, since generic consumers won't know to set that flag to one.

As a principle, Request flags should change the behavior of a request
away from whatever the default/typical behavior is in the current
context, so flags set to zero means no special behavior.

Change-Id: Id606dc0bf42210218e1745585327671a98a8dba4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26546
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: add FVP Base Power Controller model

This is a reduced model of the FVP Base platforms Power Controller.
As of now it allows the following functions from software:
- Checking for core presence
- Reporting the power state of a core / cluster
- Explicitly powering off a core on WFI
- Explicitly powering off cores in a CPU cluster on WFI
- Explicitly powering on a core through writes to PPONR register

Change-Id: Ia1d4d3ae8e4bfb2d23b2c6077396a4d8500e2e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26463
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite getMPIDR

This patch is rewriting getMPIDR to have a more canonical form:

* Using threadId() instead of contextId()

It is also splitting the helper so that a client can get an affinity
number given a specific thread context.

Change-Id: I727e4b96ada345fd548cd3ff9423bf27347812c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26304
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

kern: Minor style cleanup in the base SkipFuncEvent class.

Change-Id: I0f4efb825b0611d3bab5a429fd36d28a178f86b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24110
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Implement the AAPCS32 ABI.

Change-Id: I63b2ec586146163642392f5164fb01335d811471
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24108
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Rename GuestABI's Position to State.

This type can hold any generic state related to locating return types
and arguments in addition to simple position information. To make that
clearer, this change renames the Position type to State.

Change-Id: I50ff2ec61c3eba0e9505c66ce32e27b515bd4b27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24107
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Rename allocate in GuestABI to prepare.

This method can be used for allocating resources for registers and/or
arguments, but it can also be used for generic preparation for them
as well. For instance, it can be used to detect some sort of property
of the function signature as a whole (if it's variadic for instance)
which can be stored in position and used to change ABI behavior.

Change-Id: I8a090be65dc4987e35cd115562114cd1b748155f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24106
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Optionally pass "position" to GuestABI::Result::store.

This will let it get at information about the signature as a whole.

Also, put result storing and argument getting behind functions to hide
some of the templating involved in those mechanisms.

Change-Id: Ib9f26ff69495f8891435f68d3d2f9dfa761a0274
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24105
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Split up the guest_abi.hh header.

This header was getting pretty long, and could be broken up into a few
headers which logically grouped related definitions and concepts.

To maintain compatibility and keep things simple for users of the
mechanism, there is still a top level header with the original name
which defines the interface for using ABIs. It includes all the other
new headers, and so can also be used when defining ABIs.

Change-Id: I62a051b9bd982e0fcecfceeb3d658d1ff4d30c5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Generalize the GuestABI Result::allocate() mechanism.

This change generalizes the GuestABI Result template family's
allocate() mechanism so that it can also be used with arguments. This
is useful in cases like the 32 bit ARM ISA which says that variadic
functions treat their floating point arguments differently than
non-variadic functions do. This mechanism will give the ABI a chance
to detect that the function is variadic (by checking for VarArgs) and
then to behave differently in that case.

This also makes the GuestABI mechanism a little more regular by
supporting allocate() on both arguments and return values instead of
just return values.

Change-Id: I67050a0ad7ccf15ee75b800dca4eae4fdc0e564e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Implement the AAPCS64 ABI.

This implementation has been tested a tiny bit by intercepting a call
which passed an argument of this type to a function.

struct Test
{
    int32_t a;
    float *b;
};

The gem5 intercept printed out the value of a, the value of b, and the
value of the float it pointed to.

I was able to get things to work by commenting out the panic in
fixFuncEventAddr and making it return its argument unmodified, and by
calling addFuncEvent instead of addKernelFuncEvent which injects the
kernel symbol table. I substitured the Process's debugSymbolTable which
had the right symbols.

Note that this implementation is not completely correct. First of all,
I used a dummy type in place of the Short Vector type which is just
a byte array with the appropriate alignment forced on it. It sounds
like this type would be something the compiler would need an intrinsic
and architecture specific type for to behave correctly, and so in
gem5 we'd have to define our own type for ARM which could feed in here.

Also, strictly speaking, it sounds like HVA and HFA category of types,
the Homogeneous Short-Vector Aggregates and Homogeneous Floating-point
Aggregates, are supposed to apply to any type which is an aggregate of
all the same type (short vector for one, floating point for the other)
with 4 or fewer members.

In this implementation, I capture any *array* of 4 or fewer elements of
the appropriate type as an HVA or HFA, but I believe these structures
would also count and are not included in my implementation.

struct {
    float a;
    float b;
    float c;
};

struct {
    ShortVector a;
    ShortVector b;
};

This only matters if those sorts of structures are passed by value as
top level arguments to a function, ie they are not included in some
larger structure.

Also, rule B.6 talks about what to do with an "aignment adjusted type",
and I have no idea what that's supposed to be. Those may not be handled
correctly either.

Change-Id: I5a599a03d38075d7c0a06988c05e7fb5423c68c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23751
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

kern: Stop using a pseudo instruction to quiesce the ThreadContext.

The pseudo instruction implementation is very short, and so doing the
work it was doing directly doesn't really add much to the
implementation of the udelay events. By not calling the pseudo
instruction we also uncouple these unrelated mechanisms and don't,
for instance, cause pseudo instruction debug output every time udelay
executes.

Change-Id: I5c9b32509562487e53b2acfa1a3f6226d33d1cfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23748
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Delete the unused onKvmExitHypercall method.

The KVM_EXIT_HYPERCALL KVM exit is now unused, and so even if this
exit handler was plumbed to receive these exits, they would probably
never come.

Change-Id: Ic3ecc789102e761a6dbe80caaf57d61dd95f70a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23746
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Get rid of the now unused setSyscallReturn method.

Change-Id: I61741ab2eca4c77a2c8884e2b5c328479e2b3c90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23505
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Use the new returnInto method in cloneFunc.

This gets rid of the final use of setSyscallReturn.

Change-Id: I1108df0c5c72b5dec60128dced48ac0fd0356d24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23504
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a returnInto function to the SyscallDesc class.

This method lets system call implementations return values into
ThreadContexts other than the one they were called from. That's useful
for, for instance, clone() which creates new ThreadContexts.

By making it a virtual function in the SyscallDesc, we can delegate the
actual implementation to the SyscallDescABI subclass which knows the
ABI and how to use it to set the return value.

Change-Id: I61c6e60e4c2a8863c885cd818e4ff053fc3312ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23503
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the now unused getSyscallArg method.

Change-Id: I2f78420d8687da7530feb66784fe3e6d2357baf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Rework the SyscallDesc to use the dumpSimcall mechanism.

This greatly simplifies the doSyscall method, removes a use of
getSyscallArg, and will only print arguments the target syscall is
going to use.

Change-Id: Id8c9c995a2506468fd99fd865f2eb31c40db8b55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23461
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the no longer needed DefaultSyscallABI.

All ISAs now have their own ABI definitions.

Change-Id: I20484b024227658bed7093c232ebf7d64f29bdb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23458
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Convert the various flavors of pipe to GuestABI.

Change-Id: I44aaff417ea6a3ce311208b084fe4013bb93a48e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23457
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim,gpu: Make ioctl unconditionally take an address parameter.

The definition of ioctl is not actually variadic, it just doesn't
specify what the type of the pointer is that it takes as its third
argument. The man page says that that's because it predates void *
being valid C.

By passing this address around (even if it's unused), we avoid having
to extract system call arguments further down the call stack.

Change-Id: I62541237baafaec30bbe3df06b3284dd286a4051
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23456
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Clean up some constants used in some syscalls.

Having readable constants for these large numbers is good, but they
used incorrect style, were at global scope, and were only used in one
place.

This change centralizes them where they're used, fixes their style, and
rewrites the actual constants in a way that makes it clear what they're
values are.

Change-Id: Ib89c46fce133d4180296d384a61d51d1fe1f8d20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23455
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Convert ftruncate64 to GuestABI.

This function was specifying a particular width to getSyscallArg. The
new ISA specific ABIs now handle that automatically.

Change-Id: I141655d3bcb78f56c2a9278d140dfbc0d69e1ff4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23454
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Use a riscv specific GuestABI for riscv system calls.

Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23453
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Use a power specific GuestABI for power system calls.

Change-Id: I39cf64c025c284b63980f3c2e48fbd8b6c355d2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23452
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Use a mips specific GuestABI for mips system calls.

Change-Id: Ice9fb867b47e56bc00b171399a82b2892b16c9e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23451
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove the get*PseudoFunc handlers.

These were used in Alpha which has been removed.

Change-Id: I801ef71972b0c3d2aa04d682a3a94acfb27ac7ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23449
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use an ARM specific GuestABI for ARM system calls.

Change-Id: I2d0d0a563355f43ed791ba2f2a1894e303cca994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23448
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Use a SPARC specific GuestABI for system calls.

Change-Id: I41996cada5ccde7b265e5315829ac6690da8902f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23447
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Introduce a BitUnion for the CCR register.

This avoids opaque masks when accessing fields of this register.

Change-Id: If20d82c7c6401e6b1b35bb6d2c69542a56e2fb45
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23446
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Introduce constants for pseudo integer registers.

These are "integer" registers which are renamed, but which aren't
normally considered integer registers by the ISA. They had been indexed
by adding an opaque constant to the number of official integer
registers which obscured what they were, and was also fragile and
invited mistakes.

Change-Id: Idab8cf4d889682b98c7c81a00d9a92d8e3bb3a05
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23445
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Get rid of some commented out constants.

Change-Id: Ie2a223f5f969402a03b924ef767eddbcc14bf312
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23444
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Define a local ABI for system calls.

These ABIs (one 32 bit and one 64 bit) take advantage of the
GenericSyscallABI and X86Linux::SyscallABI partial ABIs set up earlier.

This removes x86's dependence on the getSyscallArg and setSyscallReturn
Process methods.

Change-Id: Ia07834cea1afa827d77e590af5397e2a1e0e2099
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23443
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: In X86 linux, system calls simply return their result in a register.

We can partially define an x86 linux system call ABI which handles the
return value. Argument gathering would be handled elsewhere.

Change-Id: Id2841dea39aa2ea3fc42e1a0fb70ff4e477b3671
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23442
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add GenericSyscallABI structs which can be used by the ISAs.

It's very common for system call arguments to be passed in a sequence
of registers, one argument per register. To avoid having that
implementation repeated over and over across the various ISAs and OSes,
these partial ABI implementations provide that mechanism they can just
pull in. They would need to define the sequence of registers to use,
and these would take care of the rest.

Unlike the temporary DefaultSyscallABI which defers to the Process
classes, these read registers from the ThreadContext directly.

Change-Id: Ic72eb8d784ecf4711b5eec76d958a87c70850fce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23441
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>