base: Fix unitialized storage

The bitunion is not being initialized on constructor to avoid
performance overhead, and that generated a maybe-unitialized
error when a sub-class was being copied before assigned in
serialize's parseParam() in some compilers.

This patch adds zero-initialization to the problematic variable
to appease the compiler.

Change-Id: I90fa6aa356b3e14ec25e3294b17ed10f429a9a38
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/15635
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

tests: Fix tests/main.py so it can be run from anywhere.

tests/main.py was trying to find paths relative to itself using the
string __name__ (which was __main__) when it should have been using the
string __file__ which holds the name of the file being executed.

Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738
Reviewed-on: https://gem5-review.googlesource.com/c/15675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Allow inserts in the begining of a packet queue

A packet queue keeps track of packets that are scheduled to be sent at
a specified time. Packets are sorted such that the packet with the
earliest scheduled time is at the front of the list (unless there are
other ordering requirements). Previouly, the implemented algorithm
didn't allow packets to be placed at the front of the queue resulting
in uneccessary delays. This change fixes the implementation of
schedSendTiming.

Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15556
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Determine if a packet queue forces ordering at construction

A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.

Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.

Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum

The smtCommitPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: I3625f2c08a1ae0c3b0dce7a641c6ae1ce3fd79a5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtROBPolicy a Param.ScopedEnum

The smtROBPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Ie104d055dbbc6e44997ae0c1470de714239be5a3
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtIQPolicy a Param.ScopedEnum

The smtIQPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Ieecf0a19427dd250b0d5ae3d531ab46a37326ae5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15398
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum

The smtLSQPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: I82041b88bd914c5dc660058d9e3998e3114e7c35
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15397
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum

The smtFetchPolicy is a parameter in the o3 cpu that can have 5
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Iafb4b4b27587541185ea912e5ed581bce09695f5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15396
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

python: Add support for scoped enums

At the moment gem5 has support for enum params that either generate a
unscoped within the Enums namespace or a struct encapsulated enum. The
Enums namespace is getting quite big and some params have the same
names which results in collisions. This change adds support for the
scoped enums.

Change-Id: I930e1cc3b814081627b653939e75d6c43956a334
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15395
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Make the ISA register types aliases for the global types.

The ISA specific types can thus be phased out.

Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60
Reviewed-on: https://gem5-review.googlesource.com/c/13623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Make the fp register types 64 bits.

This matches the other ISAs.

Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c
Reviewed-on: https://gem5-review.googlesource.com/c/13622
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Access Map Pattern Matching Prefetcher

Implementation of the Access Map Pattern Matching prefetcher
Based in the description of the following paper:
  Access map pattern matching for high performance data cache prefetch.
  Ishii, Y., Inaba, M., & Hiraki, K. (2011).
  Journal of Instruction-Level Parallelism, 13, 1-24.

Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c
Reviewed-on: https://gem5-review.googlesource.com/c/15096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Signature Path Prefetcher

Related paper:
  Lookahead Prefetching with Signature Path
  J Kim, PV Gratz, ALN Reddy
  The 2nd Data Prefetching Championship (DPC2), 2015

Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11
Reviewed-on: https://gem5-review.googlesource.com/c/14737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: allow prefetchers to emit page crossing references

QueuedPrefetcher takes the responsability to check for page
crossing references.

Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1
Reviewed-on: https://gem5-review.googlesource.com/c/14735
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: virtual address support for prefetchers

Prefetchers can be configured to operate with virtual or physical addreses.
The option can be configured through the "use_virtual_addresses" parameter
of the Prefetcher object.

Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa
Reviewed-on: https://gem5-review.googlesource.com/c/14416
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled

Trying to read MPIDR(_EL1) from EL1, should return the value of
VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility
function for reading MPIDR in order to match this behaviour for both
AArch32 and AArch64.

Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Added TLBI_ALL EL2 instruction

This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.

Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15616
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-riscv: Add interrupt handling

Implement the Interrupts SimObject for RISC-V. This basically just
handles setting and getting the values of the interrupt-pending and
interrupt-enable CSRs according to the privileged ISA reference chapter
3.1.14. Note that it does NOT implement the PLIC as defined in chapter
7, as that is used for handling external interrupts which are defined
based on peripherals that are available.

Change-Id: Ia1321430f870ff5a3950217266fde0511332485b
Reviewed-on: https://gem5-review.googlesource.com/c/14377
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix reset function and style

In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
 1. Privilege mode is set to M
 2. mstatus.mie <- 0; mstatus.mprv <- 0
 3. PC <- reset vector
 4. mcause <- reset cause (0 if there is no distinguishing causes)
 5. Everything else is undefined
Because of 5, everything else will be left alone

Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix usage of setArchVecElem

setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic

Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15655
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix usage of RegId constructor for VecElem

RegId() constructor requires three arguments in case of a VecElem
register: the class, the vector index and the element index inside the
vector, otherwise it panics.

Change-Id: Ic842df4dcddaffa83b211aa6e1dd1953cafa4951
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Stop using the FloatReg and FloatRegBits types.

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

config: De-nest the code in Port.splice().

The error checking in that function used an if/else structure where
one of the two branches would be the error condition which would cause
the function to exit. Because the function would exit if an error was
detected, there's no reason to have the non-error condition guarded in
the other half of the if.

This change de-nests the non-error cases to make the function simpler
and easier to read.

Change-Id: Idedf54e84a178fa5a2a47f96373374152e420cf3
Reviewed-on: https://gem5-review.googlesource.com/c/15516
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Fix an error message in Port.splice().

That error message referenced non-existent variables which were likely
renamed without updating the error message.

Change-Id: I6878802ef4b83e3fdf75a860d848b8c5e2e8d6c0
Reviewed-on: https://gem5-review.googlesource.com/c/15515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: added support of default Python installation on MacOS

Recent MacOS versions are distributed with python 2.7.
This version of python is sufficient to compile and run gem5.

This patch allows to use the default python instead of the version provided
by third-party tools (e.g., brew)

The default MacOS LLDB debugger is linked against the default python
installation, which conflicts with Python framework provided by third-party
package systems.

This patch removes the need of gem5 to have multiple python installations
on MacOS, if not explicitly installed.

Change-Id: I98f24804149cb2e04ca432c66d2f57e0296af7b2
Reviewed-on: https://gem5-review.googlesource.com/c/15475
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

sim-se, arch-arm: Add support for getdents64

Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15438
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm, sim-se: Add support for TLS in clone

Change-Id: I1f78dce05a48a2e3adfaf027cd38ab55507b9611
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15437
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm, sim-se: Fix incorrect SP handling in clone

The clone syscall is currently broken on aarch64 since the aarch64
code uses an incorrect SP register. Fix this by storing the new stack
pointer in SP_EL0 instead of R13.

Change-Id: Ie17990b4f359608e3b53e5bf625eca53769a6653
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15436
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Refactor clone to avoid most ifdefs

Some parts of clone are architecture dependent. In some cases, we are
able to use architecture-specific helper functions or register
aliases. However, there is still some architecture-specific that is
protected by ifdefs in the common clone implementation.

Move these architecture-specific bits to the architecture-specific OS
class instead to avoid these ifdefs and make the code a bit more
readable.

Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Correctly calculate next PC in clone

The clone syscall doesn't propagate all state in the PCState object
when calculating the return PC of a newly created process. Instead of
creating a new PCState object from the next PC address, copy the old
PC and advance it.

Change-Id: Ice53831920bcb5d198865169ed2cca8d06e37cfe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Use CONFIG_CLONE_BACKWARDS for Arm

Linxu on Arm users the CLONE_BACKWARDS argument order for the clone
syscall.

Change-Id: I48deb4f03140c9d4ef7a89e3e33813e76777f999
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15416
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm, sim-se: Wire up syscalls needed for pthreads

Change-Id: I8da5e3e0d7dc5d31ac82ed2045109d6d73cbf99d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15415
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 support

Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7
Reviewed-on: https://gem5-review.googlesource.com/c/14255
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Add a GICv3 model

Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Make it possible to convert strings to enums

The __to_number helper function defined in base/str.hh is used by
unserializing code. Its purpose is to convert a string into an
integral/floating point number.  Since enums underlying type can only be
an integer type, it makes sense to extend the helper function for enums
as well. In this way it will be possible to unserialize Enums and
containers of Enums without the need of casting.

Change-Id: I74069cc4c04ec8b5eb80939acea7ab18fb366dd4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15336
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Fix a function which was broken during style fixes.

Some brackets were misapplied while correcting the style of the TLM
header files.

Change-Id: I4e26d0316ca2545a5f26ad5fef0e986e42a1895b
Reviewed-on: https://gem5-review.googlesource.com/c/15455
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker

Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Reviewed-on: https://gem5-review.googlesource.com/c/14555
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Make input.txt a dependency for the tlm/endian_conv test.

This input file is consumed by the test and needs to be in the build
directory.

Change-Id: I3420dec9e41a1981c7d4e6df47f03273e378ab66
Reviewed-on: https://gem5-review.googlesource.com/c/15064
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Exclude some failing systemc TLM tests in working.filt.

These are known to fail and are undiagnosed, and so are not "working"
and shouldn't be in included when using the working.filt filter file.

Change-Id: I46e9f880bd4095085e4217ac6bec950cb2af9536
Reviewed-on: https://gem5-review.googlesource.com/c/15066
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Remove the TLM dependence on a non-standard method.

The sc_event_finder class in Accellera's implementation has a
non-standard report_error function that it uses internally. The TLM
headers were calling that function in their own event finder subclass.
This change replaces that call with what should be an equivalent bit of
code which is based on the report_error implementation.

Change-Id: Id57d26791df01403a77e70d5f4a00f650dc33599
Reviewed-on: https://gem5-review.googlesource.com/c/15063
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Stop using the sc_string_view type.

It doesn't seem to provide anything more that std::string, and comes
with extra dependencies/baggage.

Change-Id: I2c599bcc93fa4a944ff249410d24e8f8be981afe
Reviewed-on: https://gem5-review.googlesource.com/c/15298
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Replace sc_core::sc_type_index with std::type_index.

The former is either the same as the later, or a custom wrapper if
C++11 isn't supported. Since we generally expect C++11 support, we can
skip the indirection.

Change-Id: I9a45e3854bb7cc56d094e3fe2773fe4b5c94403b
Reviewed-on: https://gem5-review.googlesource.com/c/15297
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Stop using the Accellera specific "none" global event object.

That event being available is nonstandard. Define our own static event
for use in that case.

Change-Id: I5e8892bd83cc1984d63949ef3e249755dca0c702
Reviewed-on: https://gem5-review.googlesource.com/c/15296
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Rename tlm_core header files to have a .hh extentension.

This makes those files more consistent with other headers in gem5. The
top level headers (tlm and tlm.h) and the tlm_utils headers were left
alone since the user might reasonably expect those to have a well known
name. The tlm_core headers by comparison are an implementation detail,
and users shouldn't include them directly by name.

Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06
Reviewed-on: https://gem5-review.googlesource.com/c/15067
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Add a dummy argv[0] when running the tests.

One TLM test will complain if argc isn't 1 or 2, assuming that that
must mean that argc > 2. If it's 0 then the test will also complain and
fail. We therefore need to pass it at least a dummy value in argv/argc.

Change-Id: I5c64856f46d1459d7238e88ad8ba06933c7c38b8
Reviewed-on: https://gem5-review.googlesource.com/c/15065
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Stop using the non-standard sc_time % in TLM.

The TLM headers were using the non-standard % operator on sc_time.
This change replaces that with % applied to the result of
sc_time::value().

Change-Id: Ic381eb1ada2c994d04e65896db178f58446944ae
Reviewed-on: https://gem5-review.googlesource.com/c/15062
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Add an elaboration_done method to sc_simcontext.

The TLM headers rely on this non-standard function.

Change-Id: Iaedec35f1f363dcf3e1fcdb58a74eb2cdc05ddc0
Reviewed-on: https://gem5-review.googlesource.com/c/15061
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Include cstring in the tlm header file.

A lot of TLM implementation assumes the string functions (memcpy,
memset, etc) are available, but don't include cstring. Lets do that
for them to avoid having to fix up a lot of places.

Change-Id: I1f26d3a227fe2cefc2613e24cbb0333216e46ee9
Reviewed-on: https://gem5-review.googlesource.com/c/15060
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Remove redundant tlm_ prefixes from file names.

We already know those files belong to tlm because of the directory
they're in. Removing the prefix makes the paths of the headers less
enormously long.

Change-Id: I869e58fae904162f353bb31f4c0919fba08dffa6
Reviewed-on: https://gem5-review.googlesource.com/c/15059
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Replace some calls to some Accellera specific functions in TLM.

The TLM event finder class was calling implementation specific
functions from the Accellera version of systemc. This change replaces those
calls with equivalent calls which match the gem5 implementation.

Change-Id: I0ecdb0a4bf09aeb1aad823a01105fbd88edb4601
Reviewed-on: https://gem5-review.googlesource.com/c/15075
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Rename tlm .cpp files to .cc and add SConscripts.

Change-Id: Ia30192b441dd34bc7165c6335386c88c0015fdf6
Reviewed-on: https://gem5-review.googlesource.com/c/15295
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Fix style issues in the TLM header files.

Change-Id: Id12ffb9b56b3887afcf30120f81ce5eb75a5987b
Reviewed-on: https://gem5-review.googlesource.com/c/15057
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Also look for tests in the tlm test directory.

Both basic systemc and tlm tests were present, but scons only looked
in the systemc directory when populating the test json. This change
makes it also look in the tlm directory so that those tests can be run.

Change-Id: Id65b744664350f6105fb3a4f28cbc7ab91d8c82e
Reviewed-on: https://gem5-review.googlesource.com/c/15056
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

systemc: Initial import of TLM headers from Accellera.

These headers will need to be cleaned up and have some Accellera
specific quirks ironed out of them, but I'll do that in a later change
to make it clear what those changes are.

Change-Id: Ia4e08633ab552b4c616c66c9b7e2bbd78ebfe7b9
Reviewed-on: https://gem5-review.googlesource.com/c/15055
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

system-arm: Add device tree for new VExpress GEM5_V2 platform

Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034
Reviewed-on: https://gem5-review.googlesource.com/c/14275
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Add aarch64 bootloader support for GICv3

Change-Id: If75262709868cc59d320f60273a32397339f1dd5
Signed-off-by: Jairo Balart <jairo.balart@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13435
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Disable partial linking on Mac OS

Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial
linked objects do not expose symbols that are marked with the hidden
visibility and consequently building gem5 on Mac OS fails. As a
workaround, we disable partial linking, however, we may want to
revisit in the future.

Change-Id: I0a26dae082bf723c2bd49d90e4497e44ecab9c41
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15235
Reviewed-by: Andrea Mondelli <andrea.mondelli@ucf.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

dev, arm: Warn on PL011 DMA disable

The PL011 spec specifies a DMACR register at offset 0x48, which isn't
implemented in the model. Currently any attempt to access the register
results in a panic.

This change swaps the panic for a warning only when software writes into
DMACR to disable DMA, keeping the panic otherwise.

Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15279
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Added VGIC GICV_IIDR response

Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15278
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Implement GIC-400 model from GicV2

Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.

Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Move VGic from Realview.py to Gic.py

Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15276
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Added unimplemented GICv2 GICC_DIR

This GICC CPU register is not implemented but just gives a warning.

Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15275
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Stop using unions to store FP registers.

These are now accessed only as integer values.

Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb
Reviewed-on: https://gem5-review.googlesource.com/c/14458
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, cpu: Remove float type accessors.

Use the binary accessors instead.

Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Add Crypto in SE mode

This patch is also enabling AArch32 crypto instructions by setting the
ID_ISAR5 register accordingly.

Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15155
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Allow specific functions to shadow the base class method

sc_in::bind and sc_core::sc_object::print shadow their respective base
class method. This change adds the necessary declarations to inform
the compiler that this is intentional.

Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15135
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Disable systemc on Mac OS

LLVM on Mac OS up until version 10.0.0 doesn't seem to support the
attribute for weak linking and fails to compile. Additionally, even
the basic example tests fail. Therefore, this change disables systemc
by default on Mac OS until we address these issues.

Change-Id: Iaa6360ec61317e01f4e645af8b509961b3144282
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14818
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Make the ISA parser always use binary floating point accessors.

Any operands which use read_code or write_code would need to start
using the floatToBits and bitsToFloat, but only ARM is using that
mechanism, and not on float operands.

Also I notice that the "predicate" mechanism for operands ignores the
read_code and write_code mechanism, and using both will not work
correctly. This change makes no attempt to fix that problem, but
shouldn't contribute to it either.

Change-Id: I0e3a7f78ed28f40cb66958ef12c32e862950fde0
Reviewed-on: https://gem5-review.googlesource.com/c/14456
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Ensure resets and edges are notified when signaling a change.

Boolean sc_buffers (either pure bool or sc_dt::sc_logic) should signal
positive and negative edges and resets even when their value doesn't
change, unlike sc_signals. The spec doesn't actually say that and just
mentions the value changed event, but it may have been implied that the
other types of events also happen, they just made special mention of
the value change event.

This change moves some code around a bit so that when _signalChange()
is called, if the underlying type is a boolean signal, it will
automatically notify the appropriate edge event and signal any reset.
Putting the functionality in _signalChange instead of delegating it to
the sc_buffer lets us have a single template for sc_buffer and makes
the base class template specialization handle whether the edge events
exist, and if so which should be notified.

Change-Id: Ic4ca86afc3fde6a9df5c15a0a7386e24ac89a9e2
Reviewed-on: https://gem5-review.googlesource.com/c/14916
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Fixed typos in parameter/stats descriptions

Change-Id: I7b3274a3e37128da35f497da150af08343e97ee6
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14795
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Added parameters to enable/disable features in LTAGE

They are for the following features in the LTAGE loop predictor:
 - Hashing for calculating the loop table entry
 - Add direction information
 - Add speculative iteration number information

Change-Id: I395f4526163ee0d0229d1e87cde2bb046f1dd43a
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14597
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Louis Delhez <ldelhez@ucla.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor

Change 9af1214 added a new ctor to the LSQUnit, however
there is a typo/bug because it sizes the SQEntries
member variable to lqEntries + 1, as opposed to
sqEntries + 1. This change corrects the issue by
using sqEntries.

Change-Id: I19dfaa5c0e335bd7b84343a92034147d7c5d914e
Reviewed-on: https://gem5-review.googlesource.com/c/15015
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

systemc: Update test output for longer lived processes.

In the systemc spec, process handles can be invalidated if they have no
children and are terminated. The implementation is not required to do
so however, and for the sake of simplicity gem5 currently does not. To
quote:

"When the underlying process instance terminates, if the process
instance has no surviving children, an implementation may choose to
invalidate any associated process handles, but it is not obliged to do
so."

Two tests have reference output which is affected by this (legal)
difference in behavior. In one case, the test creates new processes
which reuse the names of processes that have been terminated. Since
gem5 doesn't invalidate the old processes, a standard mechanism is
activated which renames the processes to something which is unique.

The other test has this same problem, and also prints the hierarchy
of processes several times during the test. In that hierarchy, the
terminated tests with no live children are still present, where in the
old reference output they've been removed.

This change updates the reference output to match gem5's behavior.

Change-Id: I363448de10080bdce01a4df92f991c67b31a2401
Reviewed-on: https://gem5-review.googlesource.com/c/14919
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Update the ordering in the reference output for some tests.

There are a number of cases where systemc leaves the decision of what
order things happen up to the kernel, and any ordering is legal and
conformant with the spec as long as it's repeatable. The reference
outputs reflect a particular choice of ordering which is implementation
specific, and while considerable effort has been made to make the gem5
ordering match the Accellera ordering, at a certain point that's no
longer practical or desirable.

This change manually updates the reference output for the tests that
haven't been excluded for other reasons which have this sort of ordering
problem. They have been individually examined, and as best as I can
tell changing the output this way does not mask any underlying error.

One or two real problems were discovered in addition to the ordering
issues, and those were fixed in earlier changes.

Change-Id: I915269998de3f33d5ab5d1fd754a830fd620184d
Reviewed-on: https://gem5-review.googlesource.com/c/14918
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Ignore process control functions on terminated processes.

These functions can descend to the children of a terminated process,
but should have no effect on that process itself.

Change-Id: I6e4bdec8c492dd03d05bc1397aa080e8a51397c1
Reviewed-on: https://gem5-review.googlesource.com/c/14917
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Update signals before initing processes.

We were supposed to do one update phase before adding all processes
which didn't have dont_initialize() called to the run queue. We were
doing that in the opposite order.

Change-Id: I6dd4108040d455dc78029da029a2eb5e7af819cb
Reviewed-on: https://gem5-review.googlesource.com/c/14915
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

base, systemc: Fix clang compilation

This patch is fixing the following issues:

- base: typename should be used only for types
- systemc: 'GCC_VERSION' is not defined for clang

Change-Id: I27c94445d65691a08a0a14a0ffe6b6942f6c455f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Compile tracePacket only when TRACING_ON is defined

If TRACING_ON is not defined (e.g. when building gem5.fast), clang
compilations will fail reporting an unused function.

Change-Id: I959dba6e9fcf74b951e16365077939ae4d4ef924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14975
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Workaround for setWhenReady assertion

Change 174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that
is not satisfiable with current implementation, breaking some
regression tests.

Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

ext: Remove unused bankwiseMode variable

Apple LLVM version 10.0.0 (clang-1000.11.45.2) complains about
unused members variables

Change-Id: If1f2210c09e80b632cb3688aaa7df0594f9e49c9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13228
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Ported circlebuf to CircularQueue

Ported the existing circlebuf on top of the CircularQueue to condense
shared functionality and minimise code/functionality replication.

Additional contributors: Gabor Dozsa.

Change-Id: Ib4e67c638f0fb66b54cef77007a03439218bda7f
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13128
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

base: Iterable CircularQueue implementation

The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.

Additional contributors: Gabor Dozsa.

Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13127
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

ext: Build googlemock with googletest

googlemock needs to be built together with googletest. This patch
is enabling it by doing the following things

* Moving googletest and googlemock under the same top level directory,
  so that we have a single SConscript for building them.
  This also matches googletest directory structure:
  googletest
      |_googletest
      |_googlemock

* Adding a shared SConscript which is building gmock and gtest as libgtest
* Removing googletest/SConscript

Change-Id: I88accbdd2e80fb47efaa17819233371fbad6acaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14696
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

ext: Import googlemock, release version 1.8.0

gtest 1.8.0 is already part of gem5; this patch adds a matching gmock
so that it is possible to create Mocks in gem5 unit tests.

Please note: the commit is just importing the source code as it is
without adding any SConscript; it is hence unbuildable at the moment.
Next commits will integrate the mocking framework into the gem5
build system

Change-Id: Iaf05ad91b1964aac7ea37085f839027a8d34ba3e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14695
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc

Change a66d12c guards the selection of getdents()
in x86's process.cc file with SYS_getdents, however
process.cc does not include the right header for
SYS_getdents, which leads to x86 choosing the
unimplemented call. This change adds sys/syscall.h to
address the problem.

This change also adds sys/syscall.hh to syscall_emu.cc,
which only includes syscall.hh and may not be supported on
all systems.

Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e
Reviewed-on: https://gem5-review.googlesource.com/c/14775
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

mem-cache: Remove writebacks parameter from serviceMSHRTargets

Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the
writebacks parameter, but it was never used.

Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14896
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add getter and setter to CacheBlk::whenReady

Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.

As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().

Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix fiber compilation issue for Mac OS

Mac OS has deprecated the use of ucontext and at the moment we are
using a workaround to enable it. A side-effect is that the code is
marked as _POSIX_C_SOURCE and consequently <sys/mman.h> requires the
code to be also marked as _DARWIN_C_SOURCE to include the definition
of MAP_ANONYMOUS.

Change-Id: I65550d11a0a21cd36d832a7de6320e7e3f332a9d
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14817
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base, sim: Add missing destructors

Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.

Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Add type alias for raw pointer in RefCountingPtr

Change-Id: Ied2204566a8fc5c34fb4702301051b8e5ab84ffe
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Optimize sector valid and secure check

Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.

Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Change raw pointers to STL Containers

This patch changes two members from being raw pointers to being STL
containers. The reason behind, other than cleanlyness and arguable OO
best practices is that containers have more intronspections capabilities
than naked pointers do, as the size is known.

Using STL containers adds little overhead and eases the automation of
process during debugging (gdb).

Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: correctly set floats from GDB on aarch64

aarch64 floating point registers are now stored as vector type, but this
was not updated in the stub.

Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42
Reviewed-on: https://gem5-review.googlesource.com/c/14498
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

base: increase the GDB buffer size dynamically

The size was not large enough for the 'G' packet on aarch64, which the
client sends to set registers.

This would lead to the stub not to be able to find the end of the input
packet and keep waiting forever.

Change-Id: Icb149f15a6c769371ebcb6ec5fbebc6170c31fc6
Reviewed-on: https://gem5-review.googlesource.com/c/14497
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: only change the pc address when GDB registers are set

The entire pcState was being reset, which made the simulation incorrectly
switch to aarch32 from aarch64.

Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5
Reviewed-on: https://gem5-review.googlesource.com/c/14496
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: fix the aarch64 GDB stub

The main change is to remove vector registers from the GDB stub.

Those registers were intended for SVE, which is a new architecture feature
and not yet treated by default on the GDB present in Ubuntu 18.04, and
possibly not even on GDB master.

As a result, aarch64 GDB stub connections would fail with:

Remote 'g' packet reply is too long

The correct way to support those registers is to send XML GDB target
description files to the client. This feature is not yet available for
any architecture, and should be implemented in future patches.

Other smaller fixes are:

* cpsr is uint32_t in aarch64 as well as arm
* use M5_ATTR_PACKED on the register structs since they are being cast and
  sent as byte arrays

Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7
Reviewed-on: https://gem5-review.googlesource.com/c/14495
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>