yosys.git
5 years agoAdd signed opt_expr tests
Eddie Hung [Tue, 6 Aug 2019 22:40:30 +0000 (15:40 -0700)]
Add signed opt_expr tests

5 years agoAdd signed test
Eddie Hung [Tue, 6 Aug 2019 22:38:43 +0000 (15:38 -0700)]
Add signed test

5 years agoMove LSB-trimming functionality from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:25:50 +0000 (15:25 -0700)]
Move LSB-trimming functionality from wreduce to opt_expr

5 years agoAdd SigSpec::extract_end() convenience function
Eddie Hung [Tue, 6 Aug 2019 22:25:11 +0000 (15:25 -0700)]
Add SigSpec::extract_end() convenience function

5 years agoRestore original SigSpec::extract()
Eddie Hung [Tue, 6 Aug 2019 22:24:55 +0000 (15:24 -0700)]
Restore original SigSpec::extract()

5 years agoMove LSB tests from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:24:49 +0000 (15:24 -0700)]
Move LSB tests from wreduce to opt_expr

5 years agoMerge remote-tracking branch 'origin/master' into eddie/wreduce_add
Eddie Hung [Tue, 6 Aug 2019 21:50:00 +0000 (14:50 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add

5 years agoMerge pull request #1232 from YosysHQ/dave/write_gzip
David Shah [Tue, 6 Aug 2019 18:05:35 +0000 (19:05 +0100)]
Merge pull request #1232 from YosysHQ/dave/write_gzip

Add support for writing gzip-compressed files

5 years agoAdd test for writing gzip-compressed files
David Shah [Wed, 31 Jul 2019 12:58:27 +0000 (13:58 +0100)]
Add test for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd support for writing gzip-compressed files
David Shah [Mon, 29 Jul 2019 08:28:31 +0000 (09:28 +0100)]
Add support for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1251 from YosysHQ/clifford/nmux
Clifford Wolf [Tue, 6 Aug 2019 13:18:18 +0000 (15:18 +0200)]
Merge pull request #1251 from YosysHQ/clifford/nmux

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

5 years agoAdd $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Clifford Wolf [Tue, 6 Aug 2019 02:47:55 +0000 (04:47 +0200)]
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1242 from jfng/fix-proc_prune-partial
whitequark [Sat, 3 Aug 2019 07:08:41 +0000 (07:08 +0000)]
Merge pull request #1242 from jfng/fix-proc_prune-partial

proc_prune: Promote partially redundant assignments.

5 years agoMerge pull request #1238 from mmicko/vsbuild_fix
Clifford Wolf [Fri, 2 Aug 2019 15:07:39 +0000 (17:07 +0200)]
Merge pull request #1238 from mmicko/vsbuild_fix

Visual Studio build fix

5 years agoMerge pull request #1239 from mmicko/mingw_fix
Clifford Wolf [Fri, 2 Aug 2019 14:37:57 +0000 (16:37 +0200)]
Merge pull request #1239 from mmicko/mingw_fix

Fix formatting for msys2 mingw build

5 years agoMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
Eddie Hung [Thu, 1 Aug 2019 16:38:55 +0000 (09:38 -0700)]
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map

xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER

5 years agoFix linking issue for new mxe and pthread
Miodrag Milanovic [Wed, 31 Jul 2019 16:02:27 +0000 (18:02 +0200)]
Fix linking issue for new mxe and pthread

5 years agoFix yosys linking for mxe
Miodrag Milanovic [Wed, 31 Jul 2019 15:31:07 +0000 (17:31 +0200)]
Fix yosys linking for mxe

5 years agoNew mxe hacks needed to support 2ca237e
Miodrag Milanovic [Wed, 31 Jul 2019 15:30:48 +0000 (17:30 +0200)]
New mxe hacks needed to support 2ca237e

5 years agoFix formatting for msys2 mingw build using GetSize
Miodrag Milanovic [Wed, 31 Jul 2019 09:49:48 +0000 (11:49 +0200)]
Fix formatting for msys2 mingw build using GetSize

5 years agoproc_prune: Promote partially redundant assignments.
Jean-François Nguyen [Wed, 31 Jul 2019 12:26:09 +0000 (14:26 +0200)]
proc_prune: Promote partially redundant assignments.

5 years agoMerge pull request #1233 from YosysHQ/clifford/defer
Clifford Wolf [Wed, 31 Jul 2019 11:30:52 +0000 (13:30 +0200)]
Merge pull request #1233 from YosysHQ/clifford/defer

Call "read_verilog" with -defer from "read"

5 years agoVisual Studio build fix
Miodrag Milanovic [Wed, 31 Jul 2019 07:10:24 +0000 (09:10 +0200)]
Visual Studio build fix

5 years agoRST -> RSTBRST for RAMB8BWER
Eddie Hung [Mon, 29 Jul 2019 23:05:44 +0000 (16:05 -0700)]
RST -> RSTBRST for RAMB8BWER

5 years agoMerge pull request #1228 from YosysHQ/dave/yy_buf_size
Eddie Hung [Mon, 29 Jul 2019 16:16:09 +0000 (09:16 -0700)]
Merge pull request #1228 from YosysHQ/dave/yy_buf_size

verilog_lexer: Increase YY_BUF_SIZE to 65536

5 years agoMerge pull request #1234 from mmicko/fix_gzip_no_exist
David Shah [Mon, 29 Jul 2019 14:50:20 +0000 (15:50 +0100)]
Merge pull request #1234 from mmicko/fix_gzip_no_exist

Fix case when file does not exist

5 years agoFix case when file does not exist
Miodrag Milanovic [Mon, 29 Jul 2019 10:29:13 +0000 (12:29 +0200)]
Fix case when file does not exist

5 years agoUpdate README to use "read" instead of "read_verilog"
Clifford Wolf [Mon, 29 Jul 2019 08:40:30 +0000 (10:40 +0200)]
Update README to use "read" instead of "read_verilog"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCall "read_verilog" with -defer from "read"
Clifford Wolf [Mon, 29 Jul 2019 08:29:36 +0000 (10:29 +0200)]
Call "read_verilog" with -defer from "read"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1226 from YosysHQ/dave/gzip
David Shah [Sat, 27 Jul 2019 06:40:38 +0000 (07:40 +0100)]
Merge pull request #1226 from YosysHQ/dave/gzip

Add support for gzip'd input files

5 years agoUpdate CHANGELOG
David Shah [Fri, 26 Jul 2019 14:53:21 +0000 (15:53 +0100)]
Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
5 years agoverilog_lexer: Increase YY_BUF_SIZE to 65536
David Shah [Fri, 26 Jul 2019 12:35:39 +0000 (13:35 +0100)]
verilog_lexer: Increase YY_BUF_SIZE to 65536

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix frontend auto-detection for gzipped input
David Shah [Fri, 26 Jul 2019 09:29:05 +0000 (10:29 +0100)]
Fix frontend auto-detection for gzipped input

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd support for reading gzip'd input files
David Shah [Fri, 26 Jul 2019 09:23:58 +0000 (10:23 +0100)]
Add support for reading gzip'd input files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Thu, 25 Jul 2019 17:49:26 +0000 (10:49 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoBump abc to fix &mfs bug
Eddie Hung [Thu, 25 Jul 2019 17:44:20 +0000 (10:44 -0700)]
Bump abc to fix &mfs bug

5 years agoMerge branch 'ZirconiumX-synth_intel_m9k'
Clifford Wolf [Thu, 25 Jul 2019 15:23:48 +0000 (17:23 +0200)]
Merge branch 'ZirconiumX-synth_intel_m9k'

5 years agoMerge pull request #1218 from ZirconiumX/synth_intel_iopads
Clifford Wolf [Thu, 25 Jul 2019 15:19:54 +0000 (17:19 +0200)]
Merge pull request #1218 from ZirconiumX/synth_intel_iopads

intel: Make -noiopads the default

5 years agoMerge pull request #1219 from jakobwenzel/objIterator
Clifford Wolf [Thu, 25 Jul 2019 15:19:11 +0000 (17:19 +0200)]
Merge pull request #1219 from jakobwenzel/objIterator

made ObjectIterator comply with Iterator Interface

5 years agoMerge pull request #1224 from YosysHQ/xilinx_fix_ff
Eddie Hung [Thu, 25 Jul 2019 13:44:17 +0000 (06:44 -0700)]
Merge pull request #1224 from YosysHQ/xilinx_fix_ff

xilinx: Fix missing cell name underscore in cells_map.v

5 years agoreplaced std::iterator with using statements
Jakob Wenzel [Thu, 25 Jul 2019 07:51:09 +0000 (09:51 +0200)]
replaced std::iterator with using statements

5 years agoxilinx: Fix missing cell name underscore in cells_map.v
David Shah [Thu, 25 Jul 2019 07:19:07 +0000 (08:19 +0100)]
xilinx: Fix missing cell name underscore in cells_map.v

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1222 from koriakin/s6-example
Eddie Hung [Wed, 24 Jul 2019 17:51:03 +0000 (10:51 -0700)]
Merge pull request #1222 from koriakin/s6-example

Add a simple example for Spartan 6

5 years agoAdd a simple example for Spartan 6
Marcin Kościelnicki [Wed, 24 Jul 2019 16:41:39 +0000 (18:41 +0200)]
Add a simple example for Spartan 6

5 years agomade ObjectIterator extend std::iterator
Jakob Wenzel [Wed, 24 Jul 2019 11:33:07 +0000 (13:33 +0200)]
made ObjectIterator extend std::iterator

this makes it possible to use std algorithms on them

5 years agointel: Make -noiopads the default
Dan Ravensloft [Wed, 24 Jul 2019 09:38:15 +0000 (10:38 +0100)]
intel: Make -noiopads the default

5 years agointel: Map M9K BRAM only on families that have it
Dan Ravensloft [Mon, 22 Jul 2019 11:15:22 +0000 (12:15 +0100)]
intel: Map M9K BRAM only on families that have it

This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.

5 years agoMerge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
Eddie Hung [Tue, 23 Jul 2019 16:56:58 +0000 (09:56 -0700)]
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp

ice40: Fix SB_MAC16 sim model for signed modes

5 years agoMerge pull request #1214 from jakobwenzel/astmod_clone
Eddie Hung [Mon, 22 Jul 2019 14:42:53 +0000 (07:42 -0700)]
Merge pull request #1214 from jakobwenzel/astmod_clone

initialize noblackbox and nowb in AstModule::clone

5 years agoinitialize noblackbox and nowb in AstModule::clone
Jakob Wenzel [Mon, 22 Jul 2019 08:37:40 +0000 (10:37 +0200)]
initialize noblackbox and nowb in AstModule::clone

5 years agoAdd "stat -tech cmos"
Clifford Wolf [Sat, 20 Jul 2019 13:06:28 +0000 (15:06 +0200)]
Add "stat -tech cmos"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoTry and fix again
Eddie Hung [Fri, 19 Jul 2019 21:40:57 +0000 (14:40 -0700)]
Try and fix again

5 years agoAdd another test
Eddie Hung [Fri, 19 Jul 2019 21:02:46 +0000 (14:02 -0700)]
Add another test

5 years agoDo not access beyond bounds
Eddie Hung [Fri, 19 Jul 2019 20:58:50 +0000 (13:58 -0700)]
Do not access beyond bounds

5 years agoAdd an SigSpec::at(offset, defval) convenience method
Eddie Hung [Fri, 19 Jul 2019 20:54:57 +0000 (13:54 -0700)]
Add an SigSpec::at(offset, defval) convenience method

5 years agoWrap A and B in sigmap
Eddie Hung [Fri, 19 Jul 2019 20:23:07 +0000 (13:23 -0700)]
Wrap A and B in sigmap

5 years agoRemove "top" from message
Eddie Hung [Fri, 19 Jul 2019 20:20:45 +0000 (13:20 -0700)]
Remove "top" from message

5 years agoAlso optimise MSB of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:48 +0000 (13:11 -0700)]
Also optimise MSB of $sub

5 years agoAdd one more test with trimming Y_WIDTH of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:30 +0000 (13:11 -0700)]
Add one more test with trimming Y_WIDTH of $sub

5 years agoBe more explicit
Eddie Hung [Fri, 19 Jul 2019 19:53:18 +0000 (12:53 -0700)]
Be more explicit

5 years agowreduce for $sub
Eddie Hung [Fri, 19 Jul 2019 19:50:21 +0000 (12:50 -0700)]
wreduce for $sub

5 years agoAdd tests for sub too
Eddie Hung [Fri, 19 Jul 2019 19:50:11 +0000 (12:50 -0700)]
Add tests for sub too

5 years agoAdd test
Eddie Hung [Fri, 19 Jul 2019 19:43:02 +0000 (12:43 -0700)]
Add test

5 years agoSigSpec::extract to take negative lengths
Eddie Hung [Fri, 19 Jul 2019 19:34:04 +0000 (12:34 -0700)]
SigSpec::extract to take negative lengths

5 years agoice40: Fix test_dsp_model.sh
David Shah [Fri, 19 Jul 2019 16:33:57 +0000 (17:33 +0100)]
ice40: Fix test_dsp_model.sh

Signed-off-by: David Shah <dave@ds0.me>
5 years agoice40/cells_sim.v: Fix sign of J and K partial products
David Shah [Fri, 19 Jul 2019 16:33:41 +0000 (17:33 +0100)]
ice40/cells_sim.v: Fix sign of J and K partial products

Signed-off-by: David Shah <dave@ds0.me>
5 years agoice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
David Shah [Fri, 19 Jul 2019 16:13:34 +0000 (17:13 +0100)]
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd tests for all combinations of A and B signedness for comb mul
Eddie Hung [Fri, 19 Jul 2019 15:52:49 +0000 (08:52 -0700)]
Add tests for all combinations of A and B signedness for comb mul

5 years agoDon't copy ref if exists already
Eddie Hung [Fri, 19 Jul 2019 15:45:35 +0000 (08:45 -0700)]
Don't copy ref if exists already

5 years agoMerge pull request #1208 from ZirconiumX/intel_cleanups
David Shah [Thu, 18 Jul 2019 18:04:28 +0000 (19:04 +0100)]
Merge pull request #1208 from ZirconiumX/intel_cleanups

Assorted synth_intel cleanups from @bwidawsk

5 years agosynth_intel: Use stringf
Dan Ravensloft [Thu, 18 Jul 2019 17:41:34 +0000 (18:41 +0100)]
synth_intel: Use stringf

5 years agoMerge pull request #1207 from ZirconiumX/intel_new_pass_names
David Shah [Thu, 18 Jul 2019 16:34:55 +0000 (17:34 +0100)]
Merge pull request #1207 from ZirconiumX/intel_new_pass_names

synth_intel: rename for consistency with #1184

5 years agosynth_intel: s/not family/no family/
Dan Ravensloft [Thu, 18 Jul 2019 16:28:21 +0000 (17:28 +0100)]
synth_intel: s/not family/no family/

5 years agosynth_intel: revert change to run_max10
Dan Ravensloft [Thu, 18 Jul 2019 16:08:52 +0000 (17:08 +0100)]
synth_intel: revert change to run_max10

5 years agointel_synth: Fix help message
Ben Widawsky [Mon, 8 Jul 2019 19:41:22 +0000 (12:41 -0700)]
intel_synth: Fix help message

cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Small code cleanup to remove if ladder
Ben Widawsky [Mon, 8 Jul 2019 19:37:24 +0000 (12:37 -0700)]
intel_synth: Small code cleanup to remove if ladder

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Make family explicit and match
Ben Widawsky [Mon, 8 Jul 2019 19:24:24 +0000 (12:24 -0700)]
intel_synth: Make family explicit and match

The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Minor code cleanups
Ben Widawsky [Mon, 8 Jul 2019 19:03:00 +0000 (12:03 -0700)]
intel_synth: Minor code cleanups

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agosynth_intel: rename for consistency with #1184
Dan Ravensloft [Thu, 18 Jul 2019 15:46:21 +0000 (16:46 +0100)]
synth_intel: rename for consistency with #1184

Also fix a typo in the help message.

5 years agoMerge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf [Thu, 18 Jul 2019 13:34:28 +0000 (15:34 +0200)]
Merge pull request #1184 from whitequark/synth-better-labels

synth_{ice40,ecp5}: more sensible pass label naming

5 years agoMerge pull request #1203 from whitequark/write_verilog-zero-width-values
Clifford Wolf [Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)]
Merge pull request #1203 from whitequark/write_verilog-zero-width-values

write_verilog: dump zero width constants correctly

5 years agoRemove old $pmux_safe code from write_verilog
Clifford Wolf [Wed, 17 Jul 2019 09:49:04 +0000 (11:49 +0200)]
Remove old $pmux_safe code from write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1204 from smunaut/fix_1187
David Shah [Wed, 17 Jul 2019 06:55:26 +0000 (07:55 +0100)]
Merge pull request #1204 from smunaut/fix_1187

ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map

5 years agoice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut [Tue, 16 Jul 2019 21:57:15 +0000 (23:57 +0200)]
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map

The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agowrite_verilog: dump zero width constants correctly.
whitequark [Tue, 16 Jul 2019 20:57:05 +0000 (20:57 +0000)]
write_verilog: dump zero width constants correctly.

Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).

5 years agoMerge pull request #1202 from YosysHQ/cmp2lut_lut6
Eddie Hung [Tue, 16 Jul 2019 20:52:43 +0000 (13:52 -0700)]
Merge pull request #1202 from YosysHQ/cmp2lut_lut6

cmp2lut transformation to support >32 bit LUT masks

5 years agosynth_ecp5: rename dram to lutram everywhere.
whitequark [Tue, 16 Jul 2019 20:44:55 +0000 (20:44 +0000)]
synth_ecp5: rename dram to lutram everywhere.

5 years agosynth_{ice40,ecp5}: more sensible pass label naming.
whitequark [Thu, 11 Jul 2019 10:56:59 +0000 (10:56 +0000)]
synth_{ice40,ecp5}: more sensible pass label naming.

5 years agogen_lut to return correctly sized LUT mask
Eddie Hung [Tue, 16 Jul 2019 19:45:29 +0000 (12:45 -0700)]
gen_lut to return correctly sized LUT mask

5 years agoForgot to commit
Eddie Hung [Tue, 16 Jul 2019 19:44:26 +0000 (12:44 -0700)]
Forgot to commit

5 years agoAdd tests for cmp2lut on LUT6
Eddie Hung [Tue, 16 Jul 2019 19:11:59 +0000 (12:11 -0700)]
Add tests for cmp2lut on LUT6

5 years agoMerge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
Eddie Hung [Tue, 16 Jul 2019 15:53:47 +0000 (08:53 -0700)]
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters

abc9: push inverters driving box inputs (comb outputs) through $lut soft logic

5 years agoMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung [Tue, 16 Jul 2019 15:52:14 +0000 (08:52 -0700)]
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix

abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box

5 years agoMerge pull request #1200 from mmicko/fix_typo_liberty_cc
Clifford Wolf [Tue, 16 Jul 2019 13:27:25 +0000 (15:27 +0200)]
Merge pull request #1200 from mmicko/fix_typo_liberty_cc

Fix typo, double "of"

5 years agoMerge pull request #1199 from mmicko/extract_fa_fix
Clifford Wolf [Tue, 16 Jul 2019 13:27:09 +0000 (15:27 +0200)]
Merge pull request #1199 from mmicko/extract_fa_fix

Fix check logic in extract_fa

5 years agoFix typo, double "of"
Miodrag Milanovic [Tue, 16 Jul 2019 09:03:30 +0000 (11:03 +0200)]
Fix typo, double "of"

5 years agoFix check logic in extract_fa
Miodrag Milanovic [Tue, 16 Jul 2019 08:35:18 +0000 (10:35 +0200)]
Fix check logic in extract_fa

5 years agoMerge pull request #1196 from YosysHQ/eddie/fix1178
Eddie Hung [Mon, 15 Jul 2019 20:31:08 +0000 (13:31 -0700)]
Merge pull request #1196 from YosysHQ/eddie/fix1178

Fix different synth results between with and without debug output "-g"

5 years ago$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
Eddie Hung [Mon, 15 Jul 2019 19:03:51 +0000 (12:03 -0700)]
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

5 years agoMerge pull request #1189 from YosysHQ/eddie/fix1151
Clifford Wolf [Mon, 15 Jul 2019 18:06:35 +0000 (20:06 +0200)]
Merge pull request #1189 from YosysHQ/eddie/fix1151

Error out if enable > dbits in memory_bram file