microwatt.git
5 years agodon't cross compile when on Power
Dan Horák [Sat, 24 Aug 2019 12:02:35 +0000 (14:02 +0200)]
don't cross compile when on Power

5 years agoAdd a simple hello_world example that also echos input
Anton Blanchard [Fri, 23 Aug 2019 22:59:17 +0000 (08:59 +1000)]
Add a simple hello_world example that also echos input

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #2 from olofk/fusesoc_nexys_a7
Anton Blanchard [Fri, 23 Aug 2019 19:25:48 +0000 (05:25 +1000)]
Merge pull request #2 from olofk/fusesoc_nexys_a7

Fusesoc nexys a7

5 years agoAdded synthesis target
Olof Kindgren [Fri, 23 Aug 2019 12:20:20 +0000 (14:20 +0200)]
Added synthesis target

The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1

5 years agoAdd Nexys Video support
Olof Kindgren [Fri, 23 Aug 2019 12:09:06 +0000 (14:09 +0200)]
Add Nexys Video support

5 years agoAdd FuseSoC core description file with Nexys A7 support
Olof Kindgren [Fri, 23 Aug 2019 11:32:05 +0000 (13:32 +0200)]
Add FuseSoC core description file with Nexys A7 support

5 years agoAdd constraint file for Nexys A7
Olof Kindgren [Fri, 23 Aug 2019 11:19:11 +0000 (13:19 +0200)]
Add constraint file for Nexys A7

5 years agoExpose ram init file and memory size through toplevel
Olof Kindgren [Fri, 23 Aug 2019 11:18:39 +0000 (13:18 +0200)]
Expose ram init file and memory size through toplevel

5 years agoAdd dummy clock generator
Olof Kindgren [Fri, 23 Aug 2019 11:17:35 +0000 (13:17 +0200)]
Add dummy clock generator

5 years agoAdd a few more FPGA related files
Anton Blanchard [Fri, 23 Aug 2019 06:23:53 +0000 (16:23 +1000)]
Add a few more FPGA related files

Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoInitial import of microwatt
Anton Blanchard [Thu, 22 Aug 2019 06:46:13 +0000 (16:46 +1000)]
Initial import of microwatt

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>