Use soft-logic, not LUT3 instantiation

Merge branch 'map_cells_before_map_luts' into xc7srl

synth_xilinx to map_cells before map_luts

Cleanup comments

t:$dff* -> t:$dff t:$dffe

Remove handling for $pmux, since #895

-nosrl meant when -nobram

Remove duplicate STARTUPE2

Disable shregmap in synth_xilinx if -retime

Add changelog entry

Merge pull request #913 from smunaut/fix_proc_mux

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #912 from YosysHQ/bram_addr_en

memory_bram: Consider read enable for address expansion register

Merge pull request #910 from ucb-bar/memupdates

Refine memory support to deal with general Verilog memory definitions.

memory_bram: Consider read enable for address expansion register

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #895 from YosysHQ/pmux2shiftx

RFC: Add a pmux-to-shiftx optimisation to proc_mux

Refine memory support to deal with general Verilog memory definitions.

Merge pull request #907 from YosysHQ/clifford/fix906

Build Verilog parser with -DYYMAXDEPTH=100000

Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #901 from trcwm/libertyfixes

Libertyfixes: accept superfluous ; at end of group.

Merge pull request #903 from YosysHQ/bram_reset_transp

memory_bram: Reset make_transp when growing read ports

memory_bram: Reset make_transp when growing read ports

Signed-off-by: David Shah <dave@ds0.me>

Liberty file parser now accepts superfluous ;

Liberty file parser now accepts superfluous ;

Liberty file parser now accepts superfluous ;

Add "read -verific" and "read -noverific"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "rename -output"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "rename" help message

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "cutpoint -undef"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "hdlname" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix "verific -extnets" for more complex situations

Signed-off-by: Clifford Wolf <clifford@clifford.at>

synth_xilinx to use shregmap with -minlen 3

Merge remote-tracking branch 'origin/master' into xc7srl

Add "cutpoint" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Create one $shiftx per bit in width

Merge pull request #896 from YosysHQ/transp_fixes

memory_bram: Fix multiclock make_transp

Merge pull request #897 from trcwm/libertyfixes

Liberty parser: Accept ranges [A:B], and ignore missing ';'.

spaces -> tabs

EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)

Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.

memory_bram: Fix multiclock make_transp

Signed-off-by: David Shah <dave@ds0.me>

Add a pmux-to-shiftx optimisation to proc_mux

Cope with SHREG not having E port; Revert $pmux fine tune

Add "mutate -none -mode", "mutate -mode none"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -s <filename>"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #893 from YosysHQ/clifford/btormeminit

Memory init support in write_btor

Add support for memory initialization to write_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix BTOR output tags syntax in writye_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for SHREGMAP+$mux, also fine tune $pmux

Leftover printf

Fixes for multibit

Working for 1 bit

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #889 from YosysHQ/clifford/fix888

Fix mem2reg handling of memories with upto data ports

Merge pull request #890 from YosysHQ/clifford/fix887

Trim init attributes when resizing FFs in "wreduce"

Merge pull request #891 from YosysHQ/xilinx_keep

xilinx: Add keep attribute where appropriate

xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <dave@ds0.me>

Trim init attributes when resizing FFs in "wreduce", fixes #887

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add '-nosrl' option to synth_xilinx

Fix mem2reg handling of memories with upto data ports, fixes #888

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "read_verilog -dump_vlog[12]" handling of upto ranges

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Opt

Fix spacing

Fine tune cells_map.v

Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length

Add support for variable length Xilinx SRL > 128

Restore original synth_xilinx commands

Fix spacing

shregmap -tech xilinx to delete $shiftx for var length SRL

Fix INIT for variable length SRs that have been bumped up one

Merge remote-tracking branch 'origin/master' into xc7srl

Make output port a non chain user

Merge pull request #885 from YosysHQ/clifford/fix873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #808 from eddiehung/read_aiger

Add new read_aiger frontend

Merge https://github.com/YosysHQ/yosys into read_aiger

Add author name

Merge pull request #884 from zachjs/master

fix local name resolution in prefix constructs

fix local name resolution in prefix constructs

Fix shregmap to correctly recognise non chain users; cleanup

shiftx NULL pointer check

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Cleanup

Only accept <128 for variable length, only if $shiftx exclusive

Merge pull request #877 from FelixVi/master

Add note about test requirements in README

Add note about test requirements in README

Cleanup synth_xilinx

Working

Improve mix of src/wire/wirebit coverage in "mutate -list"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #876 from YosysHQ/clifford/fmcombine

Add fmcombine pass

Add "fmcombine -fwd -bwd -nop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add fmcombine pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #875 from YosysHQ/clifford/mutate

Add "mutate" pass

Disable realmath tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "mutate" list-reduce algorithm

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -cfg", improve pick_cover behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>