Michael Nolan [Mon, 8 Jun 2020 21:19:29 +0000 (17:19 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Cole Poirier [Mon, 8 Jun 2020 21:17:28 +0000 (14:17 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08jun2020
bugzilla-daemon [Mon, 8 Jun 2020 21:03:36 +0000 (21:03 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:46:26 +0000 (21:46 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:38:10 +0000 (21:38 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:31:28 +0000 (21:31 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 20:12:13 +0000 (16:12 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Michael Nolan [Mon, 8 Jun 2020 20:11:01 +0000 (16:11 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:08:54 +0000 (21:08 +0100)]
[libre-riscv-dev] daily kan-ban update 08jun2020
Yehowshua [Mon, 8 Jun 2020 19:14:05 +0000 (15:14 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 19:09:23 +0000 (15:09 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 19:05:17 +0000 (15:05 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 19:02:37 +0000 (20:02 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Sanjay Menon [Mon, 8 Jun 2020 19:01:07 +0000 (00:31 +0530)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 18:58:02 +0000 (14:58 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 18:55:41 +0000 (19:55 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:52:51 +0000 (18:52 +0000)]
[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
Yehowshua [Mon, 8 Jun 2020 18:46:36 +0000 (14:46 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 18:34:03 +0000 (18:34 +0000)]
[libre-riscv-dev] [Bug 370] New: need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
bugzilla-daemon [Mon, 8 Jun 2020 18:31:31 +0000 (18:31 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 18:24:12 +0000 (19:24 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Sanjay Menon [Mon, 8 Jun 2020 18:03:22 +0000 (23:33 +0530)]
[libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:00:05 +0000 (18:00 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Mon, 8 Jun 2020 17:57:53 +0000 (17:57 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 17:48:46 +0000 (17:48 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 15:27:46 +0000 (16:27 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 14:28:11 +0000 (14:28 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
Lauri Kasanen [Mon, 8 Jun 2020 14:15:07 +0000 (17:15 +0300)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 14:10:44 +0000 (14:10 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
Hendrik Boom [Mon, 8 Jun 2020 13:55:54 +0000 (09:55 -0400)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 13:50:54 +0000 (13:50 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 13:42:15 +0000 (13:42 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Mon, 8 Jun 2020 12:59:34 +0000 (12:59 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Staf Verhaegen [Mon, 8 Jun 2020 12:37:29 +0000 (14:37 +0200)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 11:13:48 +0000 (12:13 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Staf Verhaegen [Mon, 8 Jun 2020 10:17:05 +0000 (12:17 +0200)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 09:40:27 +0000 (10:40 +0100)]
Re: [libre-riscv-dev] Using formal to expose bugs in scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 09:13:22 +0000 (09:13 +0000)]
[libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 09:13:22 +0000 (09:13 +0000)]
[libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
Yehowshua [Mon, 8 Jun 2020 03:18:58 +0000 (23:18 -0400)]
Re: [libre-riscv-dev] Using formal to expose bugs in scoreboard
Yehowshua [Mon, 8 Jun 2020 03:11:36 +0000 (23:11 -0400)]
[libre-riscv-dev] Using formal to expose bugs in scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 01:28:51 +0000 (01:28 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 8 Jun 2020 01:20:16 +0000 (01:20 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 8 Jun 2020 01:09:26 +0000 (01:09 +0000)]
[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 00:35:43 +0000 (01:35 +0100)]
Re: [libre-riscv-dev] "simple" core
Jacob Lifshay [Mon, 8 Jun 2020 00:29:21 +0000 (17:29 -0700)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Yehowshua [Mon, 8 Jun 2020 00:27:22 +0000 (20:27 -0400)]
Re: [libre-riscv-dev] "simple" core
Cole Poirier [Mon, 8 Jun 2020 00:10:30 +0000 (17:10 -0700)]
Re: [libre-riscv-dev] "simple" core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 00:06:19 +0000 (01:06 +0100)]
Re: [libre-riscv-dev] "simple" core
Cole Poirier [Mon, 8 Jun 2020 00:01:33 +0000 (17:01 -0700)]
Re: [libre-riscv-dev] "simple" core
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 23:58:26 +0000 (00:58 +0100)]
Re: [libre-riscv-dev] "simple" core
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 23:55:42 +0000 (00:55 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Cole Poirier [Sun, 7 Jun 2020 23:54:21 +0000 (16:54 -0700)]
Re: [libre-riscv-dev] "simple" core
bugzilla-daemon [Sun, 7 Jun 2020 23:42:53 +0000 (23:42 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Cole Poirier [Sun, 7 Jun 2020 23:42:05 +0000 (16:42 -0700)]
[libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 23:31:21 +0000 (00:31 +0100)]
[libre-riscv-dev] "simple" core
bugzilla-daemon [Sun, 7 Jun 2020 23:02:24 +0000 (23:02 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:55:38 +0000 (22:55 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 7 Jun 2020 22:48:48 +0000 (22:48 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:47:59 +0000 (22:47 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:45:21 +0000 (22:45 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 22:39:59 +0000 (22:39 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 22:39:53 +0000 (22:39 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:34:24 +0000 (22:34 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 22:34:22 +0000 (22:34 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:32:17 +0000 (22:32 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 22:31:59 +0000 (22:31 +0000)]
[libre-riscv-dev] [Bug 368] New: Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 21:39:08 +0000 (21:39 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 21:31:40 +0000 (21:31 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:23:25 +0000 (21:23 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 21:23:07 +0000 (21:23 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:18:35 +0000 (21:18 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:11:59 +0000 (21:11 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:51:52 +0000 (20:51 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:45:35 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:42:16 +0000 (20:42 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:35:32 +0000 (20:35 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 7 Jun 2020 20:31:57 +0000 (20:31 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 20:29:52 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 20:25:20 +0000 (20:25 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 20:21:27 +0000 (20:21 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 20:19:47 +0000 (20:19 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 17:52:27 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 17:41:08 +0000 (17:41 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 15:08:16 +0000 (15:08 +0000)]
[libre-riscv-dev] [Bug 360] move RS to 1st or 2nd operand in CSV files
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 15:03:39 +0000 (16:03 +0100)]
[libre-riscv-dev] daily kan-ban update 07jun2020
bugzilla-daemon [Sun, 7 Jun 2020 14:32:31 +0000 (14:32 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Sun, 7 Jun 2020 06:26:29 +0000 (06:26 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 06:11:44 +0000 (06:11 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 04:30:04 +0000 (04:30 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:47:26 +0000 (03:47 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:31:57 +0000 (03:31 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:23:45 +0000 (03:23 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 03:09:59 +0000 (03:09 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 03:03:20 +0000 (03:03 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 02:50:16 +0000 (02:50 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 02:36:42 +0000 (02:36 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
projects / libre-riscv-dev.git / log