r600g: implement fast color clears for MSAA on evergreen+

Allows MSAA colorbuffers, which have a CMASK automatically and don't
need any further special handling, to be fast cleared. Instead
of clearing the buffer, set the clear color and the CMASK to the
cleared state.

Fast clear is used only when all bound colorbuffers fulfill certain
conditions: a CMASK is required, we have to be able to create a clear
color value for the format and the texture mustn't contain multiple
images. Technically, it should be possible to support array textures
and cubemaps if all images are attached to the framebuffer,
but this does not appear to be common.

v2: fix fast clear check
v3: Marek: - disable fast clear with 128-bit formats, which are unsupported
           - set tex->dirty_level_mask in r600_clear, so that the driver knows
             the resource must be decompressed/expanded
           - return early from r600_clear if there's nothing else to do

Signed-off-by: Marek Olšák <maraeo@gmail.com>

r600g/compute: disable unused colorbuffer slots

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>

st/mesa: handle SNORM formats in generic CopyPixels path

v2: check desc->is_mixed in util_format_is_snorm

i965: NULL check depth_mt to quiet static analysis.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

llvmpipe: fix timer query if there's no bins

b04a295a4a0cd2defe352b3193b5fa79ca8fc9fc removed seemingly unnecessary
code in get_query. Turns out this code could in fact be reached - while
timestamps are always binned, if there are no bins (which happens if fb
size is 0) then the rasterization query code filling this in is still
never executed.
So fix this up by filling in some timestamp, but do it at EndQuery time
not GetQuery time which should be more appropriate.
Makes piglit arb_timer_query-timestamp-get happy again.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

clover: Don't segfault when compiling a program with no kernel

mesa: Remove unused allow_large_textures driconf from classic drivers.

This option hasn't been used since the introduction of DRI2.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove GLES 3.0 sRGB workaround.

Gen3 doesn't support GLES 3.0, so there's no need for it.

Acked-by: Eric Anholt <eric@anholt.net>

i965: Remove is_945.

Only relevant on Gen3.

Acked-by: Eric Anholt <eric@anholt.net>

i965: Delete hw_stencil flag.

This was only used by i915.

Acked-by: Eric Anholt <eric@anholt.net>

i965: Remove hw_stipple flag.

This was only used by i915.

Acked-by: Eric Anholt <eric@anholt.net>

i965: Remove use_early_z option.

This was only used by i965+.

v2: Also remove the option from the driconf list. (change by anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Remove unused SUBPIXEL_* macros.

Acked-by: Eric Anholt <eric@anholt.net>

i965: Remove redundant Gen3 PCI IDs.

Acked-by: Eric Anholt <eric@anholt.net>

intel: Remove unused INTEL_MAX_FIXUP macro.

v2: Remove it from i915, too (change by anholt)

Acked-by: Eric Anholt <eric@anholt.net>

i965: Drop i915 register/instruction definitions.

v2: Remove unused DV_PF_* macros, too. (change by Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop code for calling the empty brw_update_draw_buffers() hook.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop dead i915 blend state code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop i915-specific blit clear code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop the system-memory VBO support for i915.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop i915 swtnl code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop i915-specific vtbl entries.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop swtnl fallback code for i915.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop i915 code from intel_screen.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop #ifdef I915 code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop code checking for gen <= 3.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove a duplicated set of PCI IDs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove various remaining dead code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove dead debug flags.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove state batch emit support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Drop unused register #defines from the shared reg file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Drop 965+ GL version setup.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove gen6+ batchbuffer support.

While i915 does have hardware contexts in hardware, we don't expect there
to ever be SW support for it (given that support hasn't even made it back
to gen5 or gen4).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Drop chipset detection code for 965+ chipsets.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Drop context fields specific to 965+ chipsets.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Drop all has_llc code.

i915 never has llc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove the remainder of the batchbuffer caching.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove miscellanous uncalled gen4 code from formerly shared files.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove most of the code under gen >= 4 checks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove fake ETC support that only existed on gen4+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove separate stencil code.

This was formerly-shared code for supporting gen5+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove the I915 macro from the formerly shared code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove all the MSAA support code.

This hardware doesn't have MSAA support, so this code is all a waste for it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove all the HiZ code from i915.

v2: Remove extra struct forward declaration (change by Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: GL_EXT_shadow_funcs is not optional with GL_ARB_shadow

Every driver left in Mesa that enables one also enables the other.
There's no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_ARB_texture_storage_multisample is not optional with GL_ARB_texture_multisample

In Mesa, this extension is implemented purely in software.  Drivers may
*optionally* provide optimized paths.  If a driver enables,
GL_ARB_texture_multisample, it gets GL_ARB_texture_storage_multisample
for free.

NOTE: This has the side effect of enabling the extension in Gallium
drivers that enable GL_ARB_texture_multisample.

v2 (Ken): Still prevent multisample texture targets in TexParameter for
implementations that don't support multisampling.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_ARB_texture_storage is not optional

In Mesa, this extension is implemented purely in software.  Drivers may
*optionally* provide optimized paths.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

v2: Minor whitespace tidying (suggested by Brian).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_ARB_shading_language_100 is not optional

This extension just provides some of the most basic software framework
for GLSL.  Without GL_ARB_vertex_shader or GL_ARB_fragment_shader,
applications still cannot use GLSL.  There's no value in
conditionalizing support for this extension.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_ARB_shader_objects is not optional

This extension just provides some of the most basic software framework
for GLSL.  Without GL_ARB_vertex_shader or GL_ARB_fragment_shader,
applications still cannot use GLSL.  There's no value in
conditionalizing support for this extension.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_NV_blend_square is not optional

Every driver left in Mesa enables this extension all the time.  There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_EXT_fog_coord is not optional

Every driver left in Mesa enables this extension all the time.  There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_EXT_secondary_color is not optional

Every driver left in Mesa enables this extension all the time.  There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_EXT_framebuffer_object is not optional

Every driver left in Mesa enables this extension all the time.  There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Remove GL_MESA_resize_buffers

Commit bab755a made the implementation a no-op, and it was only ever
enabled by software rasterizers.

v2: Move the spec into docs/specs/OLD since it's now obsolete
    (squashed patch from Andreas Boll)

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Remove _mesa_{enable, disable}_extension and _mesa_extension_is_enabled

They're not used anywhere.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Just set extension flags instead of calling _mesa_enable_extension

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Remove _mesa_enable_._._extensions functions

After the preceeding commits, they are not used.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

swrast: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions

_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

osmesa: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions

_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

wmesa: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions

_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

x11: Don't call _mesa_enable_._._extensions and _mesa_enable_sw_extensions

_mesa_enable_sw_extensions enables all the extensions (and more) that
the others enable.  Also, don't duplicate the DXTn checks.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965: Merge the two GEN >= 6 extension enable blocks

There's no reason for these blocks to be separate.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move GEN >= 4 extensions into the "always on" list

This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 4 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move GEN >= 3 extensions into the "always on" list

This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 3 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: Remove GEN >= 4 extension support

This copy of the source file is only used for GEN <= 3, so remove the
dead code.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Split surface format code into a new file (brw_surface_formats.c).

brw_wm_surface_state.c has gotten rather large and unwieldy.  At this
point, it consists of two separate portions:

1. Surface format code

   This includes the giant table of surface formats and what features
   they support on each generation, as well as the code to translate
   between Mesa formats and hardware formats.

   This is used across all generations.

2. Binding table (SURFACE_STATE) related code.

   This is the code to generate SURFACE_STATE entries for renderbuffers,
   textures, transform feedback buffers, constant buffers, and so on, as
   well as the code to assemble them into binding tables.

   This is only used on Gen4-6; gen7_surface_state.c has Gen7+ code.

Since the two are logically separate, and one is reused on every
generation while the other is not, it makes a lot of sense to split
them out.  It should also make finding code easier.

No code is changed by this patch.  I simply copied the file then deleted
portions of both.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

radeonsi: add kabini pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: add bonaire pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: disable 2D tiling on CIK for now

Causes GPU hangs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: add llvm processor names for CIK

Requires updated llvm.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: emit PA_SC_RASTER_CONFIG[_1] on cik

Use the golden values for each asic.

Todo: update Kabini and Kaveri.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: PA_CL_ENHANCE is privileged on CIK

Needs to be and is set by the kernel.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: update surface sync packet emit for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: store chip class in the pm4 struct

Will be used for asic specific pm4 behavior.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: properly handle DB tiling setup on CIK

On CIK, DB switches back to using per-surface tiling
parameters rather than the tile index used on SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: emit additional shader pgm rsrc registers for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: emit TA_BC_BASE_ADDR_HI for border color on CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: register updates for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: initial PM4 changes for CIK

note which packets are removed and add new ones.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: initial support for CIK chips

Add the infrastructure to differentiate them.
Just treat them like SI for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: rename SI chip class from TAHITI to SI

Covers the entire family.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

r600g: Fix build

Broken since 2840bec56f79347b95dec5458b20d4a46d1aa445 when opencl is
disabled.

mesa: Return ZeroVec/dummyReg instead of NULL pointer

Assertions are not sufficient to check for null pointers as they don't
show up in release builds. So, return ZeroVec/dummyReg instead of NULL
pointer in get_{src,dst}_register_pointer(). This should calm down the
warnings from static analysis tool.

Note: This is a candidate for the 9.1 branch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Fix build with older gcc since update of glext.h

Reviewed-by: Brian Paul <brianp@vmware.com>

r600g/compute: Accept LDS size from the LLVM backend

And allocate the correct amount before dispatching the kernel.

Tested-by: Aaron Watry <awatry@gmail.com>

r600g/compute: Move compute_shader_create() function into evergreen_compute.c

Tested-by: Aaron Watry <awatry@gmail.com>

svga: pass svga_compile_key by reference instead of value

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: use switch statement in svga_shader_type()

Safer in case the PIPE_SHADER_x tokens get renumbered (as Marek
wanted to do).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

ilo: clean up states that use ilo_view_surface

Use variables that are easier to remember what they are.

ilo: remove ilo_cbuf_state::count

We can derive it from enabled_mask.

ilo: clean up ilo_set_constant_buffer()

Add loops that will be optimized away.

ilo: clean up states that take a start_slot

They are similar, so clean them up to make them look similar.

glsl: Initialize member variable is_ubo_var in constructor.

Fixes "Uninitialized scalar field" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

ilo: use shorter names for dirty flags

The new names match those of ilo_context's members respectively, and are
shorter.

ilo: track if primitive restart has changed

Re-emit 3DSTATE_INDEX_BUFFER to enable/disable primitive restart.

ilo: avoid potential dangling pointer dereference

Set pipe_draw_info to NULL after draw_vbo().

mesa: Remove GL_EXT_clip_volume_hint

As far as I can tell, no driver has enabled this extension since c6499a7
back in 2007.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965,i915: Return early if miptree allocation fails

If allocation fails in intel_miptree_create_layout(), don't proceed to
dereference the miptree. Return an early NULL.

Fixes static analysis error reported by Klocwork.

Note: This is a candidate for the 9.1 branch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

llvmpipe: handle offset_clamp

This was just ignored (unless for some reason like unfilled polys draw was
handling this).
I'm not convinced of that code, putting the float for the clamp in the key
isn't really a good idea. Then again the other floats for depth bias are
already in there too anyway (should probably have a jit_context for the
setup function), so this is just a quick fix.
Also, the "minimum resolvable depth difference" used isn't really right as it
should be calculated according to the z values of the current primitive
and not be a constant (of course, this only makes a difference for float
depth buffers), at least for d3d10, so depth biasing is still not quite right.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>