Eddie Hung [Mon, 30 Sep 2019 22:34:04 +0000 (15:34 -0700)]
Add quick test
Eddie Hung [Sat, 28 Sep 2019 00:44:01 +0000 (17:44 -0700)]
Add -select option to aigmap
Eddie Hung [Mon, 30 Sep 2019 22:24:03 +0000 (15:24 -0700)]
Cleanup
Eddie Hung [Mon, 30 Sep 2019 22:19:02 +0000 (15:19 -0700)]
Add comment
Eddie Hung [Sat, 28 Sep 2019 00:00:19 +0000 (17:00 -0700)]
Fix typo
Eddie Hung [Mon, 30 Sep 2019 21:52:04 +0000 (14:52 -0700)]
Fix for svinterfaces
Eddie Hung [Mon, 30 Sep 2019 21:11:01 +0000 (14:11 -0700)]
module->derive() to be lazy and not touch ast if already derived
Eddie Hung [Mon, 30 Sep 2019 20:21:07 +0000 (13:21 -0700)]
Use a cell_cache to instantiate once rather than opt_merge call
Eddie Hung [Mon, 30 Sep 2019 19:57:19 +0000 (12:57 -0700)]
scc call on active module module only, plus cleanup
Eddie Hung [Mon, 30 Sep 2019 19:34:28 +0000 (12:34 -0700)]
Use derived module
Eddie Hung [Mon, 30 Sep 2019 19:29:35 +0000 (12:29 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 30 Sep 2019 17:59:56 +0000 (10:59 -0700)]
Update doc for equiv_opt
whitequark [Mon, 30 Sep 2019 17:38:20 +0000 (17:38 +0000)]
Merge pull request #1406 from whitequark/connect_rpc
rpc: new frontend
Eddie Hung [Mon, 30 Sep 2019 17:31:57 +0000 (10:31 -0700)]
Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
Generate Python wrappers for inline constructors
whitequark [Thu, 26 Sep 2019 03:57:16 +0000 (03:57 +0000)]
rpc: new frontend.
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
whitequark [Thu, 26 Sep 2019 02:11:22 +0000 (02:11 +0000)]
libs: import json11.
This commit imports the code from upstream commit
dropbox/json11@
8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
Miodrag Milanović [Mon, 30 Sep 2019 15:49:23 +0000 (17:49 +0200)]
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
Open aig frontend as binary file
Clifford Wolf [Mon, 30 Sep 2019 15:08:38 +0000 (17:08 +0200)]
Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 30 Sep 2019 15:04:21 +0000 (17:04 +0200)]
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
equiv_opt to call async2sync when not -multiclock like SymbiYosys
Clifford Wolf [Mon, 30 Sep 2019 15:04:03 +0000 (17:04 +0200)]
Merge pull request #1417 from YosysHQ/clifford/fixasync2sync
Fix $dlatch handling in async2sync
Clifford Wolf [Mon, 30 Sep 2019 12:58:23 +0000 (14:58 +0200)]
Fix $dlatch handling in async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 27 Sep 2019 19:50:20 +0000 (12:50 -0700)]
Add latch test modified from #1363
Eddie Hung [Fri, 27 Sep 2019 19:49:57 +0000 (12:49 -0700)]
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Marcin Kościelnicki [Mon, 23 Sep 2019 10:41:42 +0000 (12:41 +0200)]
synth_xilinx: Support latches, remove used-up FF init values.
Fixes #1387.
Eddie Hung [Mon, 30 Sep 2019 04:55:53 +0000 (21:55 -0700)]
Missing endmodule
Eddie Hung [Mon, 30 Sep 2019 02:39:12 +0000 (19:39 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 30 Sep 2019 02:35:23 +0000 (19:35 -0700)]
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
Avoid work in replace() if rules empty.
Eddie Hung [Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)]
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Eddie Hung [Sun, 29 Sep 2019 18:25:34 +0000 (11:25 -0700)]
FDCE_1 does not have IS_CLR_INVERTED
Eddie Hung [Sun, 29 Sep 2019 16:58:00 +0000 (09:58 -0700)]
Fix "scc" call inside abc9 to consider all wires
Eddie Hung [Sun, 29 Sep 2019 16:21:51 +0000 (09:21 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Miodrag Milanovic [Sun, 29 Sep 2019 13:40:37 +0000 (15:40 +0200)]
Fix reading aig files on windows
Miodrag Milanovic [Sun, 29 Sep 2019 11:22:11 +0000 (13:22 +0200)]
Open aig frontend as binary file
Miodrag Milanović [Sun, 29 Sep 2019 08:37:34 +0000 (10:37 +0200)]
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
Support binary files for backends, fixes #1407
Clifford Wolf [Sun, 29 Sep 2019 08:36:25 +0000 (10:36 +0200)]
Merge pull request #1411 from aman-goel/YosysHQ-master
Corrects BTOR2 backend
Henner Zeller [Sun, 29 Sep 2019 07:17:40 +0000 (00:17 -0700)]
Avoid work in replace() if rules empty.
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
Eddie Hung [Sun, 29 Sep 2019 06:48:17 +0000 (23:48 -0700)]
Big rework; flop info now mostly in cells_sim.v
Miodrag Milanovic [Sat, 28 Sep 2019 07:50:29 +0000 (09:50 +0200)]
Add aiger and protobuf backends binary support
Miodrag Milanovic [Sat, 28 Sep 2019 07:28:51 +0000 (09:28 +0200)]
Support binary files for backends, fixes #1407
Eddie Hung [Sat, 28 Sep 2019 01:49:45 +0000 (18:49 -0700)]
Fix box name
Eddie Hung [Sat, 28 Sep 2019 01:41:43 +0000 (18:41 -0700)]
Use abc_mergeability attr for "r" extension
Eddie Hung [Sat, 28 Sep 2019 01:41:04 +0000 (18:41 -0700)]
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
Eddie Hung [Sat, 28 Sep 2019 00:45:49 +0000 (17:45 -0700)]
Fix infinite recursion
Eddie Hung [Sat, 28 Sep 2019 00:44:01 +0000 (17:44 -0700)]
Add -select option to aigmap
Eddie Hung [Sat, 28 Sep 2019 00:00:19 +0000 (17:00 -0700)]
Fix typo
Eddie Hung [Fri, 27 Sep 2019 22:14:31 +0000 (15:14 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Fri, 27 Sep 2019 21:32:07 +0000 (14:32 -0700)]
Re-order
Eddie Hung [Fri, 27 Sep 2019 21:21:47 +0000 (14:21 -0700)]
Missing (* mul2dsp *) for sliceB
Eddie Hung [Fri, 27 Sep 2019 19:59:10 +0000 (12:59 -0700)]
equiv_opt to call async2sync when not -multiclock like SymbiYosys
Eddie Hung [Fri, 27 Sep 2019 18:57:53 +0000 (11:57 -0700)]
Ooops AREG and BREG to default to -1
Aman Goel [Fri, 27 Sep 2019 16:40:17 +0000 (12:40 -0400)]
Corrects btor2 backend
Marcin Kościelnicki [Fri, 27 Sep 2019 09:03:04 +0000 (11:03 +0200)]
Fix _TECHMAP_REMOVEINIT_ handling.
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396.
Aman Goel [Fri, 27 Sep 2019 16:30:27 +0000 (12:30 -0400)]
Merge pull request #7 from YosysHQ/master
Syncing with official repo
Miodrag Milanović [Fri, 27 Sep 2019 15:37:55 +0000 (17:37 +0200)]
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt_difference
Change order of parameters, to work on other OS
Miodrag Milanovic [Fri, 27 Sep 2019 09:31:55 +0000 (11:31 +0200)]
Change order of parameters, to work on other os
Clifford Wolf [Fri, 27 Sep 2019 07:57:28 +0000 (09:57 +0200)]
Merge pull request #1404 from YosysHQ/fix_gzip_macos
Make read/write gzip files on macos works, fixes #1357
Eddie Hung [Thu, 26 Sep 2019 21:31:02 +0000 (14:31 -0700)]
Update doc with max cascade chain of 20
Eddie Hung [Thu, 26 Sep 2019 20:59:05 +0000 (13:59 -0700)]
Do not always zero out C (e.g. during cascade breaks)
Eddie Hung [Thu, 26 Sep 2019 20:44:41 +0000 (13:44 -0700)]
Update doc
Eddie Hung [Thu, 26 Sep 2019 20:40:38 +0000 (13:40 -0700)]
Zero out ports
Eddie Hung [Thu, 26 Sep 2019 20:29:18 +0000 (13:29 -0700)]
xilinx_dsp_cascade to also cascade AREG and BREG
Eddie Hung [Thu, 26 Sep 2019 19:09:57 +0000 (12:09 -0700)]
Try recursive pmgen for P cascade
Eddie Hung [Thu, 26 Sep 2019 18:13:08 +0000 (11:13 -0700)]
Missing an '&'
Eddie Hung [Thu, 26 Sep 2019 17:45:14 +0000 (10:45 -0700)]
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
Miodrag Milanovic [Thu, 26 Sep 2019 17:35:12 +0000 (19:35 +0200)]
Make read/write gzip files on macos works, fixes #1357
Eddie Hung [Thu, 26 Sep 2019 17:34:14 +0000 (10:34 -0700)]
Typo
Eddie Hung [Thu, 26 Sep 2019 17:32:01 +0000 (10:32 -0700)]
CREG to check for \keep
Eddie Hung [Thu, 26 Sep 2019 17:31:55 +0000 (10:31 -0700)]
Remove newline
Eddie Hung [Thu, 26 Sep 2019 17:15:05 +0000 (10:15 -0700)]
select once
Eddie Hung [Thu, 26 Sep 2019 16:57:11 +0000 (09:57 -0700)]
Stop trying to be too smart by prematurely optimising
Eddie Hung [Thu, 26 Sep 2019 05:58:55 +0000 (22:58 -0700)]
mul2dsp.v slice names
Eddie Hung [Thu, 26 Sep 2019 05:58:03 +0000 (22:58 -0700)]
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
Eddie Hung [Thu, 26 Sep 2019 01:21:08 +0000 (18:21 -0700)]
Reject if (* init *) present
Eddie Hung [Thu, 26 Sep 2019 00:26:47 +0000 (17:26 -0700)]
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung [Thu, 26 Sep 2019 00:25:44 +0000 (17:25 -0700)]
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
This reverts commit
234738b103d4f2b3d937ed928fd89bc4e31627f1.
Eddie Hung [Thu, 26 Sep 2019 00:24:11 +0000 (17:24 -0700)]
Revert "No need for $__mul anymore?"
This reverts commit
1d875ac76a354f654f28b9632d83f6b43542e827.
Eddie Hung [Thu, 26 Sep 2019 00:22:30 +0000 (17:22 -0700)]
Rework xilinx_dsp postAdd for new wreduce call
Eddie Hung [Thu, 26 Sep 2019 00:22:04 +0000 (17:22 -0700)]
Only wreduce on t:$add
Eddie Hung [Wed, 25 Sep 2019 23:51:31 +0000 (16:51 -0700)]
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung [Wed, 25 Sep 2019 23:45:51 +0000 (16:45 -0700)]
Fix memory issue since SigSpec& could be invalidated
Eddie Hung [Wed, 25 Sep 2019 23:43:24 +0000 (16:43 -0700)]
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
ICE40 tests. adffs test update (equiv_opt -multiclock).
Eddie Hung [Wed, 25 Sep 2019 21:06:21 +0000 (14:06 -0700)]
No need for $__mul anymore?
Eddie Hung [Wed, 25 Sep 2019 21:05:59 +0000 (14:05 -0700)]
unextend only used in init
Eddie Hung [Wed, 25 Sep 2019 21:04:36 +0000 (14:04 -0700)]
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung [Wed, 25 Sep 2019 17:33:16 +0000 (10:33 -0700)]
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
SergeyDegtyar [Wed, 25 Sep 2019 11:43:26 +0000 (14:43 +0300)]
Change sync controls to async.
Clifford Wolf [Wed, 25 Sep 2019 07:20:54 +0000 (09:20 +0200)]
Merge pull request #1402 from YosysHQ/clifford/portlist
Add "portlist" command
Clifford Wolf [Wed, 25 Sep 2019 07:20:38 +0000 (09:20 +0200)]
Improve "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 24 Sep 2019 16:08:59 +0000 (18:08 +0200)]
Add "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
SergeyDegtyar [Tue, 24 Sep 2019 11:55:32 +0000 (14:55 +0300)]
adffs test update (equiv_opt -multiclock).
Eddie Hung [Tue, 24 Sep 2019 05:02:22 +0000 (22:02 -0700)]
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung [Tue, 24 Sep 2019 04:58:40 +0000 (21:58 -0700)]
"abc_padding" attr for blackbox outputs that were padded, remove them later
Eddie Hung [Tue, 24 Sep 2019 04:58:04 +0000 (21:58 -0700)]
Force $inout.out ports to begin with '$' to indicate internal
Eddie Hung [Tue, 24 Sep 2019 04:56:28 +0000 (21:56 -0700)]
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Add a xilinx_finalise pass"
This reverts commit
23d90e0439ffef510632ce45a3d2aff1c129f405.
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
This reverts commit
67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
Eddie Hung [Tue, 24 Sep 2019 02:52:54 +0000 (19:52 -0700)]
Revert "Vivado does not like zero width port connections"
This reverts commit
895e2befa76bd326cc47fd40de112ea067fcaf98.
Eddie Hung [Tue, 24 Sep 2019 02:04:07 +0000 (19:04 -0700)]
Vivado does not like zero width port connections
Eddie Hung [Tue, 24 Sep 2019 01:56:18 +0000 (18:56 -0700)]
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung [Tue, 24 Sep 2019 01:56:02 +0000 (18:56 -0700)]
Add a xilinx_finalise pass