yosys.git
5 years agoMerge pull request #821 from eddiehung/dff_init
Clifford Wolf [Thu, 21 Feb 2019 17:46:58 +0000 (18:46 +0100)]
Merge pull request #821 from eddiehung/dff_init

Revert "Add -B option to autotest.sh to append to backend_opts"

5 years agoRevert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung [Thu, 21 Feb 2019 17:22:29 +0000 (09:22 -0800)]
Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.

5 years agoMerge pull request #817 from eddiehung/dff_init
Eddie Hung [Thu, 21 Feb 2019 01:26:56 +0000 (17:26 -0800)]
Merge pull request #817 from eddiehung/dff_init

Cleanup #805

5 years agoRemove simple_defparam tests
Eddie Hung [Wed, 20 Feb 2019 23:45:45 +0000 (15:45 -0800)]
Remove simple_defparam tests

5 years agoMerge pull request #805 from eddiehung/dff_init
Eddie Hung [Tue, 19 Feb 2019 20:32:40 +0000 (12:32 -0800)]
Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

5 years agoInstead of INIT param on cells, use initial statement with hier ref as
Eddie Hung [Sun, 17 Feb 2019 20:18:12 +0000 (12:18 -0800)]
Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf

5 years agoRevert "Add INIT parameter to all ff/latch cells"
Eddie Hung [Sun, 17 Feb 2019 20:11:52 +0000 (12:11 -0800)]
Revert "Add INIT parameter to all ff/latch cells"

This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.

5 years agoMerge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung [Sun, 17 Feb 2019 19:49:06 +0000 (11:49 -0800)]
Merge https://github.com/YosysHQ/yosys into dff_init

5 years agoMerge pull request #811 from ucb-bar/firrtlfixes
Clifford Wolf [Sun, 17 Feb 2019 10:39:14 +0000 (11:39 +0100)]
Merge pull request #811 from ucb-bar/firrtlfixes

Update cells supported for verilog to FIRRTL conversion.

5 years agoRemoved unused variables, functions.
Jim Lawson [Fri, 15 Feb 2019 20:00:28 +0000 (12:00 -0800)]
Removed unused variables, functions.

5 years agoAppend (instead of over-writing) EXTRA_FLAGS
Jim Lawson [Fri, 15 Feb 2019 19:56:51 +0000 (11:56 -0800)]
Append (instead of over-writing) EXTRA_FLAGS

5 years agoUpdate cells supported for verilog to FIRRTL conversion.
Jim Lawson [Fri, 15 Feb 2019 19:14:17 +0000 (11:14 -0800)]
Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.

5 years agoFix sign handling of real constants
Clifford Wolf [Wed, 13 Feb 2019 11:36:47 +0000 (12:36 +0100)]
Fix sign handling of real constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #802 from whitequark/write_verilog_async_mem_ports
Clifford Wolf [Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)]
Merge pull request #802 from whitequark/write_verilog_async_mem_ports

write_verilog: correctly emit asynchronous transparent ports

5 years agoMerge pull request #806 from daveshah1/fsm_opt_no_reset
Clifford Wolf [Tue, 12 Feb 2019 13:39:39 +0000 (14:39 +0100)]
Merge pull request #806 from daveshah1/fsm_opt_no_reset

fsm_opt: Fix runtime error for FSMs without a reset state

5 years agofsm_opt: Fix runtime error for FSMs without a reset state
David Shah [Thu, 7 Feb 2019 10:35:36 +0000 (10:35 +0000)]
fsm_opt: Fix runtime error for FSMs without a reset state

Signed-off-by: David Shah <dave@ds0.me>
5 years agoCope WIDTH of ff/latch cells is default of zero
Eddie Hung [Wed, 6 Feb 2019 23:51:12 +0000 (15:51 -0800)]
Cope WIDTH of ff/latch cells is default of zero

5 years agoRemove check for cell->name[0] == '$'
Eddie Hung [Wed, 6 Feb 2019 22:53:40 +0000 (14:53 -0800)]
Remove check for cell->name[0] == '$'

5 years agoRefactor
Eddie Hung [Wed, 6 Feb 2019 22:28:44 +0000 (14:28 -0800)]
Refactor

5 years agowrite_verilog to cope with init attr on q when -noexpr
Eddie Hung [Wed, 6 Feb 2019 22:17:09 +0000 (14:17 -0800)]
write_verilog to cope with init attr on q when -noexpr

5 years agoAdd INIT parameter to all ff/latch cells
Eddie Hung [Wed, 6 Feb 2019 22:16:26 +0000 (14:16 -0800)]
Add INIT parameter to all ff/latch cells

5 years agoAdd tests for simple cases using defparam
Eddie Hung [Wed, 6 Feb 2019 22:15:17 +0000 (14:15 -0800)]
Add tests for simple cases using defparam

5 years agoAdd -B option to autotest.sh to append to backend_opts
Eddie Hung [Wed, 6 Feb 2019 22:14:55 +0000 (14:14 -0800)]
Add -B option to autotest.sh to append to backend_opts

5 years agoExtend testcase
Eddie Hung [Wed, 6 Feb 2019 22:02:11 +0000 (14:02 -0800)]
Extend testcase

5 years agoAdd testcase
Eddie Hung [Wed, 6 Feb 2019 20:49:30 +0000 (12:49 -0800)]
Add testcase

5 years agoAdd missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id...
Clifford Wolf [Wed, 6 Feb 2019 15:35:59 +0000 (16:35 +0100)]
Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agowrite_verilog: correctly emit asynchronous transparent ports.
whitequark [Tue, 29 Jan 2019 02:24:00 +0000 (02:24 +0000)]
write_verilog: correctly emit asynchronous transparent ports.

This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.

5 years agoMerge pull request #798 from mmicko/master
Clifford Wolf [Sun, 27 Jan 2019 08:25:18 +0000 (09:25 +0100)]
Merge pull request #798 from mmicko/master

Fixed Anlogic simulation model

5 years agoMerge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf [Sun, 27 Jan 2019 08:23:41 +0000 (09:23 +0100)]
Merge pull request #800 from whitequark/write_verilog_tribuf

write_verilog: write $tribuf cell as ternary

5 years agoMerge branch 'whitequark-write_verilog_keyword'
Clifford Wolf [Sun, 27 Jan 2019 08:17:29 +0000 (09:17 +0100)]
Merge branch 'whitequark-write_verilog_keyword'

5 years agoRemove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf [Sun, 27 Jan 2019 08:17:02 +0000 (09:17 +0100)]
Remove asicworld tests for (unsupported) switch-level modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agowrite_verilog: write $tribuf cell as ternary.
whitequark [Sun, 27 Jan 2019 00:21:31 +0000 (00:21 +0000)]
write_verilog: write $tribuf cell as ternary.

5 years agowrite_verilog: escape names that match SystemVerilog keywords.
whitequark [Sat, 26 Jan 2019 23:55:46 +0000 (23:55 +0000)]
write_verilog: escape names that match SystemVerilog keywords.

5 years agoMerge pull request #796 from whitequark/proc_clean_typo
David Shah [Fri, 25 Jan 2019 21:33:06 +0000 (21:33 +0000)]
Merge pull request #796 from whitequark/proc_clean_typo

proc_clean: fix critical typo

5 years agoFixed Anlogic simulation model
Miodrag Milanovic [Fri, 25 Jan 2019 18:25:25 +0000 (19:25 +0100)]
Fixed Anlogic simulation model

5 years agoproc_clean: fix critical typo.
whitequark [Wed, 23 Jan 2019 22:08:38 +0000 (22:08 +0000)]
proc_clean: fix critical typo.

5 years agoMerge pull request #793 from whitequark/proc_clean_fix_fully_def
Clifford Wolf [Sat, 19 Jan 2019 08:31:17 +0000 (09:31 +0100)]
Merge pull request #793 from whitequark/proc_clean_fix_fully_def

proc_clean: fix fully def check to consider compare/signal length

5 years agoproc_clean: fix fully def check to consider compare/signal length.
whitequark [Fri, 18 Jan 2019 23:22:02 +0000 (23:22 +0000)]
proc_clean: fix fully def check to consider compare/signal length.

Fixes #790.

5 years agoCleanups in igloo2 example design
Clifford Wolf [Thu, 17 Jan 2019 13:54:04 +0000 (14:54 +0100)]
Cleanups in igloo2 example design

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd SF2 IO buffer insertion
Clifford Wolf [Thu, 17 Jan 2019 13:38:37 +0000 (14:38 +0100)]
Add SF2 IO buffer insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove Igloo2 example
Clifford Wolf [Thu, 17 Jan 2019 12:35:52 +0000 (13:35 +0100)]
Improve Igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf [Thu, 17 Jan 2019 12:33:45 +0000 (13:33 +0100)]
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "write_edif -gndvccy"
Clifford Wolf [Thu, 17 Jan 2019 12:33:11 +0000 (13:33 +0100)]
Add "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd optional nullstr argument to log_id()
Clifford Wolf [Sun, 13 Jan 2019 16:00:58 +0000 (17:00 +0100)]
Add optional nullstr argument to log_id()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of $shiftx in Verilog back-end
Clifford Wolf [Tue, 15 Jan 2019 09:55:27 +0000 (10:55 +0100)]
Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #788 from whitequark/master
Clifford Wolf [Tue, 15 Jan 2019 08:52:01 +0000 (09:52 +0100)]
Merge pull request #788 from whitequark/master

Document $tribuf and some gates

5 years agoMerge pull request #787 from whitequark/flowmap_relax
Clifford Wolf [Tue, 15 Jan 2019 08:50:58 +0000 (09:50 +0100)]
Merge pull request #787 from whitequark/flowmap_relax

flowmap: implement depth relaxation

5 years agomanual: document some gates.
whitequark [Mon, 14 Jan 2019 16:17:25 +0000 (16:17 +0000)]
manual: document some gates.

5 years agomanual: explain $tribuf cell.
whitequark [Mon, 14 Jan 2019 16:08:58 +0000 (16:08 +0000)]
manual: explain $tribuf cell.

5 years agoImprove igloo2 example
Clifford Wolf [Tue, 8 Jan 2019 19:16:36 +0000 (20:16 +0100)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoflowmap: clean up terminology.
whitequark [Tue, 8 Jan 2019 02:05:06 +0000 (02:05 +0000)]
flowmap: clean up terminology.

  * "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.

5 years agoflowmap: implement depth relaxation.
whitequark [Fri, 4 Jan 2019 13:06:51 +0000 (13:06 +0000)]
flowmap: implement depth relaxation.

5 years agoFix typo in manual
Clifford Wolf [Mon, 7 Jan 2019 09:07:28 +0000 (10:07 +0100)]
Fix typo in manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in $memrd sharing
Clifford Wolf [Mon, 7 Jan 2019 09:01:11 +0000 (10:01 +0100)]
Bugfix in $memrd sharing

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #782 from whitequark/flowmap_dfs
Clifford Wolf [Mon, 7 Jan 2019 08:47:57 +0000 (09:47 +0100)]
Merge pull request #782 from whitequark/flowmap_dfs

 flowmap: construct a max-volume max-flow min-cut, not just any one

5 years agoSwitch "bugpoint" from system() to run_command()
Clifford Wolf [Mon, 7 Jan 2019 08:45:21 +0000 (09:45 +0100)]
Switch "bugpoint" from system() to run_command()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #783 from whitequark/bugpoint
Clifford Wolf [Mon, 7 Jan 2019 08:42:17 +0000 (09:42 +0100)]
Merge pull request #783 from whitequark/bugpoint

bugpoint: new pass

5 years agobugpoint: new pass.
whitequark [Mon, 7 Jan 2019 00:11:49 +0000 (00:11 +0000)]
bugpoint: new pass.

A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)

5 years agoflowmap: construct a max-volume max-flow min-cut, not just any one.
whitequark [Sun, 6 Jan 2019 19:51:37 +0000 (19:51 +0000)]
flowmap: construct a max-volume max-flow min-cut, not just any one.

5 years agoMerge pull request #780 from phire/rename_from_wire
Clifford Wolf [Sun, 6 Jan 2019 10:35:31 +0000 (11:35 +0100)]
Merge pull request #780 from phire/rename_from_wire

Rename cells based on the wires they drive.

5 years agoRename cells based on the wires they drive.
Scott Mansell [Sun, 6 Jan 2019 01:40:10 +0000 (14:40 +1300)]
Rename cells based on the wires they drive.

5 years agoAdd skeleton Yosys-Libero igloo2 example project
Clifford Wolf [Sat, 5 Jan 2019 16:02:01 +0000 (17:02 +0100)]
Add skeleton Yosys-Libero igloo2 example project

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in Verilog string handling
Clifford Wolf [Sat, 5 Jan 2019 11:10:24 +0000 (12:10 +0100)]
Bugfix in Verilog string handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoflowmap: add -minlut option, to allow postprocessing with opt_lut.
whitequark [Fri, 4 Jan 2019 21:18:03 +0000 (21:18 +0000)]
flowmap: add -minlut option, to allow postprocessing with opt_lut.

5 years agoMerge pull request #777 from mmicko/achronix_cell_sim_fix
Clifford Wolf [Fri, 4 Jan 2019 14:18:18 +0000 (15:18 +0100)]
Merge pull request #777 from mmicko/achronix_cell_sim_fix

Fix cells_sim.v for Achronix FPGA

5 years agoFix cells_sim.v for Achronix FPGA
Miodrag Milanovic [Fri, 4 Jan 2019 14:15:23 +0000 (15:15 +0100)]
Fix cells_sim.v for Achronix FPGA

5 years agoRemove -m32 Verific eval lib build instructions
Clifford Wolf [Fri, 4 Jan 2019 14:03:29 +0000 (15:03 +0100)]
Remove -m32 Verific eval lib build instructions

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #776 from mmicko/unify_noflatten
Clifford Wolf [Fri, 4 Jan 2019 13:56:04 +0000 (14:56 +0100)]
Merge pull request #776 from mmicko/unify_noflatten

Unify usage of noflatten among architectures

5 years agoUpdate Verific default path
Clifford Wolf [Fri, 4 Jan 2019 13:44:35 +0000 (14:44 +0100)]
Update Verific default path

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoflowmap: cleanup for clarity. NFCI.
whitequark [Fri, 4 Jan 2019 04:54:20 +0000 (04:54 +0000)]
flowmap: cleanup for clarity. NFCI.

5 years agoUnify usage of noflatten among architectures
Miodrag Milanovic [Fri, 4 Jan 2019 10:37:25 +0000 (11:37 +0100)]
Unify usage of noflatten among architectures

5 years agoflowmap: improve debug graph output. NFC.
whitequark [Fri, 4 Jan 2019 02:46:27 +0000 (02:46 +0000)]
flowmap: improve debug graph output. NFC.

5 years agoflowmap: add link to longer version of paper. NFC.
whitequark [Fri, 4 Jan 2019 02:33:10 +0000 (02:33 +0000)]
flowmap: add link to longer version of paper. NFC.

5 years agoMerge pull request #775 from whitequark/opt_flowmap
Clifford Wolf [Thu, 3 Jan 2019 16:03:18 +0000 (17:03 +0100)]
Merge pull request #775 from whitequark/opt_flowmap

flowmap: new techmap pass

5 years agoflowmap: new techmap pass.
whitequark [Wed, 2 Jan 2019 14:09:53 +0000 (14:09 +0000)]
flowmap: new techmap pass.

5 years agoMerge pull request #770 from whitequark/opt_expr_cmp
Clifford Wolf [Wed, 2 Jan 2019 16:34:04 +0000 (17:34 +0100)]
Merge pull request #770 from whitequark/opt_expr_cmp

opt_expr: refactor and improve simplification of comparisons

5 years agoopt_expr: improve simplification of comparisons with large constants.
whitequark [Wed, 2 Jan 2019 05:04:28 +0000 (05:04 +0000)]
opt_expr: improve simplification of comparisons with large constants.

The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.

5 years agoMerge pull request #755 from Icenowy/anlogic-dram-init
Clifford Wolf [Wed, 2 Jan 2019 15:28:18 +0000 (16:28 +0100)]
Merge pull request #755 from Icenowy/anlogic-dram-init

anlogic: implement DRAM initialization

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Wed, 2 Jan 2019 14:53:50 +0000 (15:53 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoMerge pull request #750 from Icenowy/anlogic-ff-init
Clifford Wolf [Wed, 2 Jan 2019 14:52:22 +0000 (15:52 +0100)]
Merge pull request #750 from Icenowy/anlogic-ff-init

Initialization of Anlogic DFFs

5 years agoMerge pull request #773 from whitequark/opt_lut_elim_fixes
Clifford Wolf [Wed, 2 Jan 2019 14:45:29 +0000 (15:45 +0100)]
Merge pull request #773 from whitequark/opt_lut_elim_fixes

opt_lut: elimination fixes

5 years agoMerge pull request #772 from whitequark/synth_lut
Clifford Wolf [Wed, 2 Jan 2019 14:44:57 +0000 (15:44 +0100)]
Merge pull request #772 from whitequark/synth_lut

synth: add k-LUT mode

5 years agoMerge pull request #771 from whitequark/techmap_cmp2lut
Clifford Wolf [Wed, 2 Jan 2019 14:43:10 +0000 (15:43 +0100)]
Merge pull request #771 from whitequark/techmap_cmp2lut

cmp2lut: new techmap pass

5 years agoImprove VerificImporter support for writes to asymmetric memories
Clifford Wolf [Wed, 2 Jan 2019 14:33:43 +0000 (15:33 +0100)]
Improve VerificImporter support for writes to asymmetric memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix VerificImporter asymmetric memories error message
Clifford Wolf [Wed, 2 Jan 2019 14:05:23 +0000 (15:05 +0100)]
Fix VerificImporter asymmetric memories error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #769 from whitequark/typos
Clifford Wolf [Wed, 2 Jan 2019 13:47:18 +0000 (14:47 +0100)]
Merge pull request #769 from whitequark/typos

Fix typographical and grammatical errors and inconsistencies

5 years agoFix typographical and grammatical errors and inconsistencies.
whitequark [Fri, 7 Dec 2018 19:14:07 +0000 (19:14 +0000)]
Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.

5 years agoopt_lut: reflect changes in sigmap.
whitequark [Wed, 2 Jan 2019 10:21:58 +0000 (10:21 +0000)]
opt_lut: reflect changes in sigmap.

Otherwise, some LUTs will be missed during elimination.

5 years agoopt_lut: use a worklist, and revisit cells affected by elimination.
whitequark [Wed, 2 Jan 2019 09:36:32 +0000 (09:36 +0000)]
opt_lut: use a worklist, and revisit cells affected by elimination.

5 years agoopt_lut: count eliminated cells, and set opt.did_something for them.
whitequark [Wed, 2 Jan 2019 08:40:01 +0000 (08:40 +0000)]
opt_lut: count eliminated cells, and set opt.did_something for them.

5 years agosynth_ice40: use 4-LUT coarse synthesis mode.
whitequark [Wed, 2 Jan 2019 08:25:55 +0000 (08:25 +0000)]
synth_ice40: use 4-LUT coarse synthesis mode.

5 years agosynth: add k-LUT mode.
whitequark [Wed, 2 Jan 2019 08:25:03 +0000 (08:25 +0000)]
synth: add k-LUT mode.

5 years agosynth: improve script documentation. NFC.
whitequark [Wed, 2 Jan 2019 08:05:44 +0000 (08:05 +0000)]
synth: improve script documentation. NFC.

5 years agocmp2lut: new techmap pass.
whitequark [Wed, 2 Jan 2019 07:53:31 +0000 (07:53 +0000)]
cmp2lut: new techmap pass.

5 years agoopt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
whitequark [Wed, 2 Jan 2019 04:31:20 +0000 (04:31 +0000)]
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.

5 years agoopt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
whitequark [Wed, 2 Jan 2019 03:01:25 +0000 (03:01 +0000)]
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.

5 years agoopt_expr: simplify any unsigned comparisons with all-0 and all-1.
whitequark [Wed, 2 Jan 2019 02:45:49 +0000 (02:45 +0000)]
opt_expr: simplify any unsigned comparisons with all-0 and all-1.

Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.

5 years agoMerge pull request #768 from whitequark/opt_lut_elim
Clifford Wolf [Tue, 1 Jan 2019 10:13:48 +0000 (11:13 +0100)]
Merge pull request #768 from whitequark/opt_lut_elim

opt_lut: eliminate LUTs evaluating to constants or inputs

5 years agoopt_lut: eliminate LUTs evaluating to constants or inputs.
whitequark [Mon, 31 Dec 2018 23:53:23 +0000 (23:53 +0000)]
opt_lut: eliminate LUTs evaluating to constants or inputs.

5 years agoFix handling of (* keep *) wires in wreduce
Clifford Wolf [Mon, 31 Dec 2018 15:34:27 +0000 (16:34 +0100)]
Fix handling of (* keep *) wires in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>